TM4C1233H6PGE: ESD Changing the State of GPIOs

Andrew Worwood

Part Number: TM4C1233H6PGE

I have a system that uses the TM4C family of processors(specifically TM4C1233H6PGE) and we are seeing some strange behavior during our ESD testing. We are seeing GPIOs go into some sort of pseudo latch up. A gpio that is configured as an output and set high, or an input, will go low to around 1V. The outputs can be recovered to the high state only by asserting them low first and then high again. If there are in this weird 'low' state and we just assert them high, they will stay in the same weird low state. We have added ESD protection to the GPIO that we observed this happening on, but that hasnt fixed the problem. We even added some TVS diodes to the power rail for the processor and that hasnt helped either. The processor is properly decoupled. Have you ever seen anything like this, and do you know how to fix it?

over 1 year ago

+1 Charles Tsai over 1 year ago

TI__Guru**** 191486 points

Hi,

I think you are hitting GPIO#10 errata. https://www.ti.com/lit/pdf/spmz849. Please limit the IO slew rate as suggested in the workaround.

0 Andrew Worwood over 1 year ago in reply to Charles Tsai

Prodigy 80 points

So does this mean that any ESD event can cause any GPIO to go into a low resistance state? Also, We have seen some similar behavior on the USB pins. Could this same issue be effecting the USB behavior, and if so how could we fix that? My understanding is that it would be very bad practice to add a ferrite on the usb data lines.

0 Charles Tsai over 1 year ago in reply to Andrew Worwood

TI__Guru**** 191486 points

Andrew Worwood said:
So does this mean that any ESD event can cause any GPIO to go into a low resistance state?

Hi Andrew,

Yes, a fast ESD event can cause the errata to occur. You added ESD protection but that does not decrease the slew rate but only eliminate spikes.

Andrew Worwood said:
We have seen some similar behavior on the USB pins.

The DP/DM are differential data pin for USB. The errata will not apply.

Andrew Worwood said:
My understanding is that it would be very bad practice to add a ferrite on the usb data lines.

Please refer to the best practices for USB in this System Design Guideline for TM4C123. https://www.ti.com/lit/pdf/spma059

0 Andrew Worwood over 1 year ago in reply to Charles Tsai

Prodigy 80 points

Charles Tsai said:
The DP/DM are differential data pin for USB. The errata will not apply.

Would you be able to explain why this would not be effected by the errata? When an ESD event occurs both DP and DM lines would be coupling in noise from the ESD event with very fast slew rate. The differential nature of the usb data lines would mean that the data shouldn't be corrupted by the noise, but the high slew rate is still there.

0 Charles Tsai over 1 year ago in reply to Andrew Worwood

TI__Guru**** 191486 points

Hi Andrew,

I don't know the design of the internal circuitry. Although DP/DM can be used as GPIO if USB is not used, they are also routed to the USB transceiver block. I think the USB transceiver has circuitry that prevents the latch behavior when in USB mode. The errata does not mention any USB misbehavior in this regard and I have not heard of USB reporting that traces to GPIO#10.

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TM4C1233H6PGE: ESD Changing the State of GPIOs