MSPM0G3507: For I2C DMA repeated block transfer mode how to set the RXFIFO count bit in the MFIFOSR register?

Currently in the process of I2C data read via DMA in single transfer mode I'm able to read up to 8bytes.

But if I need to read more than 8bytes I've tried to enable the repeated single transfer mode, but what I see is even though the data is being transmitted to the TI launchpad the RXFIFO can only receive a single byte and RXFIFOCNT is remaining as 0x00.

What should be done to make the receive fifo count as 8?

Hi Lavina,

Lavina Vijay said:

But if I need to read more than 8bytes I've tried to enable the repeated single transfer mode

Single transfer mode is also OK in this scenario. Set a correct size of DMA is okay, for exmaple, 16/32/...

Lavina Vijay said:

What should be done to make the receive fifo count as 8?

If you enable DMA, then the receive fifo count will not reach 8, due to DMA will firstly transfer the data, and the count is less than you setting. If you set RX trigger level is 1, then it always be 0 due to DMA tranfer the data in RXFIFO.

I think below thread has give you a example project for further test.

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1352528/mspm0g3507-could-you-please-suggest-the-steps-to-read-approx-100bytes-of-data-via-i2c-dma

B.R.

Sal