Other Parts Discussed in Thread: HALCOGEN
Hello,
we use the method descriped in the following document the generate a system tick for our OS: https://www.ti.com/lit/fs/spna123/spna123.pdf
In this example (and also in our implementation) we reset the interrupt pending bit INT3 (because we use the compare 3 for this) in the RTI Interrupt Flag Register (RTIINTFLAG) by software.
I want to change it in that way, that this interrupt pending bit will be reset automatically. For this I
- defined the counter-value CMP3CLR in the RTI Compare 3 Clear Register (RTICOMP3CLR) and
- activated the auto-reset by writing 0xA in the INTCLRENABLE3-bits of the the RTI Compare Interrupt Clear Enable Register (RTIINTCLRENABLE),
but it's not working.
On the other hand we also use conversion with the internal ADC, triggered cyclic by the compare 0 of the RTI by using the auto-reset feature. There it works.
Is there a limitation with the RTI auto-reset feature? Or do I something wrong?
I'm asking my, why the example in spna123.pdf will not use the auto-reset feature?
Thanks for help.