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MSP432E401Y: EPI Host bus mode with 3 Chip selects polling initialization bit

Part Number: MSP432E401Y

Hello,

I'm using Host bus 16 mux mode with ALE and connected 3 devices with Chipselect including FPGA,SRAM and a parallel flash. I have configured the EPI peripheral as below snippet. But to send and receive from each Chip select

I'm currently using epi_sdram_basic_MSP_EXP432E401Y_nortos_ccs as reference.

In the below snippet, the SDRAM initialization sequence bit is polled for wakeup. But when we have 3 devices, how to poll initialization sequence bit for all the devices?

  /* Wait for the SDRAM wake-up to complete by polling the SDRAM
     * initialization sequence bit.  This bit is true when the SDRAM interface
     * is going through the initialization and false when the SDRAM interface
     * it is not in a wake-up period. */
    while(EPI0->STAT & EPI_STAT_INITSEQ)
    {
    }

Also,Can you please share any example VHDL code that's available for EPI ?

  • Hi,

      Unlike SDRAM where there is a wakeup period (e.g. greater than 100us), there is no such timing requirement for FPGA and SDRAM. Your FPGA is especially a custom IC and you should know if there is any wakeup sequence before you can access it. By the time you the SDRAM is ready for access, your other devices (SRAM and FPGA) should be available as well. 

    Also,Can you please share any example VHDL code that's available for EPI ?

    Not sure why are you asking for this. VHDL is a hardware description language that describes the construction of the design. This is a intellectual property of any form (VHDL, Verilog, netlist or etc) that we will not share externally. If you just want to learn VHDL, you can do some Google searches.