Other Parts Discussed in Thread: SYSCONFIG,
Tool/software:
Hi Experts,
I am posting this on behalf of the customer.
I have been working through the OpAmp Introduction lab from the MSPM0 Academy. I completed step 2a. of the first project about configuring the OpAmp in Buffer mode. I checked my solution with the OPA Sysconfig solution provided but when I went to part b "Go to SYSCTL and enable the MFCLK (Middle Frequency Clock)" my MFCLK enable box is greyed out and it wont let me enable it. I am using CCS Theia 1.3.1 and imported the dac12_fifo_timer_event under the TI Clang Compiler folder in the CCS Theia Resource Explorer.
I am using the MSPM0G3507 launchpad. I just found that if i uncheck the clock tree it will let me adjust the MFCLK. I am not sure what the next step after that or if this is what im supposed to do as the lab instructions just say "–> 3. Program the LaunchPad. 4. Connect your oscilloscope to OpAmp0 output(PA22) on the Launchpad." I went to Project --> build all in the top of the screen but not file was generated
In the notes here: Let’s take a look at the configuration code, this can be found in Project → Generated Source → SysConfig → ti_msp_dl_config.c. Sysconfig will generate the proper configuration code, but if you want to write your code your own independently the Sysconfig generated code is a great reference. The first step in the configuration is setting the reference voltage. The reference voltage will determine the range of output voltages the DAC can generate. The DAC12 is a 12-bit DAC which means that the maximum value is 4096. With a reference voltage of 2.5V, a digital value of 4096 will result in an output voltage of 2.5V. For a reference voltage of 1.4V, the same 4096 value will result in an output voltage of 1.4V.
Thank you in advance.
Best regards,
Jonathan
