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TMS570LC4357: Test for corruption of flash bank 7

Part Number: TMS570LC4357

Tool/software:

Hello, I want to intentionally corrupt a few sectors in flash bank 7 for testing purposes. Therefore, I performed a write operation that fills a sector continuously for about 5 days. After each write operation, I move to a new sector, allowing me to continuously fill and erase the sectors. Despite the long duration, no corruption occurred in flash bank 7. Approximately 300,000 write/erase cycles have been completed. The only issue I can currently observe is that the write/erase operations take much longer than usual after 100,000 cycles. What method can I use to corrupt the bits, pages, or sectors in this area?

  • Hi Zonguldak's Rose,

    What method can I use to corrupt the bits, pages, or sectors in this area?

    There is no method to corrupt the flash deliberately.

    The flash maybe corrupted during the following conditions:

    1. The datasheet lists the recommended operation condition and the absolute maximum rating for VCC/VCCIO/VCCP and temperature. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

    2. Using for more than the recommended Write/erase cycles. But the specified write/erase cycles in the datasheet are minimum cycles, that means flash will definitely work without any issues till this number of times however sometimes the flash can work for more than these cycles. We cannot predict exact number of cycles.

    So, it is not possible to corrupt the flash deliberately.

    You can do one thing, you can use diagnostic mode.

    For this purpose, first you just need to write the data and corresponding ECC to the flash. And after that you can corrupt either ECC or data to create single bit errors or multiple bit errors. The SECDED module in the controller will correct the single bit errors and can detect the double bit errors and also you will get the corresponding ESM flag bits to be set.

    You can find code for this in the SafeTI Diagnostic Library:

    SAFETI_DIAG_LIB Driver or library | TI.com

    --
    Thanks & Regards,
    Jagadish.

  • Actually I want to control eeprom bits using my own test which is write some data and after that read that data and comparing with written data. As my understanding your answer, this test is not a proper method for this. Because if the flash bank 7 area is damaged, it will give an esm error and I don't need any test for control this area. Is my understanding right ?
    I want to control durability/lifetime of flash bank 7. Is there any method for this ? Is ECC only method for understand our eeprom is damaged?

  • Hi Zonguldak's Rose,

    Because if the flash bank 7 area is damaged, it will give an esm error and I don't need any test for control this area. Is my understanding right ?

    Your understanding was correct.

    I want to control durability/lifetime of flash bank 7. Is there any method for this ? Is ECC only method for understand our eeprom is damaged?

    ECC is one of the easiest ways because we no need to do any manual Comparisions of data to find out the damaged EEPROM.

    Instead of we can enable the ECC and ESM notifications for corresponding interrupts. So, whenever CPU reads a damages location, in the background ECC validation will be done for corresponding memory, if it is damages then you will immediately get the ESM notification, now you can take the required action.

    For more details refer chapter-7 in CRC "F021 Level 2 Flash Module Controller (L2FMC)"

    --
    Thanks & regards,
    Jagadish.