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TMS570LS3137: How to maintain MibSPI Slave Transmit 7 word transfer group data coherency?

Joe Barrus
Prodigy 80 points
Part Number: TMS570LS3137

Tool/software:

Hi, I'm using the TMS570LS3137 MIBSPI5 as a slave.  We are transferring 7 16-bit words in one transfer group (single Chip Select assertion) frame. 

Each SPI transfer the Slave is transmitting 7 16-bits of Slave status and receiving 7 16-bits of new commands from the Master.

The Master controls the SPI transactions timing and the transactions are asynchronous to the Slave regularly updating the TXRAM buffers using mibspiSetData().

We have a concern about what happens when the Master sends a SPI transaction in the middle of the the Slave updating the 7 data words in TXRAM buffers.

We are worried that the first 3 16-bit words could be sent from the Slave to the Master then the Slave status data is updated and the following 4 words of the frame might not be coherent with the first 3 words of the Slave status transmit data.

While it appears that each 16 bit word is moved into the TX shift register (per Section 25.2.2.1 of the TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual, see below) in a single operation, how can we ensure our 7 16-bit Slave transmit transfer group is transferred as one coherent block of data?

Thanks, 

-Joe

______________________

25.2.2.1 Data Sequencing when SPIDAT0 or SPIDAT1 is Written
• If both the TX shift register and TXBUF are empty, then the data is directly copied to the TX shift
register. For devices with DMA, if DMA is enabled, a transmit DMA request (TX_DMA_REQ) is
generated to cause the next word to be fetched. If transmit interrupts are enabled, a transmitter-empty
interrupt is generated.
• If the TX shift register is already full or is in the process of shifting and if TXBUF is expty then the data
written to SPIDAT0 / SPIDAT1 is copied to TXBUF and TXFULL flag is set to 1 at the same time.
• When a shift operation is complete, data from the TXBUF (if it is full) is copied into TX shift register
and the TXFULL flag is cleared to 0 to indicate that next data can be fetched. A transmit DMA request
(if enabled) or a transmitter-empty interrupt (if enabled) is generated at the same time.

  • +1
    TI__Guru 70681 points

    Hi Joe,

    Joe Barrus said:
    We are worried that the first 3 16-bit words could be sent from the Slave to the Master then the Slave status data is updated and the following 4 words of the frame might not be coherent with the first 3 words of the Slave status transmit data.

    I think this will not happen. According to my understanding of Mibspi, it depends on the TGENA bit in the TGxCTRL register.

    Actually, for data transmission in slave side first we will call the "mibspiSetData" function to initialize the data to the MibSPI RAM and then we will call the mibspiTransfer function, right?

    Here in this mibspiTransfer function we will enable the TGENA bit for corresponding transfer group.

    For example, if slave is updating the data in the mibspiSetData data function and TGENA bit was not set, if in this condition master sends the clock and trying to receive the data from the slave then the from slave the data in the MibSPI RAM will not get transfer, instead of all 0's or all 1's will get transfer depends on the pull state.

    If pullup set, then all 1's will get received to the master.

    Note:
    After reset initially this TGENA bit will be 0, but after we do first transfer by setting this bit then it will be in set state only and we should need to clear it manually before doing data initialization using mibspiSetData. If we didn't reset this bit (TGENA = 1), if master sends clock in this condition, then the data in the MibSPI RAM will get transfer directly, i mean if slave updates 3 bytes of 8 bytes, then master will receive updated data for first 3 bytes and old data in the next 5 bytes.

    So, you can control the data from slave using TGENA, i mean if you receive all 1's then you can consider slave not updated data in the master side. But this is also not a good method because what if slave trying to send all 1's only.

    So, the good method is that you need to add some checksum or CRC in the last bytes. If CRC matches then master can process the data, if CRC doesn't match then master can request the data again from slave.

    --
    Thanks & Regards,
    Jagadish.

  • +1 in reply to jagadish gundavarapu
    Prodigy 80 points

    Thanks Jagadish for the suggestions. 

    In section 25.9.34 TGx Control Registers (TGxCTRL) of the TMS570LS31x/21x Technical Reference Manual, it says regarding TGENA:

    "TGx enable.
    If the correct event (TRIGEVTx) occurs at the selected source (TRIGSRCx), a group transfer is
    initiated if no higher-priority TG is in active-transfer mode or if one or more higher-priority TGs are
    in transfer-suspend mode.
    Disabling a TG while a transfer is ongoing will finish the ongoing word transfer but not the whole
    group transfer."

    So it looks like if the Slave asynchronously clears TGENA, we could still interrupt a transfer group.in the middle of transmission.-- causing all 1's to be sent to the Master for the remainder of the transfer group.

    We already have a checksum in our transfer group defined so we'll plan on using that to discard any frames that aren't coherent/checksum doesn't match.

    Best regards!

    Joe