Part Number: MCU-PLUS-SDK-AM263X
Tool/software:
I am using AM263X-LP and wants to implement simultaneous sampling on 4 adc channel(all channel working at its maximum sampling rate), what is best example project to refer for?
Pls tell the difference in output obtained in two situations mentioned below
1. implementation of simultaneous sampling using 1 adc module and utilizing it's 4 channel.
2. implementation of simultaneous sampling using 4 adc module and utilizing single channel of each.
Hii Fleenor,
Thanks for your suggestions,
After going through multiple thread in ti E2E, I realised AM263x MCU+ SDK: ADC SOC Continuous DMA is better option for simultaneous sampling for higher frequency signal. it is working well when i am setting the sampling rate at 3.2 MSPS(or low) but when i set sampling rate to 4MSPS ( by changing the adc clk prescaler) there is phase difference for same signal(both signal with same properties) on both the channel. below i have attached the image for same.
how to resolve this issue??
sampling rate = 3.2msps(approx) , frequency of sine wave= 400KHz(on both channel)
sampling rate = 4msps , frequency of sine wave= 400KHz(on both channel)
Hii Fleenor,
This is additional details for sampling 4 adc channel (1 channel of 4 different adc instance)
The sequence in which i am calling App_dmaConfigure function is given below -
App_dmaConfigure(gAdc1DataBuffer, RESULTS_BUFFER_SIZE, gEdmaHandle[0],
ADC1_EDMA_CHANNEL, CONFIG_ADC1_RESULT_BASE_ADDR, &tccAlloc0, EDMA_TEST_EVT_QUEUE_NO_0);
App_dmaConfigure(gAdc2DataBuffer, RESULTS_BUFFER_SIZE, gEdmaHandle[0],
ADC2_EDMA_CHANNEL, CONFIG_ADC2_RESULT_BASE_ADDR, &tccAlloc1, EDMA_TEST_EVT_QUEUE_NO_1);
App_dmaConfigure(gAdc3DataBuffer, RESULTS_BUFFER_SIZE, gEdmaHandle[0],
ADC3_EDMA_CHANNEL, CONFIG_ADC3_RESULT_BASE_ADDR, &tccAlloc2, EDMA_TEST_EVT_QUEUE_NO_0);
App_dmaConfigure(gAdc4DataBuffer, RESULTS_BUFFER_SIZE, gEdmaHandle[0],
ADC4_EDMA_CHANNEL, CONFIG_ADC4_RESULT_BASE_ADDR, &tccAlloc3, EDMA_TEST_EVT_QUEUE_NO_1);
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#include <stdio.h>
#include <kernel/dpl/DebugP.h>
#include <kernel/dpl/ClockP.h>
#include <kernel/dpl/SemaphoreP.h>
#include <kernel/dpl/HwiP.h>
#include <drivers/epwm.h>
#include <drivers/adc.h>
#include "ti_drivers_config.h"
#include "ti_drivers_open_close.h"
#include "ti_board_open_close.h"
/*
* This example sets up two ADC channels to convert simultaneously. The
* results will be transferred by DMA into a buffer in RAM.
*
* errata i2355 for AM263x:
* DMA trigger from the ADC INT (Late) occurs just before the Result space updation,
* as a result of which the stale data from the result space will be transferred by
* DMA.
* Workaround:
* use an empty channel transfer before the Actual transfer.
*
* It configures ePWM0 to trigger SOC0 on ADC1 and ADC2. EPWM is only used to
* trigger the first ADC conversion. INT0 of ADC1 is configured to generate
* interrupt after first conversion and will then disable EPWM SOC generation.
* INT1 of both ADC's is configured to enable continuous conversion.
*
* DMA channel 0 is triggered at EOC0 of ADC1 and will copy conversion result
* to a empty buffer in RAM, and triggers DMA Channel 1 to copy actual conversion
* result to result buffer in RAM. Similarly, DMA Channel 2 is triggered at ADC 2 EOC0
* and transfers ADC 2 result space an empty buffer in RAM and .
* DMA will generate interrupt after the buffer is filled and will stop conversion on both ADCs.
*
* The below watch variables can be used to view ADC conversion results.
*
* External Connections
* ADC1_AIN0 and ADC2_AIN0 pins should be connected to signals to be converted.
* AM263pX-CC E2 or AM263X-CC E2 :
* - Feed the External Volatage to the following
* - ADC1_AIN0 : HSEC-PIN 12
* - ADC2_AIN0 : HSEC-PIN 31
* AM263PX-LP or AM263X-LP :
* - Feed the External Volatage to the following
* - ADC1_AIN0 : J1/3 24
* - ADC2_AIN0 : J1/3 25
*
* Watch Variables
* gAdc1DataBuffer - Buffers which stores conversion results from ADC1
* gADC2DataBuffer - Buffers which stores conversion results from ADC2
*/
/* Size of buffer for storing conversion results */
#define RESULTS_BUFFER_SIZE 1024*16
/* Event queue to be used for EDMA transfer */
#define EDMA_TEST_EVT_QUEUE_NO_0 0U
#define EDMA_TEST_EVT_QUEUE_NO_1 1U
#define EDMA_TEST_EVT_QUEUE_NO_2 2U
#define EDMA_TEST_EVT_QUEUE_NO_3 3U
/* DMA channel number to transfer ADC1 and ADC2 conversion results*/
/* the following channels will be used for empty transaction to comply to errata i2355
these chain the ADC result data transfer */
#define ADC1_EDMA_CHANNEL (DMA_TRIG_XBAR_EDMA_MODULE_0)
#define ADC2_EDMA_CHANNEL (DMA_TRIG_XBAR_EDMA_MODULE_2)
#define ADC3_EDMA_CHANNEL (DMA_TRIG_XBAR_EDMA_MODULE_4)
#define ADC4_EDMA_CHANNEL (DMA_TRIG_XBAR_EDMA_MODULE_6)
/* Note: the actual transfer channels are configured for EDMA_RESOURCE_ALLOC_ANY,
typically selecting the next available channels
in this case, DMA_TRIG_XBAR_EDMA_MODULE_1 and DMA_TRIG_XBAR_EDMA_MODULE_3 hold the actual transfer.*/
/* Global variables and objects */
/* Buffers to store conversion results from ADC1 and ADC2 */
uint16_t gAdc1DataBuffer[RESULTS_BUFFER_SIZE];
uint16_t gAdc2DataBuffer[RESULTS_BUFFER_SIZE];
uint16_t gAdc3DataBuffer[RESULTS_BUFFER_SIZE];
uint16_t gAdc4DataBuffer[RESULTS_BUFFER_SIZE];
uint16_t gUnusedBuffer[RESULTS_BUFFER_SIZE];
static HwiP_Object gAdcHwiObject;
/* Semaphore to indicate transfer completion */
static SemaphoreP_Object gEdmaTransferDoneSem;
/* ADC instance base addresses */
uint32_t gAdc1baseAddr = CONFIG_ADC1_BASE_ADDR;
uint32_t gAdc2baseAddr = CONFIG_ADC2_BASE_ADDR;
uint32_t gAdc3baseAddr = CONFIG_ADC3_BASE_ADDR;
uint32_t gAdc4baseAddr = CONFIG_ADC4_BASE_ADDR;
int region=0,counter=0;
/* Function Prototypes */
uint16_t App_dmaConfigure(const uint16_t *table, uint16_t table_size,
EDMA_Handle dma_handle, uint32_t dma_ch,
uint32_t adc_base, uint32_t *tccAlloc, uint32_t event_queue_number);
static void App_adcISR(void *args);
static void App_dmach0ISR(Edma_IntrHandle intrHandle, void *args);
void adc_soc_continuous_dma_main(void *args)
{
int32_t status;
Edma_IntrObject intrObj;
HwiP_Params hwiPrms;
uint32_t loopCnt = 0;
uint32_t tccAlloc0, tccAlloc1,tccAlloc2,tccAlloc3;
/* Open drivers to open the UART driver for console */
Drivers_open();
Board_driversOpen();
DebugP_log("ADC Continuous DMA transfer Test Started ...\r\n");
/* Initialize both the result buffers with zeroes */
for(loopCnt = 0U; loopCnt < RESULTS_BUFFER_SIZE; loopCnt++)
{
gUnusedBuffer[loopCnt] = 0U;
gAdc1DataBuffer[loopCnt] = 0U;
gAdc2DataBuffer[loopCnt] = 0U;
gAdc3DataBuffer[loopCnt] = 0U;
gAdc4DataBuffer[loopCnt] = 0U;
}
// /* Perform a cache write back to the result buffers */
// CacheP_wb((void *)gAdc1DataBuffer, RESULTS_BUFFER_SIZE*2, CacheP_TYPE_ALL);
// CacheP_wb((void *)gAdc2DataBuffer, RESULTS_BUFFER_SIZE*2, CacheP_TYPE_ALL);
/* Register & enable interrupt */
HwiP_Params_init(&hwiPrms);
hwiPrms.intNum = CSLR_R5FSS0_CORE0_CONTROLSS_INTRXBAR0_OUT_0;
hwiPrms.callback = &App_adcISR;
status = HwiP_construct(&gAdcHwiObject, &hwiPrms);
DebugP_assert(status == SystemP_SUCCESS);
/* Create a semaphore to signal EDMA transfer completion */
status = SemaphoreP_constructBinary(&gEdmaTransferDoneSem, 0);
DebugP_assert(SystemP_SUCCESS == status);
/* Configure DMA channels to transfer both ADC results */
App_dmaConfigure(gAdc1DataBuffer, RESULTS_BUFFER_SIZE, gEdmaHandle[0],
ADC1_EDMA_CHANNEL, CONFIG_ADC1_RESULT_BASE_ADDR, &tccAlloc0, EDMA_TEST_EVT_QUEUE_NO_0);
App_dmaConfigure(gAdc2DataBuffer, RESULTS_BUFFER_SIZE, gEdmaHandle[0],
ADC2_EDMA_CHANNEL, CONFIG_ADC2_RESULT_BASE_ADDR, &tccAlloc1, EDMA_TEST_EVT_QUEUE_NO_1);
App_dmaConfigure(gAdc3DataBuffer, RESULTS_BUFFER_SIZE, gEdmaHandle[0],
ADC3_EDMA_CHANNEL, CONFIG_ADC3_RESULT_BASE_ADDR, &tccAlloc2, EDMA_TEST_EVT_QUEUE_NO_0);
App_dmaConfigure(gAdc4DataBuffer, RESULTS_BUFFER_SIZE, gEdmaHandle[0],
ADC4_EDMA_CHANNEL, CONFIG_ADC4_RESULT_BASE_ADDR, &tccAlloc3, EDMA_TEST_EVT_QUEUE_NO_1);
/* Register interrupt */
intrObj.tccNum = tccAlloc3;
intrObj.cbFxn = &App_dmach0ISR;
intrObj.appData = (void *) &gEdmaTransferDoneSem;
status = EDMA_registerIntr(gEdmaHandle[0], &intrObj);
DebugP_assert(status == SystemP_SUCCESS);
/* Clear ADC Interrupt status */
ADC_clearInterruptStatus(gAdc1baseAddr,ADC_INT_NUMBER1);
ADC_clearInterruptStatus(gAdc1baseAddr,ADC_INT_NUMBER2);
ADC_clearInterruptStatus(gAdc2baseAddr,ADC_INT_NUMBER1);
ADC_clearInterruptStatus(gAdc2baseAddr,ADC_INT_NUMBER2);
ADC_clearInterruptStatus(gAdc3baseAddr,ADC_INT_NUMBER1);
ADC_clearInterruptStatus(gAdc3baseAddr,ADC_INT_NUMBER2);
ADC_clearInterruptStatus(gAdc4baseAddr,ADC_INT_NUMBER1);
ADC_clearInterruptStatus(gAdc4baseAddr,ADC_INT_NUMBER2);
/* Enable event counter init for SOCA */
EPWM_enableADCTriggerEventCountInit(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_A);
/* Set the event counter init value to 0 */
EPWM_setADCTriggerEventCountInitValue(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_A, 0);
/* Force the event counter init value to event counter */
EPWM_forceADCTriggerEventCountInit(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_A);
EPWM_clearADCTriggerFlag(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_A);
/* Enable ADC Trigger from EPWM to start ADC conversion */
EPWM_enableADCTrigger(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_A);
EPWM_setADCTriggerSource(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_A, EPWM_SOC_TBCTR_ZERO, EPWM_SOC_TBCTR_ZERO);
EPWM_setADCTriggerEventPrescale(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_A, 1);
EPWM_setTimeBaseCounterMode(CONFIG_EPWM0_BASE_ADDR, EPWM_COUNTER_MODE_UP);
/*
* Wait while DMA transfers ADC conversion results to buffer.
*/
SemaphoreP_pend(&gEdmaTransferDoneSem, SystemP_WAIT_FOREVER);
/* Invalidate destination buffer */
CacheP_inv((void *)gUnusedBuffer, RESULTS_BUFFER_SIZE*2, CacheP_TYPE_ALL);
CacheP_inv((void *)gAdc1DataBuffer, RESULTS_BUFFER_SIZE*2, CacheP_TYPE_ALL);
CacheP_inv((void *)gAdc2DataBuffer, RESULTS_BUFFER_SIZE*2, CacheP_TYPE_ALL);
CacheP_inv((void *)gAdc3DataBuffer, RESULTS_BUFFER_SIZE*2, CacheP_TYPE_ALL);
CacheP_inv((void *)gAdc4DataBuffer, RESULTS_BUFFER_SIZE*2, CacheP_TYPE_ALL);
DebugP_log("Result register value -\r\n");
loopCnt = 0;
/* Print few elements from the result buffer */
while(loopCnt < RESULTS_BUFFER_SIZE)
{
DebugP_log("%d \t %d \t %d \t %d \r\n", gAdc1DataBuffer[loopCnt], gAdc2DataBuffer[loopCnt],gAdc3DataBuffer[loopCnt],gAdc4DataBuffer[loopCnt]);
loopCnt += 1;
}
DebugP_log("ADC Continuous DMA transfer Test Passed\r\n");
DebugP_log("All tests have passed!!\r\n");
Board_driversClose();
Drivers_close();
}
uint16_t App_dmaConfigure(
const uint16_t *table, uint16_t table_size,
EDMA_Handle dma_handle, uint32_t dma_ch,
uint32_t adc_base, uint32_t *tccAlloc, uint32_t event_queue_number)
{
uint32_t baseAddr, regionId;
EDMACCPaRAMEntry empty_edmaParam, edmaParam;
uint32_t empty_dmaCh, dmaCh, empty_tcc, tcc, empty_param, param;
// EDMACCPaRAMEntry empty_edmaParam;
// uint32_t empty_dmaCh, empty_tcc, empty_param;
int32_t testStatus = SystemP_SUCCESS;
/* Enable only TC and ITC chaining on dmaCh0.
TC and ITC interrupt enable not required. */
uint32_t chainOptions = (EDMA_OPT_TCCHEN_MASK |
EDMA_OPT_ITCCHEN_MASK);
baseAddr = EDMA_getBaseAddr(gEdmaHandle[0]);
DebugP_assert(baseAddr != 0);
regionId = EDMA_getRegionId(gEdmaHandle[0]);
DebugP_assert(regionId < SOC_EDMA_NUM_REGIONS);
// printf("region: %d \t \n",region++);
empty_dmaCh = dma_ch;
testStatus = EDMA_allocDmaChannel(gEdmaHandle[0], &empty_dmaCh);
DebugP_assert(testStatus == SystemP_SUCCESS);
// printf("allocated dma channel %d \n",empty_dmaCh);
/* typically allocates the next available channel */
empty_tcc = EDMA_RESOURCE_ALLOC_ANY;
testStatus = EDMA_allocTcc(gEdmaHandle[0], &empty_tcc);
DebugP_assert(testStatus == SystemP_SUCCESS);
empty_param = EDMA_RESOURCE_ALLOC_ANY;
testStatus = EDMA_allocParam(gEdmaHandle[0], &empty_param);
DebugP_assert(testStatus == SystemP_SUCCESS);
dmaCh = EDMA_RESOURCE_ALLOC_ANY;
testStatus = EDMA_allocDmaChannel(gEdmaHandle[0], &dmaCh);
DebugP_assert(testStatus == SystemP_SUCCESS);
printf("allocated dma channel %d \n",dmaCh);
tcc = EDMA_RESOURCE_ALLOC_ANY;
testStatus = EDMA_allocTcc(gEdmaHandle[0], &tcc);
DebugP_assert(testStatus == SystemP_SUCCESS);
/* Passing back the Channel parameter to register the interrupt ISR*/
*tccAlloc = tcc;
printf("counter assigned %d \n",counter++);
param = EDMA_RESOURCE_ALLOC_ANY;
testStatus = EDMA_allocParam(gEdmaHandle[0], ¶m);
DebugP_assert(testStatus == SystemP_SUCCESS);
/* Request channel */
EDMA_configureChannelRegion(baseAddr, regionId, EDMA_CHANNEL_TYPE_DMA,
empty_dmaCh, empty_tcc, empty_param, event_queue_number);
/* Program Param Set */
EDMA_ccPaRAMEntry_init(&empty_edmaParam);
empty_edmaParam.srcAddr = (uint32_t) SOC_virtToPhy((void *)(adc_base+CSL_ADC_RESULT_ADCRESULT0));
empty_edmaParam.destAddr = (uint32_t) SOC_virtToPhy((void *)gUnusedBuffer);
empty_edmaParam.aCnt = (uint16_t) 2;
empty_edmaParam.bCnt = (uint16_t) table_size;
empty_edmaParam.cCnt = (uint16_t) 1;
empty_edmaParam.bCntReload = 0;
empty_edmaParam.srcBIdx = (int16_t) EDMA_PARAM_BIDX(0);
empty_edmaParam.destBIdx = (int16_t) EDMA_PARAM_BIDX(2);
empty_edmaParam.srcCIdx = (int16_t) 0;
empty_edmaParam.destCIdx = (int16_t) 0;
empty_edmaParam.linkAddr = 0xFFFFU;
empty_edmaParam.srcBIdxExt = (int8_t) EDMA_PARAM_BIDX_EXT(0);
empty_edmaParam.destBIdxExt = (int8_t) EDMA_PARAM_BIDX_EXT(2);
empty_edmaParam.opt = (EDMA_OPT_TCINTEN_MASK | EDMA_OPT_ITCINTEN_MASK |
((((uint32_t)empty_tcc) << EDMA_OPT_TCC_SHIFT) & EDMA_OPT_TCC_MASK));
/* Enabling in options for the,
the Transfer-complete Interrupt --> After total data is transferred
, Intermediate transfer complete interrupt --> After each A data chunk transfer is comeplete
this will be used for the chaining of the actual transfer.
*/
EDMA_setPaRAM(baseAddr, empty_param, &empty_edmaParam);
EDMA_configureChannelRegion(baseAddr, regionId, EDMA_CHANNEL_TYPE_DMA, dmaCh, tcc, param, event_queue_number);
/* Program Param Set */
EDMA_ccPaRAMEntry_init(&edmaParam);
edmaParam.srcAddr = (uint32_t) SOC_virtToPhy((void *)(adc_base+CSL_ADC_RESULT_ADCRESULT0));
edmaParam.destAddr = (uint32_t) SOC_virtToPhy((void *)table);
edmaParam.aCnt = (uint16_t) 2;
edmaParam.bCnt = (uint16_t) table_size;
edmaParam.cCnt = (uint16_t) 1;
edmaParam.bCntReload = 0;
edmaParam.srcBIdx = (int16_t) EDMA_PARAM_BIDX(0);
edmaParam.destBIdx = (int16_t) EDMA_PARAM_BIDX(2);
edmaParam.srcCIdx = (int16_t) 0;
edmaParam.destCIdx = (int16_t) 0;
edmaParam.linkAddr = 0xFFFFU;
edmaParam.srcBIdxExt = (int8_t) EDMA_PARAM_BIDX_EXT(0);
edmaParam.destBIdxExt = (int8_t) EDMA_PARAM_BIDX_EXT(2);
edmaParam.opt = (EDMA_OPT_TCINTEN_MASK |
((((uint32_t)tcc) << EDMA_OPT_TCC_SHIFT) & EDMA_OPT_TCC_MASK));
/* Enabling the Interrupt for Transfer complete of all the data */
EDMA_setPaRAM(baseAddr, param, &edmaParam);
/* Chain the empty transfer to the actual transfer.
Chain options include Total transfer completion and intermediate channel completion flags
from empty channel*/
EDMA_chainChannel(baseAddr, empty_param, dmaCh, chainOptions);
/* Enabling the transfer region for empty channel for the trigger mode set in the Syscfg through
the DMA Xbars adn DMA TRIG Xbars.*/
EDMA_enableTransferRegion(baseAddr, regionId, empty_dmaCh,
EDMA_TRIG_MODE_EVENT);
return testStatus;
}
void App_adcISR(void *args)
{
/* Remove ePWM trigger */
printf("inside the adc interrupt \n");
EPWM_disableADCTrigger(CONFIG_EPWM0_BASE_ADDR, EPWM_SOC_A);
/* Disable this interrupt from happening again */
ADC_disableInterrupt(gAdc1baseAddr, ADC_INT_NUMBER1);
}
void App_dmach0ISR(Edma_IntrHandle intrHandle, void *args)
{
SemaphoreP_Object *semObjPtr = (SemaphoreP_Object *)args;
DebugP_assert(semObjPtr != NULL);
printf("inside the interrupt \n");
/* Stop the ADCs by removing the trigger for SOC0 */
ADC_setInterruptSOCTrigger(gAdc1baseAddr, ADC_SOC_NUMBER0,
ADC_INT_SOC_TRIGGER_NONE);
ADC_setInterruptSOCTrigger(gAdc2baseAddr, ADC_SOC_NUMBER0,
ADC_INT_SOC_TRIGGER_NONE);
ADC_setInterruptSOCTrigger(gAdc3baseAddr, ADC_SOC_NUMBER0,
ADC_INT_SOC_TRIGGER_NONE);
/* Post the semaphore to signal end of DMA transfer */
SemaphoreP_post(semObjPtr);
}
Hi Madhava,
1. Yes ADCs are triggered by their own INT.
Approch is mentioned below-
a) First ADC conversion is done using ePWM0, ADCSOCA. INT1, INT2 is generated at the end of conversion.
b) ADC0_INT1 is linked to INT_XBAR_0 for generating interrupt.
c) When interrupt is received after first converion, I am disabling the ePWM trigger and ADC0_INT1.
d) From this point onwards INT2 is used to start the interrupt for conversion.
2. I have assigned S/H window to 16 (sysclk cycle) which is 80ns for all cases.
When i am doing ADCCLK = (input clock) / 4.5 ( sampling rate = 3.2 MSPS approx) it works fine for 2 ADC channel.
When i make Adc Prescaler 3 or below ( sampling rate >= 4MSPS approx) then there is some phase difference while sampling 2 signal
of higher frequency.
Below is formula from which i am calculating sampling rate.
The main problem comes when i am sampling 4 ADCs simultaneously, Then there is phase difference even for sampling rate of 3.2MSPS.
I have already shared the details of DMA PaRAM configuration in previous response.
Thanks.
Hi Madhava,
Yes even at sampling rate of 3.2 MSPS i am facing the phase difference issue.
This is the observation i am getting for 4 ADC simultaneous sampling.
The sequence in which i am calling App_dmaConfigure function is given below -
App_dmaConfigure(gAdc1DataBuffer, RESULTS_BUFFER_SIZE, gEdmaHandle[0],
ADC1_EDMA_CHANNEL, CONFIG_ADC1_RESULT_BASE_ADDR, &tccAlloc0, EDMA_TEST_EVT_QUEUE_NO_0);
App_dmaConfigure(gAdc2DataBuffer, RESULTS_BUFFER_SIZE, gEdmaHandle[0],
ADC2_EDMA_CHANNEL, CONFIG_ADC2_RESULT_BASE_ADDR, &tccAlloc1, EDMA_TEST_EVT_QUEUE_NO_1);
App_dmaConfigure(gAdc3DataBuffer, RESULTS_BUFFER_SIZE, gEdmaHandle[0],
ADC3_EDMA_CHANNEL, CONFIG_ADC3_RESULT_BASE_ADDR, &tccAlloc2, EDMA_TEST_EVT_QUEUE_NO_0);
App_dmaConfigure(gAdc4DataBuffer, RESULTS_BUFFER_SIZE, gEdmaHandle[0],
ADC4_EDMA_CHANNEL, CONFIG_ADC4_RESULT_BASE_ADDR, &tccAlloc3, EDMA_TEST_EVT_QUEUE_NO_1);
uint16_t App_dmaConfigure(
const uint16_t *table, uint16_t table_size,
EDMA_Handle dma_handle, uint32_t dma_ch,
uint32_t adc_base, uint32_t *tccAlloc, uint32_t event_queue_number)
{
uint32_t baseAddr, regionId;
EDMACCPaRAMEntry empty_edmaParam, edmaParam;
uint32_t empty_dmaCh, dmaCh, empty_tcc, tcc, empty_param, param;
// EDMACCPaRAMEntry empty_edmaParam;
// uint32_t empty_dmaCh, empty_tcc, empty_param;
int32_t testStatus = SystemP_SUCCESS;
uint32_t chainOptions = (EDMA_OPT_TCCHEN_MASK |
EDMA_OPT_ITCCHEN_MASK);
baseAddr = EDMA_getBaseAddr(gEdmaHandle[0]);
DebugP_assert(baseAddr != 0);
regionId = EDMA_getRegionId(gEdmaHandle[0]);
DebugP_assert(regionId < SOC_EDMA_NUM_REGIONS);
empty_dmaCh = dma_ch;
testStatus = EDMA_allocDmaChannel(gEdmaHandle[0], &empty_dmaCh);
DebugP_assert(testStatus == SystemP_SUCCESS);
empty_tcc = EDMA_RESOURCE_ALLOC_ANY;
testStatus = EDMA_allocTcc(gEdmaHandle[0], &empty_tcc);
DebugP_assert(testStatus == SystemP_SUCCESS);
empty_param = EDMA_RESOURCE_ALLOC_ANY;
testStatus = EDMA_allocParam(gEdmaHandle[0], &empty_param);
DebugP_assert(testStatus == SystemP_SUCCESS);
dmaCh = EDMA_RESOURCE_ALLOC_ANY;
testStatus = EDMA_allocDmaChannel(gEdmaHandle[0], &dmaCh);
DebugP_assert(testStatus == SystemP_SUCCESS);
printf("allocated dma channel %d \n",dmaCh);
tcc = EDMA_RESOURCE_ALLOC_ANY;
testStatus = EDMA_allocTcc(gEdmaHandle[0], &tcc);
DebugP_assert(testStatus == SystemP_SUCCESS);
/* Passing back the Channel parameter to register the interrupt ISR*/
*tccAlloc = tcc;
printf("counter assigned %d \n",counter++);
param = EDMA_RESOURCE_ALLOC_ANY;
testStatus = EDMA_allocParam(gEdmaHandle[0], ¶m);
DebugP_assert(testStatus == SystemP_SUCCESS);
/* Request channel */
EDMA_configureChannelRegion(baseAddr, regionId, EDMA_CHANNEL_TYPE_DMA,
empty_dmaCh, empty_tcc, empty_param, event_queue_number);
/* Program Param Set */
EDMA_ccPaRAMEntry_init(&empty_edmaParam);
empty_edmaParam.srcAddr = (uint32_t) SOC_virtToPhy((void *)(adc_base+CSL_ADC_RESULT_ADCRESULT0));
empty_edmaParam.destAddr = (uint32_t) SOC_virtToPhy((void *)gUnusedBuffer);
empty_edmaParam.aCnt = (uint16_t) 2;
empty_edmaParam.bCnt = (uint16_t) table_size;
empty_edmaParam.cCnt = (uint16_t) 1;
empty_edmaParam.bCntReload = 0;
empty_edmaParam.srcBIdx = (int16_t) EDMA_PARAM_BIDX(0);
empty_edmaParam.destBIdx = (int16_t) EDMA_PARAM_BIDX(2);
empty_edmaParam.srcCIdx = (int16_t) 0;
empty_edmaParam.destCIdx = (int16_t) 0;
empty_edmaParam.linkAddr = 0xFFFFU;
empty_edmaParam.srcBIdxExt = (int8_t) EDMA_PARAM_BIDX_EXT(0);
empty_edmaParam.destBIdxExt = (int8_t) EDMA_PARAM_BIDX_EXT(2);
empty_edmaParam.opt = (EDMA_OPT_TCINTEN_MASK | EDMA_OPT_ITCINTEN_MASK |
((((uint32_t)empty_tcc) << EDMA_OPT_TCC_SHIFT) & EDMA_OPT_TCC_MASK));
EDMA_setPaRAM(baseAddr, empty_param, &empty_edmaParam);
EDMA_configureChannelRegion(baseAddr, regionId, EDMA_CHANNEL_TYPE_DMA, dmaCh, tcc, param, event_queue_number);
/* Program Param Set */
EDMA_ccPaRAMEntry_init(&edmaParam);
edmaParam.srcAddr = (uint32_t) SOC_virtToPhy((void *)(adc_base+CSL_ADC_RESULT_ADCRESULT0));
edmaParam.destAddr = (uint32_t) SOC_virtToPhy((void *)table);
edmaParam.aCnt = (uint16_t) 2;
edmaParam.bCnt = (uint16_t) table_size;
edmaParam.cCnt = (uint16_t) 1;
edmaParam.bCntReload = 0;
edmaParam.srcBIdx = (int16_t) EDMA_PARAM_BIDX(0);
edmaParam.destBIdx = (int16_t) EDMA_PARAM_BIDX(2);
edmaParam.srcCIdx = (int16_t) 0;
edmaParam.destCIdx = (int16_t) 0;
edmaParam.linkAddr = 0xFFFFU;
edmaParam.srcBIdxExt = (int8_t) EDMA_PARAM_BIDX_EXT(0);
edmaParam.destBIdxExt = (int8_t) EDMA_PARAM_BIDX_EXT(2);
edmaParam.opt = (EDMA_OPT_TCINTEN_MASK |
((((uint32_t)tcc) << EDMA_OPT_TCC_SHIFT) & EDMA_OPT_TCC_MASK));
/* Enabling the Interrupt for Transfer complete of all the data */
EDMA_setPaRAM(baseAddr, param, &edmaParam);
EDMA_chainChannel(baseAddr, empty_param, dmaCh, chainOptions);
EDMA_enableTransferRegion(baseAddr, regionId, empty_dmaCh,
EDMA_TRIG_MODE_EVENT);
return testStatus;
}
void App_dmach0ISR(Edma_IntrHandle intrHandle, void *args)
{
SemaphoreP_Object *semObjPtr = (SemaphoreP_Object *)args;
DebugP_assert(semObjPtr != NULL);
printf("inside the interrupt \n");
ADC_setInterruptSOCTrigger(gAdc1baseAddr, ADC_SOC_NUMBER0,
ADC_INT_SOC_TRIGGER_NONE);
ADC_setInterruptSOCTrigger(gAdc2baseAddr, ADC_SOC_NUMBER0,
ADC_INT_SOC_TRIGGER_NONE);
ADC_setInterruptSOCTrigger(gAdc3baseAddr, ADC_SOC_NUMBER0,
ADC_INT_SOC_TRIGGER_NONE);
/* Post the semaphore to signal end of DMA transfer */
SemaphoreP_post(semObjPtr);
}Hii Madhava,
When i am sampling ADCs from the reset this is the graph i am getting ( Graph is for the 100KHz signal getting sampled at 4MSPS).
problem which i am facing is-
1) For 100KHz signal sampling at 4MSPS we should get 40 samples per cycle but i am getting only 20 samples.
There is one doubt from my side-
We will receive the interrupt for end of conversion simultaneously from 4 ADC channel, then how can 2 transfer controllers make then synchronized for simultaneous sampling?
How to solve this problem??
Thanks.
Hi Madhava,
1. Yes the destination buffer size is 16 bit.
2. This is the details of memory dump file.
Dump Summary ------------ Dump File: ccstudio.DMP : C:\Users\vishn\AppData\Local\Temp\ccstudio.DMP Last Write Time: 01-07-2024 15:36:06 Process Name: C:\ti\ccs1260\ccs\eclipse\ccstudio.exe Process Architecture: x64 Exception Code: not found Exception Information: Heap Information: Present System Information ------------------ OS Version: 10.0.22631 CLR Version(s): Modules ------- Module Name Module Path Module Version ----------- ----------- -------------- ccstudio.exe C:\ti\ccs1260\ccs\eclipse\ccstudio.exe 0.0.0.0 ntdll.dll C:\Windows\System32\ntdll.dll 10.0.22621.3733 kernel32.dll C:\Windows\System32\kernel32.dll 10.0.22621.3672 KERNELBASE.dll C:\Windows\System32\KERNELBASE.dll 10.0.22621.3733 user32.dll C:\Windows\System32\user32.dll 10.0.22621.3672 win32u.dll C:\Windows\System32\win32u.dll 10.0.22621.3733 gdi32.dll C:\Windows\System32\gdi32.dll 10.0.22621.3672 gdi32full.dll C:\Windows\System32\gdi32full.dll 10.0.22621.3672 msvcp_win.dll C:\Windows\System32\msvcp_win.dll 10.0.22621.3374 ucrtbase.dll C:\Windows\System32\ucrtbase.dll 10.0.22621.3593 comctl32.dll C:\Windows\WinSxS\amd64_microsoft.windows.common-controls_6595b64144ccf1df_6.0.22621.3672_none_2713b9d173822955\comctl32.dll 6.10.22621.3672 msvcrt.dll C:\Windows\System32\msvcrt.dll 7.0.22621.2506 imm32.dll C:\Windows\System32\imm32.dll 10.0.22621.3374 eclipse_11602.dll C:\ti\ccs1260\ccs\eclipse\plugins\org.eclipse.equinox.launcher.win32.win32.x86_64_1.2.400.v20211117-0650\eclipse_11602.dll 0.0.0.0 advapi32.dll C:\Windows\System32\advapi32.dll 10.0.22621.3733 sechost.dll C:\Windows\System32\sechost.dll 10.0.22621.3733 bcrypt.dll C:\Windows\System32\bcrypt.dll 10.0.22621.2506 rpcrt4.dll C:\Windows\System32\rpcrt4.dll 10.0.22621.3672 ole32.dll C:\Windows\System32\ole32.dll 10.0.22621.3672 combase.dll C:\Windows\System32\combase.dll 10.0.22621.3672 version.dll C:\Windows\System32\version.dll 10.0.22621.1 uxtheme.dll C:\Windows\System32\uxtheme.dll 10.0.22621.3672 msctf.dll C:\Windows\System32\msctf.dll 10.0.22621.3672 kernel.appcore.dll C:\Windows\System32\kernel.appcore.dll 10.0.22621.2715 bcryptPrimitives.dll C:\Windows\System32\bcryptPrimitives.dll 10.0.22621.3672 clbcatq.dll C:\Windows\System32\clbcatq.dll 2001.12.10941.16384 textinputframework.dll C:\Windows\System32\textinputframework.dll 10.0.22621.3672 oleaut32.dll C:\Windows\System32\oleaut32.dll 10.0.22621.3672 CoreMessaging.dll C:\Windows\System32\CoreMessaging.dll 10.0.22621.3672 CoreUIComponents.dll C:\Windows\System32\CoreUIComponents.dll 10.0.22621.3672 WinTypes.dll C:\Windows\System32\WinTypes.dll 10.0.22621.3672 CRYPTBASE.DLL C:\Windows\System32\CRYPTBASE.DLL 10.0.22621.1 jvm.dll C:\ti\ccs1260\ccs\eclipse\jre\bin\server\jvm.dll 11.0.13.0 psapi.dll C:\Windows\System32\psapi.dll 10.0.22621.1 winmm.dll C:\Windows\System32\winmm.dll 10.0.22621.3672 wsock32.dll C:\Windows\System32\wsock32.dll 10.0.22621.1 VCRUNTIME140.dll C:\Windows\System32\VCRUNTIME140.dll 14.38.33135.0 ws2_32.dll C:\Windows\System32\ws2_32.dll 10.0.22621.1 verify.dll C:\ti\ccs1260\ccs\eclipse\jre\bin\verify.dll 11.0.13.0 dbghelp.dll C:\Windows\System32\dbghelp.dll 10.0.22621.3593 dbgcore.dll C:\Windows\System32\dbgcore.dll 10.0.22621.1 java.dll C:\ti\ccs1260\ccs\eclipse\jre\bin\java.dll 11.0.13.0 jimage.dll C:\ti\ccs1260\ccs\eclipse\jre\bin\jimage.dll 11.0.13.0 zip.dll C:\ti\ccs1260\ccs\eclipse\jre\bin\zip.dll 11.0.13.0 shell32.dll C:\Windows\System32\shell32.dll 10.0.22621.3733 windows.storage.dll C:\Windows\System32\windows.storage.dll 10.0.22621.3733 SHCore.dll C:\Windows\System32\SHCore.dll 10.0.22621.3733 shlwapi.dll C:\Windows\System32\shlwapi.dll 10.0.22621.3672 profapi.dll C:\Windows\System32\profapi.dll 10.0.22621.3527 net.dll C:\ti\ccs1260\ccs\eclipse\jre\bin\net.dll 11.0.13.0 winhttp.dll C:\Windows\System32\winhttp.dll 10.0.22621.3672 mswsock.dll C:\Windows\System32\mswsock.dll 10.0.22621.2506 nio.dll C:\ti\ccs1260\ccs\eclipse\jre\bin\nio.dll 11.0.13.0 cryptsp.dll C:\Windows\System32\cryptsp.dll 10.0.22621.3672 rsaenh.dll C:\Windows\System32\rsaenh.dll 10.0.22621.1 userenv.dll C:\Windows\System32\userenv.dll 10.0.22621.3527 IPHLPAPI.DLL C:\Windows\System32\IPHLPAPI.DLL 10.0.22621.1 nsi.dll C:\Windows\System32\nsi.dll 10.0.22621.1 dhcpcsvc6.DLL C:\Windows\System32\dhcpcsvc6.DLL 10.0.22621.2506 dhcpcsvc.dll C:\Windows\System32\dhcpcsvc.dll 10.0.22621.2506 dnsapi.dll C:\Windows\System32\dnsapi.dll 10.0.22621.3733 swt-win32-4950r5.dll C:\ti\ccs1260\ccs\eclipse\configuration\org.eclipse.osgi\488\0\.cp\swt-win32-4950r5.dll 4.950.5.0 comdlg32.dll C:\Windows\System32\comdlg32.dll 10.0.22621.3672 winspool.drv C:\Windows\System32\winspool.drv 10.0.22621.3672 oleacc.dll C:\Windows\System32\oleacc.dll 7.2.22621.1 usp10.dll C:\Windows\System32\usp10.dll 10.0.22621.1 wininet.dll C:\Windows\System32\wininet.dll 11.0.22621.2506 propsys.dll C:\Windows\System32\propsys.dll 7.0.22621.3672 msimg32.dll C:\Windows\System32\msimg32.dll 10.0.22621.2506 urlmon.dll C:\Windows\System32\urlmon.dll 11.0.22621.3733 dwmapi.dll C:\Windows\System32\dwmapi.dll 10.0.22621.3672 iertutil.dll C:\Windows\System32\iertutil.dll 11.0.22621.3672 srvcli.dll C:\Windows\System32\srvcli.dll 10.0.22621.3374 netutils.dll C:\Windows\System32\netutils.dll 10.0.22621.2506 swt-gdip-win32-4950r5.dll C:\ti\ccs1260\ccs\eclipse\configuration\org.eclipse.osgi\488\0\.cp\swt-gdip-win32-4950r5.dll 4.950.5.0 GdiPlus.dll C:\Windows\WinSxS\amd64_microsoft.windows.gdiplus_6595b64144ccf1df_1.1.22621.3672_none_57feacb6ce14a323\GdiPlus.dll 10.0.22621.3672 WindowsCodecs.dll C:\Windows\System32\WindowsCodecs.dll 10.0.22621.3672 TextShaping.dll C:\Windows\System32\TextShaping.dll 10.0.22621.3672 mlang.dll C:\Windows\System32\mlang.dll 10.0.22621.1 localfile_1_0_0.dll C:\ti\ccs1260\ccs\eclipse\configuration\org.eclipse.osgi\285\0\.cp\os\win32\x86_64\localfile_1_0_0.dll 0.0.0.0 win32refresh.dll C:\ti\ccs1260\ccs\eclipse\configuration\org.eclipse.osgi\290\0\.cp\os\win32\x86_64\win32refresh.dll 0.0.0.0 dataexchange.dll C:\Windows\System32\dataexchange.dll 10.0.22621.3672 twinapi.appcore.dll C:\Windows\System32\twinapi.appcore.dll 10.0.22621.3672 LibraryLoader.dll C:\ti\ccs1260\ccs\ccs_base\DebugServer\bin\LibraryLoader.dll 12.6.0.3269 msvcp140.dll C:\Windows\System32\msvcp140.dll 14.38.33135.0 VCRUNTIME140_1.dll C:\Windows\System32\VCRUNTIME140_1.dll 14.38.33135.0 ti_logger.dll C:\ti\ccs1260\ccs\ccs_base\common\bin\ti_logger.dll 12.6.0.3269 CCReg.dll C:\ti\ccs1260\ccs\ccs_base\common\bin\CCReg.dll 12.6.0.3269 fsutil.dll C:\ti\ccs1260\ccs\ccs_base\common\bin\fsutil.dll 12.6.0.3269 libusb-1.0.dll C:\ti\ccs1260\ccs\ccs_base\common\bin\libusb-1.0.dll 1.0.19.10903 MiniDump.dll C:\ti\ccs1260\ccs\ccs_base\common\bin\MiniDump.dll 12.6.0.3269 setup_parser.dll C:\ti\ccs1260\ccs\ccs_base\common\bin\setup_parser.dll 12.6.0.3269 xerces-c_2_8.dll C:\ti\ccs1260\ccs\ccs_base\common\bin\xerces-c_2_8.dll 2.8.0.0 ti_targetdb_parser.dll C:\ti\ccs1260\ccs\ccs_base\common\bin\ti_targetdb_parser.dll 5.0.2.0 ti_xpcom.dll C:\ti\ccs1260\ccs\ccs_base\DebugServer\bin\ti_xpcom.dll 12.6.0.3269 DirectoryService.dll C:\ti\ccs1260\ccs\ccs_base\DebugServer\bin\DirectoryService.dll 12.6.0.3269 XPCOMUtility.dll C:\ti\ccs1260\ccs\ccs_base\DebugServer\bin\XPCOMUtility.dll 12.6.0.3269 DWrite.dll C:\Windows\System32\DWrite.dll 10.0.22621.3672 toolkit64.dll C:\ti\ccs1260\ccs\eclipse\configuration\.jxbrowser.bin\7.29\toolkit64.dll 0.0.0.0 ipc64.dll C:\ti\ccs1260\ccs\eclipse\configuration\.jxbrowser.bin\7.29\ipc64.dll 0.0.0.0 XPCOMTILogger.dll C:\ti\ccs1260\ccs\ccs_base\DebugServer\bin\XPCOMTILogger.dll 12.6.0.3269 explorerframe.dll C:\Windows\System32\explorerframe.dll 10.0.22621.3672 jWinHttp-1.0.0.dll C:\ti\ccs1260\ccs\eclipse\configuration\org.eclipse.osgi\288\0\.cp\jWinHttp-1.0.0.dll 0.0.0.0 rasadhlp.dll C:\Windows\System32\rasadhlp.dll 10.0.22621.1 proxy_vole5503326919132165432.dll C:\Users\vishn\AppData\Local\Temp\proxy_vole5503326919132165432.dll 0.0.0.0 edputil.dll C:\Windows\System32\edputil.dll 10.0.22621.3527 cToolsIF.dll C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\cToolsIF.dll 2.1.0.0 ctools.dll C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\ctools.dll 2.3.0.0 TraceFactory.dll C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\TraceFactory.dll 0.0.0.0 sqlite3.dll C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\sqlite3.dll 0.0.0.0 CloudTrace.dll C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\CloudTrace.dll 0.0.0.0 AETPropertyHelper.dll C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\AETPropertyHelper.dll 1.2.0.0 ti_aett_session.dll C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\ti_aett_session.dll 0.0.0.0 sunmscapi.dll C:\ti\ccs1260\ccs\eclipse\jre\bin\sunmscapi.dll 11.0.13.0 crypt32.dll C:\Windows\System32\crypt32.dll 10.0.22621.3672 ncrypt.dll C:\Windows\System32\ncrypt.dll 10.0.22621.3672 ntasn1.dll C:\Windows\System32\ntasn1.dll 10.0.22621.1 sunec.dll C:\ti\ccs1260\ccs\eclipse\jre\bin\sunec.dll 11.0.13.0 management.dll C:\ti\ccs1260\ccs\eclipse\jre\bin\management.dll 11.0.13.0 management_ext.dll C:\ti\ccs1260\ccs\eclipse\jre\bin\management_ext.dll 11.0.13.0 DebugServer.dll C:\ti\ccs1260\ccs\ccs_base\DebugServer\bin\DebugServer.dll 12.6.0.3269 tiofr11.dll C:\ti\ccs1260\ccs\ccs_base\DebugServer\bin\tiofr11.dll 12.6.0.3269 NapiNSP.dll C:\Windows\System32\NapiNSP.dll 10.0.22621.1 pnrpnsp.dll C:\Windows\System32\pnrpnsp.dll 10.0.22621.1 winrnr.dll C:\Windows\System32\winrnr.dll 10.0.22621.1 nlansp_c.dll C:\Windows\System32\nlansp_c.dll 10.0.22621.3672 wshbth.dll C:\Windows\System32\wshbth.dll 10.0.22621.3374 FWPUCLNT.DLL C:\Windows\System32\FWPUCLNT.DLL 10.0.22621.3235 ninput.dll C:\Windows\System32\ninput.dll 10.0.22621.3672 DebugProperties.dll C:\ti\ccs1260\ccs\ccs_base\DebugServer\bin\DebugProperties.dll 12.6.0.3269 spawner.dll C:\ti\ccs1260\ccs\eclipse\plugins\org.eclipse.cdt.core.win32.x86_64_6.0.500.202203091838\os\win32\x86_64\spawner.dll 0.0.0.0 ntmarta.dll C:\Windows\System32\ntmarta.dll 10.0.22621.1 GTIRemoteProxy.dll C:\ti\ccs1260\ccs\ccs_base\DebugServer\bin\GTIRemoteProxy.dll 12.6.0.3269 jtagdata.dll C:\ti\ccs1260\ccs\ccs_base\common\uscif\jtagdata.dll 35.35.0.0 cfgmgr32.dll C:\Windows\System32\cfgmgr32.dll 10.0.22621.2506 setupapi.dll C:\Windows\System32\setupapi.dll 10.0.22621.2506 winusb.dll C:\Windows\System32\winusb.dll 10.0.22621.1 hid.dll C:\Windows\System32\hid.dll 10.0.22621.1 devobj.dll C:\Windows\System32\devobj.dll 10.0.22621.2506 wintrust.dll C:\Windows\System32\wintrust.dll 10.0.22621.3737 msasn1.dll C:\Windows\System32\msasn1.dll 10.0.22621.2506 ti_aett_logger.dll C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\ti_aett_logger.dll 0.0.0.0 ti_aett_setup_manager.DLL C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\ti_aett_setup_manager.DLL 0.0.0.0 ICETargetAdapter.DLL C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\ICETargetAdapter.DLL 1.3.0.0 IceCD.dll C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\IceCD.dll 1.3.0.0 ti_aett_database.dll C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\ti_aett_database.dll 0.0.0.0 lldbSM.dll C:\ti\ccs1260\ccs\ccs_base\DebugServer\bin\lldbSM.dll 16.0.1310.0 System_xmtr.DLL C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\System_xmtr.DLL 0.0.0.0 proxy_vole8770055297768816587.dll C:\Users\vishn\AppData\Local\Temp\proxy_vole8770055297768816587.dll 0.0.0.0 awt.dll C:\ti\ccs1260\ccs\eclipse\jre\bin\awt.dll 11.0.13.0 apphelp.dll C:\Windows\System32\apphelp.dll 10.0.22621.3672 WebView2Loader.dll C:\ti\ccs1260\ccs\eclipse\configuration\org.eclipse.osgi\488\0\.cp\WebView2Loader.dll 1.0.721.0 EmbeddedBrowserWebView.dll C:\Program Files (x86)\Microsoft\EdgeWebView\Application\126.0.2592.68\EBWebView\x64\EmbeddedBrowserWebView.dll 126.0.2592.68 sspicli.dll C:\Windows\System32\sspicli.dll 10.0.22621.3672 Windows.System.Launcher.dll C:\Windows\System32\Windows.System.Launcher.dll 10.0.22621.3672 msvcp110_win.dll C:\Windows\System32\msvcp110_win.dll 10.0.22621.1 windows.staterepositorycore.dll C:\Windows\System32\windows.staterepositorycore.dll 10.0.22621.3672 AETProperties.DLL C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\AETProperties.DLL 0.0.0.0 tixds510debugssm.dvr C:\ti\ccs1260\ccs\ccs_base\emulation\drivers\tixds510debugssm.dvr 1.0.0.0 xdsfast3.dll C:\ti\ccs1260\ccs\ccs_base\common\uscif\xdsfast3.dll 35.35.0.0 prsc.dll C:\ti\ccs1260\ccs\ccs_base\emulation\drivers\prsc.dll 5.1.2.0 tixds510cs_dap.dvr C:\ti\ccs1260\ccs\ccs_base\emulation\drivers\tixds510cs_dap.dvr 5.0.1.0 cmapi.dll C:\ti\ccs1260\ccs\ccs_base\emulation\drivers\cmapi.dll 1.1.0.0 jscxds110.dll C:\ti\ccs1260\ccs\ccs_base\common\uscif\jscxds110.dll 35.35.0.0 tixds510cortexR.dvr C:\ti\ccs1260\ccs\ccs_base\emulation\drivers\tixds510cortexR.dvr 11.0.2.0 tixds510cortexM.dvr C:\ti\ccs1260\ccs\ccs_base\emulation\drivers\tixds510cortexM.dvr 11.2.2.0 tixds510pru.dvr C:\ti\ccs1260\ccs\ccs_base\emulation\drivers\tixds510pru.dvr 2.0.2.0 tixds510csstm.dvr C:\ti\ccs1260\ccs\ccs_base\emulation\drivers\tixds510csstm.dvr 4.0.1.0 tixds510etbcs.dvr C:\ti\ccs1260\ccs\ccs_base\emulation\drivers\tixds510etbcs.dvr 4.1.1.0 tpi_icepick.dll C:\ti\ccs1260\ccs\ccs_base\emulation\tpi\tpi_icepick.dll 4.0.1.0 xdsboard.dll C:\ti\ccs1260\ccs\ccs_base\common\uscif\xdsboard.dll 35.35.0.0 tpi_cs_dap.dll C:\ti\ccs1260\ccs\ccs_base\emulation\tpi\tpi_cs_dap.dll 5.0.1.0 tpiarm_x.dll C:\ti\ccs1260\ccs\ccs_base\emulation\tpi\tpiarm_x.dll 34.0.0.0 tpi_ihwa.dll C:\ti\ccs1260\ccs\ccs_base\emulation\tpi\tpi_ihwa.dll 5.0.5.0 tpitrace.dll C:\ti\ccs1260\ccs\ccs_base\emulation\tpi\tpitrace.dll 4.0.0.0 tpietb.dll C:\ti\ccs1260\ccs\ccs_base\emulation\tpi\tpietb.dll 4.0.1.0 ctoolsndbg.DLL C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\ctoolsndbg.DLL 2.1.0.0 TraceOperationServer.DLL C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\TraceOperationServer.DLL 0.0.0.0 xdstrove.dll C:\ti\ccs1260\ccs\ccs_base\common\uscif\xdstrove.dll 35.35.0.0 xdslocal.dll C:\ti\ccs1260\ccs\ccs_base\common\uscif\xdslocal.dll 35.35.0.0 xdsroute.dll C:\ti\ccs1260\ccs\ccs_base\common\uscif\xdsroute.dll 35.35.0.0 xdsicicle.dll C:\ti\ccs1260\ccs\ccs_base\common\uscif\xdsicicle.dll 35.35.0.0 DeviceIdentifier.DLL C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\DeviceIdentifier.DLL 0.0.0.0 ti_aett_radar.DLL C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\ti_aett_radar.DLL 0.0.0.0 ct470api.dll C:\ti\ccs1260\ccs\ccs_base\emulation\analysis\bin\ct470api.dll 0.0.0.0 FlashSitaraMCU.dll C:\ti\ccs1260\ccs\ccs_base\DebugServer\bin\FlashSitaraMCU.dll 0.0.0.0
Hi Tej,
The Memory Browser image was what I requested. thanks.
When i am sampling ADCs from the reset this is the graph i am getting ( Graph is for the 100KHz signal getting sampled at 4MSPS).
This image you have shared, this seems like the samples are not taken at the same time (reason : same sample, different voltage point on the same input). Can you confirm if you had 40 samples per input cycle when you had only 2 DMA channels and 2 ADCs?
Also, Could you confirm if you are enabling the ADC SOC trigger from EPWM before or after configuring the DMA channels?
Thanks and regards,
Madhava
Hi Madhava,
1. This is the graph for sampling rate 4MSPS with signal of 100KHz.
Number of samples points for each cycle is in range 39-40.
2. I am enabling ADC SOC trigger from EPWM after configuring the DMA channels.
Thanks.
Hi Madhava,
This is the value of register during execution of program.
Can you exactly point out the register whose value you are interested in??
Thanks.