Tool/software:
Hi,
Kindly confirm the connection of EMIF address lines for External Flash U2 and SRAM U3 in attached schematic diagram.
As per the Reference Manual Figure 21.8 The conneection for 16 bit Memory is different. ie. EMIF ADD 0 shall be connected to memory ADD1.
Kindly confirm. 
EMIF_16Bit_.pdf
Hi Amit,
My apologies I just overlooked schematic previously, as customer given EMIFA0 and EMIFBA1 to the A0 of the memory, I just assumed EMIFBA1 connecting to the A0 but now I realized all other pins are not shifted that means EMIFA0 not connected to A1 of the memory and so on.
The TRM was correct, the connection should be as below for 16-bit asynchronous memory.
This is because, if we verify the TRM there is a sentence, “The EMIF address pin EMIF_A[0] always provides the least significant bit of a 32-bit word address. Therefore, when interfacing to a 16-bit or 8-bit asynchronous device, the EMIF_BA[1] and EMIF_BA[0] pins provide the least-significant bits of the halfword or byte address, respectively.”
This means that, if we are interfacing with 32-bit asynchronous memory then EMIF_A[0] will act as a bit-0 of the address. But if we are interfacing with 16-asynchrouns memory then EMIF_A[0] will act as bit-1 of the address, because now least significant bit does not represent the 32-bit address and it is just a 16-bit address, so that means bit-1 will be represents the 32bit address. As TRM mentioned EMIF_A[0] will always be the least significant bit of the 32-bit address right. So that is the reason BA1 should be connected to the A0 of the memory and EMIF_A[1] should need to connect to the A1 of the 16-bit synchronous memory.
--
Thanks & regards,
Jagadish.
