AM2434: Sigma Delta + Biss-C example project

Sigma Delta and Biss-C applications should have separate memory regions and do not conflict. Configure communication between the two PRUs if necessary.

Hi Ariel,

There is an example in motor control sdk where the EnDAT and SDFM application running on the same slice (ICSSG0). You can refer this example for your use case where you need sdfm on one pru and Biss-C on another pru of icssg1 slice.

examples\tidep_01032_dual_motor_drive\single_chip_servo\am243x-lp\r5fss0-0_nortos

MOTOR-CONTROL-SDK-AM243X Software development kit (SDK) | TI.com

As this example and BiSS-C sdk example are using ICSSG0 so you have to make some SysConfig and code changes to use ICSSG1

Require changes: 

• Need to select corresponding PRUs of ICSSG1 instance in SysConfig 
  • single_chip_servo\am243x-lp\r5fss0-0_nortos example does not use SDFM SysConfig settings for SDFM but In your case better to use SDFM SysConfig settings instead of doing SDFM pin settings manually 
• INTC configuration, manual addition is needed
  • Add INTC configuration in SysConfig for ICSSG1
  • 
  • Update "icss0_intc_initdata" variable with "icss1_intc_initdata" in bissc_periodic_trigger.c file  
  • 

Thanks & Regards,

Achala Ram

Hi again,

Sorry for the late response but I have a follow up question regarding the clock configuration.

When I configure the BiSS-C via SysConfig it locks my ICSSG core clock value at 200kHz

However, in your SDFM example AND the single chip example you set the clock to 300kHz (both the core and IEP).

I would like to know the reason for this limitation and what are the correct configuration to support both applications.

Thanks!

Hi Ariel,

Ariel Ronen said:

When I configure the BiSS-C via SysConfig it locks my ICSSG core clock value at 200kHz

There is a bug in the BiSS-C Sysconfig module, so it is not allowing the other core clock value to be selected instead of 200mhz

In Biss-c Sysconfig meta file (\source\.meta\position_sense\bissc.syscfg.js), it is hard coded to 200mhz.

You have to disable this "coreClk: 200*1000000," line then SysConfig will allow to select other pru core clock values.

Thanks & Regards,

Achala Ram

Ariel Ronen said:

I would like to know the reason for this limitation and what are the correct configuration to support both applications

BiSS-C firmware do not have any limitation with pru core clock. It has been tested with 300 MHz and 200 MHz. But for SDMF firmware, pru core clock value depends on the number of SDFM channels, sample mode etc.

If you want to use the following features with one pru core, there is a limit that you have use >= 300mhz core clock or sdfm clock <= 20mhz.

• 3 Channels on one PRU core
• Trigger based Normal and continuous Over current for each channel
  
  

Thanks & Regards,

Achala Ram