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AM2634: CacheP_wbInv Queries for AM2634 Device

Cesc Yang
Prodigy 221 points
Part Number: AM2634

Tool/software:

Hi TI,

I have a few questions related to cache operations that need clarification on:

  1. Cache Capacity of CacheP_wbInv: What is the maximum amount of data that CacheP_wbInv can handle in one invocation? Can it process more than 16KB at a time?
  2. Non-Cached Regions and CacheP_wbInv: If an array is located in a memory region configured as NON-CACHED through the MPU, does invoking the CacheP_wbInv interface on this address have any effect?
  3. Cache Operations for Struct Pointers in SIPC: Consider a scenario where we define a struct variable used in SIPC, one of its members being a pointer that is assigned a value on the HSM side without prior initialization. In this case, is it necessary to perform a CacheP_wbInv operation for this pointer?

These clarifications are crucial for optimizing our system's performance and ensuring correct data handling. I appreciate your timely response to these queries.

Thank you very much.

Best regards,

  • 0 in reply to Nilabh Anand
    Prodigy 221 points

    Hi Anand,

     
    I would like to outline my current understanding regarding cache operations to ensure that I am proceeding correctly:

    1. If there is an array HsmArray located within the L2OCRAM memory area and it needs to be transmitted via SIPC, my understanding is that I do not need to call CacheP_wbInv because, according to the cache APIs documentation, the R5 core only supports CacheP_TYPE_L1P and CacheP_TYPE_L1D.

    2. If there is an array HsmArray of 32KB size, not located in the L2OCRAM memory area, and needs to be transmitted via SIPC with the memory area configured as cached, the manual states that the cache size is 16KB. In this case, I still need to execute:

      uint32_t alignedArrayCacheSize = (sizeof(HsmArray) + CacheP_CACHELINE_ALIGNMENT) & ~(CacheP_CACHELINE_ALIGNMENT - 1); CacheP_wbInv(HsmArray, alignedArrayCacheSize, CacheP_TYPE_ALL);

      even though the array size exceeds the cache size.

    3. Consider a scenario where a structure Struct is defined with two members, and is sent to the HSM core via SIPC: CipherPtr (to hold encrypted data) and PlainPtr (for example, to hold plaintext data decrypted by HSM).  If I assign a value to &Struct->CipherPtr (insert encrypted data) and PlainPtr has not been assigned or initialized on the R5 core, before sending the structure's address via SIPC, it is necessary to perform CacheP_wbInv for the structure Struct. It is also required for the pointer &Struct->CipherPtr, but not for the pointer &Struct->PlainPtr.

    Please review the above points and advise if my understanding are correct.

    Thank you for your guidance.

    Best regards.

  • 0 in reply to Cesc Yang
    TI__Mastermind 44514 points

    Hi Yang,

    I will get back with an reply by early next week no later than wednesday.