TMS570LC4357: Cache invalidation by address

Paul Sheppard

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Tool/software:

Following on from:

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1158788/faq-tms570lc4357-how-to-solve-the-cache-coherency-issues-when-accessing-the-shared-memory-through-cpu-and-dma/4356840#4356840

The two mentioned functions ( coreInvalidateDCByAddress() & coreCleanDCByAddress() ) appear not to be available in HalcoGen.

Where can I find these?

Thanks

over 2 years ago

0 jagadish gundavarapu over 2 years ago

TI__Guru* 78436 points

Hi Paul,

I too verified it and find that you are correct.

All i can see is _dCacheInvalidate_ and _iCacheInvalidate_ in HALCoGen generated code.

I am checking with my senior colleague and i will get back to you soon.

--
Thanks & regards,
Jagadish.

0 Paul Sheppard over 2 years ago in reply to jagadish gundavarapu

Prodigy 130 points

Indeed, there's not even a flush/clean cache.

That would be great, thanks

While we're in that area a _setCPSRValue_() would be nice too.

In comparison to NXP's SDK offering, TI's is somewhat disappointing

+1 jagadish gundavarapu over 2 years ago in reply to Paul Sheppard

TI__Guru* 78436 points

Hi Paul,

I discussed this with the person who created that FAQ. He mentioned that these functions are not generating by ( coreInvalidateDCByAddress() & coreCleanDCByAddress() ) by HALCoGen.

He told me that these operations can be found in the cortex-R5 TRM.

1067.DDI0460C_cortexr5_trm.pdf

In above TRM, please refer the section 4.3.22 (Cache operations).

Here they have given how to perform different cache operations:

As these entire operations are not generating by HALCoGen, we should need to create our API's based on requirements.

Thanks & regards,
Jagadish.

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TMS570LC4357: Cache invalidation by address