AM2432: SDL Usage Inquiry

Hello Expert:

I have two more questions for which I am awaiting your response:
1. The TRM states that ESM0 does not have the capability to control the MCU_SAFETY_ERRORn pin. In the context of SDL, is the errorpinBitmap parameter in the SDL_ESM_InitConfig_s configuration for ESM0 still relevant?
2. Which interrupt source is generated by the VIM SRAM Data ECC with DED Vector diagnostic feature in R5F.VIM1?

Thank you.

Hello,

Jimmy said:

1. Since the R5FSS ECC aggregator is only used in error-injection mode, which ECC aggregator is employed for Memory ECC diagnostic measures in the Security Manual when implemented? What is the required memory sub-type initialization?

The R5F has an internal ECC mechanism which detects any errors in the R5F internal memories(TCM,caches). The TI R5F ECC Aggr can only inject an error into the R5F memories and error correction and detection is taken care internally by the R5F core. 

Jimmy said:

2. Which ECC aggregator is utilized for Memory ECC diagnostic measures on-chip SRAM under normal conditions? And which aggregator would be used to inject errors if needed?

You can use the below aggregators to inject error and enable ECC for SRAM.

Jimmy said:

1. The TRM states that ESM0 does not have the capability to control the MCU_SAFETY_ERRORn pin. In the context of SDL, is the errorpinBitmap parameter in the SDL_ESM_InitConfig_s configuration for ESM0 still relevant?

No, the errorpinBitmap parameter will not do anything for Main ESM. 

I am looking into your other questions. I will give you an update soon.

Regards,

Nihar Potturu

Hello Expert:

Thank you for your response. Based on your explanation, I have gained some clarity on my questions, but there are still a few points of confusion:
1. As I understand it, when performing R5FSS-Memory ECC diagnostic actions, there is no need for additional ECC initialization; only the corresponding ESM events need to be enabled. In the ESM callback, there's no requirement to clear R5F ECC events (since there is no aggregator). Am I correct in this understanding?
2. Which ESM event source is associated with the R5FSS-Memory ECC diagnostic procedure? I noticed two different sets, so does this measure require enabling the PMU module?

Please address the remaining questions:
3. Under what conditions is the SDL_ECC_AGGR1 aggregator used?
4. Which ESM event source is generated by the CBA4 - Override register parity diagnostic feature?
5. What interrupt source is produced by the VIM SRAM Data ECC with DED Vector diagnostic functionality in R5F.VIM1?

Thank you.

Hello expert, do you have any updates on my question? Thank you for your response.