Tool/software:
I am trying to PWM a brake with an N2HET, my hardware has separate Hi-side and LO-side FET drivers, so I have to insure both FETs are not on at the same time (essentially a SW deadtime).
Ignoring the CNT and BR instructions, my N2HET code looks like:
1. Using ECMP (data = 0), set Lo-side on after HR-delay
2. Using ECMP (data = 0), set Hi-side off immediately
3. Using MCMP (data set by host), set Lo-side off -- if true, execute next statement
4. Using MCMP (data = 0), set Hi-side on after HR-delay
This all works except for the ECMP delay.
If I add a delay only to MCMP, the trailing edges are perfectly delayed.
If I add the same delay to first ECMP, the lo-side never gets cleared (SET always)
I have 2 questions:
1. Am I allowed to have 2 hr_delays in one LRP? The TRM is a little unclear. It looked like 2
hr_delays are OK as long as they are on separate pins.
2. Is the ECMP delay somehow skipping over the next Lo-side MCMP (because the delay is 1/2 LRP)?
Thanks,
Jim
Here is my actual N2HET code:
L00 CNT { reqnum=0, request=NOREQ, reg=A, irq=OFF, max=PWM_PERIOD};
L01 ECMP { next=L02, hr_lr=HIGH, en_pin_action=ON, cond_addr=L02, pin=PWM_BRAKEALO,
action=SET, reg=A, irq=OFF, data=0, hr_data=64};
L02 ECMP { next=L03, hr_lr=LOW, en_pin_action=ON, cond_addr=L03, pin=PWM_BRAKEAHI,
action=CLEAR, reg=A, irq=OFF, data=0, hr_data=0};
L03 MCMP { next=L05, hr_lr=LOW, en_pin_action=ON, cond_addr=L04, pin=PWM_BRAKEALO,
action=CLEAR, reg=A, irq=OFF, data=INIT_COMPARE, hr_data=0, order=REG_GE_DATA};
L04 MCMP { next=L05, hr_lr=HIGH, en_pin_action=ON, cond_addr=L05, pin=PWM_BRAKEAHI,
action=SET, reg=A, irq=OFF, data=0, hr_data=64, order=REG_GE_DATA};
L05 BR { next= L00, cond_addr=L00, event= NOCOND }
