• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 30 subscribers
  • Views 1161 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

FPU performance

Kjetil46144
Prodigy 180 points
Other Parts Discussed in Thread: TMS570LS20216

Any pointers to cycle count for double precision math instructions?

  • 0
    Prodigy 110 points

    Hi, I'm also looking for performance numbers for both double and single precision floating point operations, (specially multiplication).

    I'll check out ARM 'R4 architecture docs, but real world numbers from TI's TMS570 implementation would be better, of course (and greatly appreciated). I'm deciding to use an MCBTMS570 board and I/O board, with a TMS570LS20216 chip

    Kind regards,

    Sebastian.-

     

     

     

  • 0 in reply to Sebas
    Prodigy 110 points

    OK, just found it in ARM's Cortex-R4(F) TRM doc (DDI 0363E), chpt. 14 "Cycle Timings and Interlock Behavior".  I suppose the implemented core in TMS570LS20216 is v.  r1p3, as its the only one mentioned in TI's TMS570LS Series TRM doc. (SPNU489C). Please correct me if I'm wrong.

     

    So now my question is:   Are there any performance limitations in TI's TMS570 SoC implementation ? That is, both FPU throughput and latency, as seen from an application.

     

    Kind regards,

    Sebastian.-

     

  • 0 in reply to Sebas
    Prodigy 180 points

    Thank you very much for your response and pardon my rather basic questions; I've not yet gotten to the instruction set of these as they are for an upcoming project due in a month or two. I've never touched them before, apart from looking at the example code and verifying that it compiles on my limited copy of CCS that came with the evaluation boards (mine are actually the RM4 type, but I presume FPU architecture applies to both families).

    I'm looking at table 14-9 with multiplication latencies but are not immidiatly able to tell which (if any) of the instructions are floating point. Care to set it straight for me?

     

    Regards,

    Kjetil

    EDIT: table 14-9 of the ARM's Cortex-R4(F) TRM, that is.

  • 0 in reply to Kjetil46144
    TI__Mastermind 49120 points

    Hello,

    The table 14-9 gives information about the multiply instructions executed by the integer unit. The information about the floating-point instructions is in sections 14.19 through 14.22.

    There are no additional limitations on the FPU imposed by the TMS570 implementation.

    As for the version of the Cortex-R4F CPU, the TMS570LS20216x microcontrollers have the version r1p2. The newer TMS570LS31x/21x and the RM48x microcontrollers have the version r1p3 of the Cortex-R4F CPU.

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Prodigy 180 points

    Excellent. Thanks to both of you.

     

    Regards,

    Kjetil