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Original question:

RM48L952: Understanding Mibspi dma data size

TMS570LC4357: MIBSPI TGENA not clearing after DMA->SPI transfer completes

Paul Sheppard
Prodigy 60 points

Tool/software:

Following on from:

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/996614/rm48l952-understanding-mibspi-dma-data-size

I have a similar setup, where I have TGs of length 1 8-bit element, using frame size to vary the transfer length. TG one-shot is disabled (DMACTRL enabled)

Data is getting from normal RAM to the SPI bus via DMA to the TxRAM buffers ok - I can see that on the 'scope. But I have 2 issues:

1. TGENA  is never cleared and TGTDx also remains set - This means the transfer occurs only once.

2. The CS doesn't de-assert once the transfer completes (CSHOLD is enabled, as I don't want is to be de-asserted between elements) .

Should the DMA completing not clear TGENA ? Do I have to set up an interrupt to do this?

Since I only have 1 buffer in the transfer group, I can't disable CSHOLD in the last buffer, so how do I get around this?

Many thanks.

  • 0
    TI__Guru 57560 points

    Hi Paul,

    Paul Sheppard said:
    I have a similar setup, where I have TGs of length 1 8-bit element,

    I don't understand this!

    why you are trying to make TG length as one element. If you are trying to use TG as 1 element, then you can go for SPI instead of MibSPI right?

    In mibSPI the TG length usually more than one byte and can be equal to the number of elements you want to transfer with single trigger.

    Hercules Tutorial: MibSPI and DMA Overview (youtube.com)

    You can refer above thread to understand how they are using TG as 127 elements size.

    Paul Sheppard said:
    2. The CS doesn't de-assert once the transfer completes (CSHOLD is enabled, as I don't want is to be de-asserted between elements) .

    If you want to control CSHOLD in between the transfers, then you can do one thing.

    Instead of doing 8-bit transfers from DMA you can do 32-bit transfers. I mean you can also do the control information transfer also along with data transfer.

    I got this requirement previously, please refer below thread once:

    (2) TMS570LS3137: Sending multiple 24 bit transfer groups - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

    Precisely look at below comment in above thread:

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 60 points

    The use case is to have a 'generic' interface where any length can be transferred (e.g. for configuring the device) and then use another TG of a fixed length for the regular transfers.

    I did try the interrupt approach in the end, to clear the TGENA and re-set the RX/TXDMAENA bits, and that's working as far as resetting the TG. I can repeat the transfer in my task now. CS is still an issue though.

    I had thought of the control part transfer too, but then that kinda defeats the point of using the DMA at all, since you'd have to do that copying up-front.

    The issue with the RAM buffers, is they don't lend themselves to being dynamically re-sizeable, since they are sequential. 

    Another thought is to size the TG large, and only use a portion of them. i,e 4 TGs, each with 32 entries allocated. Transfers set up to use what is needed up to the limit - However, reading around I've not seen if this can be done. Everything I've seen points to the buffer length and transaction length having to be the same. Is this approach possible?

    Many thanks for you help!

  • 0 in reply to Paul Sheppard
    Prodigy 60 points
    Paul Sheppard said:
    Another thought is to size the TG large, and only use a portion of them. i,e 4 TGs, each with 32 entries allocated.

    ...And I've just realised that this would also require resetting of the control bits in the Tx buffers to ensure the last entry for the given transfer size disables the CSHOLD.

    Hmm.

    Edit: Well a bit - can store the last size transferred and restore that buffer entry, then set the buffer entry for the next transfer.

  • +1 in reply to Paul Sheppard
    Prodigy 60 points

    OK, I think I go something that's looking like it should.

    So, over-sized TGs (4x 32 for me),

    Configure Tx buffs with BUFMODE 3 (skip), CSHOLD enabled

    Each transfer:

    Set CSHOLD on previous size transfer buffer, clear for the new sized transfer

    Set DMA ELCNT to new transfer size

    Set DMACTRL BUFID to the last buffer for the new transfer size (same buf as CSHOLD disabled)

    Set DMACTRL Tx/RXDMAENA

    Go...

    In interrupt:

    Clear TGCTRL TGENA

  • 0 in reply to Paul Sheppard
    TI__Guru 57560 points

    Hi Paul,

    Your approach looks fine for me.

    --
    Thanks & regards,
    Jagadish.