MSPM0G1507: frequency of the PLL output clock changes while using external clock as input after resetting the microcontroller

Hi Pritesh,

Can you explain a little further what behavior you are seeing? Such as an example of the different clock outputs that you are seeing? Also, this only occurs when power cycling the board, does it return to the correct frequency after some time or does it remain the incorrect frequency until you have power cycled again?

PLL output frequency change happens on resetting as well as power cycling the microcontroller,
Ex. if the clock output is expected to give output as 24 MHz, then sometimes it gives 13 MHz, 32 MHz randomly. 
it does not return to correct frequency after some time (we observed for 5 mins),
After power cycle or reset, frequency gets changed but probability of getting correct frequency is 2 out of 5 times doing power cycle/reset.

I see, thank you for the information.

Are you using one of our premade examples in the SDK to do this? If not, are you using Sysconfig to set up the clock configuration? 

Additionally, what are you using as the external HFCLK source? Does it fit the specifications mentioned in our datasheet?

What I am getting at is I am wondering if the clock source is a valid input, and if we are taking the steps to properly set the HFCLK input as the source for the PLL. For example, are you checking the HFCLK Startup Monitor before switching to use it as the clock source? You can read more about this in our technical reference manual, specifically in section 2. Section 2.3.4.3.3 contains information on the HFCLK startup monitor.