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AM2432: Sigma Delta clock generator source

Gael Messager
Prodigy 40 points
Part Number: AM2432
Other Parts Discussed in Thread: SYSCONFIG,

Tool/software:

Hello TI support,

from the Motor Control SDK 09.02, I'm using the SDFM example with phase compensation which we need to get reliable data.

In the TI example, the clock (SYNC_OUT1) returning as "clock in" (SD8_CLK) has to be rooted externally, with a physical wire.

Is it possible to do this connection internally, without having to root any external wire? From the TRM I understand that the SDFM only accepts external signals. In our PCB design, we have a conflict of GPIO if we must use external signal.

Thank you, regards, Gael Messager

  • 0
    TI__Intellectual 2700 points

    Hi Gael,

    Gael Messager said:
    Is it possible to do this connection internally, without having to root any external wire?

    There is no such internal mapping for the sdfm module, but there are other options to source the sd clock in the sdfm module if you have the gpio conflict with sd8_clk pin.
    There are three ways to source the clock in the sdfm module.

    1. pr<k>_pru<n>_sd8_clk (SD8_clk): common clock source for all 9 SDFMs, all sdfm examples using SD8_clk as clock source.
    2. pr<k>_pru<n>_sd<i>_clk:   independent clock source for each SDFMs
    3.  pr<k>_pru<n>_sd0_clk for sd0, sd1, and sd2;   pr<k>_pru<n>_sd3_clk for sd3, sd4, and sd5;  pr<n>_pru<k>_sd6_clk for sd6, sd7, and sd8
      1. pr<k>_pru<n>_sd0_clk :  same clock for all three SDFMs (0-2)
      2. pr<k>_pru<n>_sd3_clk : same clock for next three SDFMs(3-5)
      3. pr<k>_pru<n>_sd6_clk : same clock for next three SDFMs(6-8)

    Please see the section: 4.5.2.2.3.5.1 in TRM for Sigma Delta clock GPIOs mapping for more details

    You can configure and use any suitable clock source option from the sdfm Sysconfig module.

    Thanks & regards,

    Achala Ram

  • 0 in reply to Achala Ram
    Prodigy 40 points

    Hello Achala,

    thank you for your answer. Sorry, I was not precise enough on my question:

    Our problem does not concern SD_CLK (which are all available) but SYNC_OUT. The example requires both SYNC_OUT0 and 1 for phase compensation. These  can only be rooted to W1 and U1 of AM2432 (on the ALV variante). W1 is conflicting in our case. That is why we would like to get SYNC_OUT on SD_CLK without external connection.

    If I understand you correctly, there is no other alternate to root internally, right?

    Thank you for the support, regards, Gael Messager

  • +1 in reply to Gael Messager
    TI__Intellectual 2700 points
    Gael Messager said:
    If I understand you correctly, there is no other alternate to root internally, right?

    Yes right, there is no way to root SD_CLK internally!!

    Thanks & regards,

    Achala Ram