Why there's no option to view FPU registers while debugging using EKI-LM4F232 on board jtag.
Using external J-link or simulator the view of FPU Register is available
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Why there's no option to view FPU registers while debugging using EKI-LM4F232 on board jtag.
Using external J-link or simulator the view of FPU Register is available
Hi Ari,
I assume by your kit part number that you are using the IAR debugger.
The TI supplied driver for the on board jtag does support viewing the FPU registers. It is up to IAR as to when they will be enabling this feature.
- Ken
Ken,
Another problem that i noted on the EKI-LM4F232 kit, using external jlink, is that the cpu get lost after the execution of the function below, when the CPU clock is changed to 80MHZ. If let the clock in 50MHZ (SYSCTL_SYSDIV_4) the debugger works okay.
ROM_SysCtlClockSet(SYSCTL_SYSDIV_2_5 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN |SYSCTL_XTAL_16MHZ);
So, If I want to run code at 80 MHZ I need to use ICDI. If I want to view FPU registers I need to use external jlink.
Why all EK-LM4F232 code examples are set up to a maximum frequency of 50MHZ? is there some clock limitation on the board?
Do check the errata - for at least one of these new devices there is difficulty with a fractional divide of the clock. This may mean you must change SYSDIV_2_5 to SYSDIV_3 - yielding 66.66MHz.
And here the errata: (and NOW I note - a complete cure for your issue!) Would you be so kind as to tick my correct answer box?
3.2 ROM_SysCtlClockSet() does not operate correctly with fractional dividers Description: The ROM_SysCtlClockSet() function in StellarisWare does not operate correctly when using fractional dividers (such as SYSDIV_2_5. The function does work correctly with integer dividers. Workaround: If fractional clock dividers are used, load the StellarisWare version of SysCtlClockSet() into Flash memory and use that version of the function.