MCU-PLUS-SDK-AM243X: R5F ECC Testing Issues

Jimmy

Part Number: MCU-PLUS-SDK-AM243X
Other Parts Discussed in Thread: AM2432

Tool/software:

Hello expert.

I am conducting ECC testing on R5F and have passed it:https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1272835/processor-sdk-am64x-how-to-do-ecc-of-atcm-btcm-and-msram-in-r5f0_0-with-mcu_sdk_09_00_00_35/4822544?tisearch=e2e-sitesearch&keymatch=TCM%25252525252520ECC#4822544 I am able to insert the TCM error, but as with the previous issue, the SDL_ECC_getESMErrInfo function returns -1, and the SDL_ECC_clearNIntPending function cannot clear the interrupt. The SDK version I am using is 9.1.0.41

I have three questions:
1. Will the known issue be fixed and when is it expected to be fixed? Because we are eager to obtain security certification.

2. What operation should be used to obtain error information and clear interrupts for non injected TCM and cache ECC errors?

3. If I want to test cache insertion errors, which address range should I insert the error into?

thank you
Best wishes

Jimmy

over 1 year ago

0 Nihar Potturu over 1 year ago

TI__Mastermind 22726 points

Hello Jimmy,

Apologies for the delay.

I assume you are able to inject error and see an error getting detected for TCM memories already. We have an ECC TCM example for AM62x. You can also use that as reference.

software-dl.ti.com/.../EXAMPLES_SDL_R5F_ECC_TCM.html

The R5F memory errors cannot be directly cleared using the standard ESM/ECC APIs. Instead you can try doing this :

Read the R5F_EVENT_BUS_ESM_CLR register and keep writing the read value back until the R5FSS_EVNT_BUS_ESM_SET register becomes 0.

These are R5F pulsar registers that get updated based on the errors detected in the R5F memories by the PMU.

Can you give more details on why do you want to test the R5F memories for ECC?

Regards,

Nihar Potturu.

0 Jimmy over 1 year ago in reply to Nihar Potturu

Prodigy 180 points

Hi Nihar Potturu

Thank you for your reply.

Your response has provided me with new insights and progress.

The purpose of conducting ECC tests is to validate the effectiveness of error responses;

1. Based on your answer, I understand that R5F ECC error detection requires enabling the PMU module; otherwise, errors cannot be detected (insert mode does not require using PMW). Is my understanding correct?

2. I have successfully managed to inject single-bit errors with ATCM, but I am unable to inject double-bit errors (even referring to examples from AM62X doesn't work). It appears that the issue might lie in the configuration of the injection address or flipped bits. Could you provide an example for injecting double-bit errors using ATCM on AM2432?

My input configuration is as follows:

memset(&stInjectErrorConfig, 0U, sizeof(stInjectErrorConfig));
stInjectErrorConfig.pErrMem = (RTS_UI32 *)(0x00000510UL);
stInjectErrorConfig.flipBitMask = 0x08;
stInjectErrorConfig.chkGrp = 0U;
ulSubType = SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_RAM_ID;
result = OS_SDL_InjectEccError(SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR,
                            ulSubType,
                            ulInjectErrorType,
                            &stInjectErrorConfig);

thank you
Best wishes

Jimmy

0 Zekun Bai over 1 year ago in reply to Jimmy

TI__Expert 3955 points

Hi Nihar

Can you help to give customer more updates here? It have been pending for so long.

Regards

Zekun

0 Linjun Meng over 1 year ago in reply to Jimmy

TI__Genius 9981 points

Hi Jimmy,

R5F core has it's own ECC schemes, please check the https://developer.arm.com/documentation/ddi0460/d/CACCEFCJ ECC Schemes section.

Jimmy said:
1. Based on your answer, I understand that R5F ECC error detection requires enabling the PMU module; otherwise, errors cannot be detected (insert mode does not require using PMW). Is my understanding correct?

Regarding the inject double-bit errors, as to it can't recovery by ECC unit, it will trigger system data abort exception. What's the stauts you observed now?

Jimmy said:
2. I have successfully managed to inject single-bit errors with ATCM, but I am unable to inject double-bit errors (even referring to examples from AM62X doesn't work). It appears that the issue might lie in the configuration of the injection address or flipped bits. Could you provide an example for injecting double-bit errors using ATCM on AM2432?

Regards,

Linjun

0 Jimmy over 1 year ago in reply to Linjun Meng

Prodigy 180 points

Hi Linjun

1、我看到了R5内核有自己的ECC机制，我的疑惑是:R5内核产生的ECC异常，能否报告给ESM模块，需不需要使能PMU模块?

2、我使用注入模式，给ATCM注入单比特错误是成功的。注入双比特错误后，没有异常响应，也没有产生数据中止。我怀疑我注入的地址不正确，麻烦帮我看下，注入代码在上方有。

谢谢

Regards

Jimmy

0 Linjun Meng over 1 year ago in reply to Jimmy

TI__Genius 9981 points

Hi Jimmy,

Here are two mode when ECC error happens.

a inject mode,

To R5F core , there are two result accroding to the attribution of it's RAM ID.

If the inject_type is 0,which means the erros will be captured. checked the RAM as below,

SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID (27U)

SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID (28U)

If the inject_type is 1, which means inject only. so no esm event report . Checked the RAM ID, from 0 to 26 ares these type.

b ECC enable mode

When ECC error happened, the event sends to ESM module. The events is below,

#define SDLR_ESM0_ESM_LVL_EVENT_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0 (30U)

#define SDLR_ESM0_ESM_LVL_EVENT_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0 (91U)

Abort inject ATCM DED error, if disabled data abort exception , the R5F ECC registor should indicate DED error happened.

Regards,

Linjun

0 Jimmy over 1 year ago in reply to Linjun Meng

Prodigy 180 points

Hi Linjun

1、关于注入模式，我所注入的RAM类型为

#define SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_RAM_ID (21U)

他的注入类型为1，我理解他是仅能作为注入模式，但是我是可以为该RAM注入1bit错误，并收到ESM的错误响应，但是我注入2bit错误时，收不到错误响应。这似乎与你所解释的类型为1时不会产生ESM事件不一致。麻烦确认，

我能够为VIM RAM注入1bit和2bit的错误，这没有问题。我的问题在于，如何为R5 ECC注入错误以验证错误响应，所以我才会为ATCM注入错误验证。

2、关于ECC enable mode，我理解该模式是正常的R5内核的ECC机制，当R5产生ECC错误时，ESM就会报告此错误，与故障注入无关。按照您的解释，该模式也不需要PMU模块参与(请确认需不需要使能PMU)，我的理解对吗?

谢谢

Jimmy

0 Linjun Meng over 1 year ago in reply to Jimmy

TI__Genius 9981 points

Jimmy said:
这似乎与你所解释的类型为1时不会产生ESM事件不一致。麻烦确认

Pleas help to check when SEC injection happend, which evnent is captured by ESM ?

Jimmy said:
关于ECC enable mode，我理解该模式是正常的R5内核的ECC机制，当R5产生ECC错误时，ESM就会报告此错误，与故障注入无关。按照您的解释，该模式也不需要PMU模块参与(请确认需不需要使能PMU)，我的理解对吗?

Which core is handle the ESM interrupt?

Checked the PMU module for details of which part error occurred when the R5F ECC error occurred, if PMU is enabled. Therefore, Enabling the PMU module is a good addition to a more comprehensive approach to safety diagnostics.

0 Jimmy over 1 year ago in reply to Linjun Meng

Prodigy 180 points

Hi Linjun

I modified the injection error address, and after injecting a double bit error into ATCM, the phenomenon was that data was aborted without generating the ESM0_LVL-IN_40 event; Injecting a single bit is normal and can generate ESM0_LVL-IN-42 events. Is this a normal phenomenon? Can the effectiveness of this diagnostic measure be proven?

stInjectErrorConfig.pErrMem = (RTS_UI32 *)(0x00000510UL);
            stInjectErrorConfig.flipBitMask = 0x05;
            stInjectErrorConfig.chkGrp = 0U;
            ulSubType = SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_RAM_ID;
            result = OS_SDL_InjectEccError(SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR,
                                        ulSubType,
                                        ulInjectErrorType,
                                        &stInjectErrorConfig);

Regards,

Jimmy

0 Linjun Meng over 1 year ago in reply to Jimmy

TI__Genius 9981 points

Hi Jimmy,

When data abort happend , it means the R/W is not allowed. Could you please check the MPU setting by the variable gMpuRegionConfig?

Such as MpuP_AP_S_RW_U_R means is not allow write in user mode.

Another concern is have you actived ATCM ? Actually if enalbe ATCM, and rebase to 0, the address is correct. By system view, Main R5F Core0 address is 0x78000000UL. Thanks.

Linjun

0 Jimmy over 1 year ago in reply to Linjun Meng

Prodigy 180 points

Hi Linjun

I checked my MPU configuration, with the ATCM area configured as MpuP_AP_ALL_RW.

MpuP_RegionConfig gMpuRegionConfig[CONFIG_MPU_NUM_REGIONS + 4] =
{
    {
        .baseAddr = 0x0u, /* back groud */
        .size = MpuP_RegionSize_4G,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 0,
            .isBufferable = 0,
            .isSharable = 1,
            .isExecuteNever = 0,
            .tex = 0,
            .accessPerm = MpuP_AP_S_RW,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x0u, /* vectors */
        .size = MpuP_RegionSize_32K,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 1,
            .isBufferable = 1,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
            .accessPerm = MpuP_AP_S_R,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x50000000u, /* gpmc area */
        .size = MpuP_RegionSize_16M,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 0,
            .isBufferable = 0,
            .isSharable = 1,
            .isExecuteNever = 0,
            .tex = 0,
            .accessPerm = MpuP_AP_ALL_RW,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x70000000u, /* msram background */
        .size = MpuP_RegionSize_2M,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 1,
            .isBufferable = 1,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
            .accessPerm = MpuP_AP_ALL_RW,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x80000000u, /* ddr background */
        .size = MpuP_RegionSize_2G,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 1,
            .isBufferable = 1,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
            .accessPerm = MpuP_AP_ALL_RW,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x70080000u, /* kernel code */
        .size = MpuP_RegionSize_512K,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 1,
            .isBufferable = 1,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
#ifndef BIULDING_RELEASE
            .accessPerm = MpuP_AP_S_RW,
#else
            .accessPerm = MpuP_AP_S_R,
#endif
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x70100000u, /* kernel data */
        .size = MpuP_RegionSize_512K,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 1,
            .isBufferable = 1,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
            .accessPerm = MpuP_AP_S_RW,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x78000000U, /* ATCM */
        .size = MpuP_RegionSize_64K,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 0,
            .isBufferable = 0,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
            .accessPerm = MpuP_AP_ALL_RW,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x70180000u, /* memheap */
        .size = MpuP_RegionSize_512K,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 1,
            .isBufferable = 1,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
            .accessPerm = MpuP_AP_S_RW_U_R,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x80000000u, /* rodata */
        .size = MpuP_RegionSize_8M,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 1,
            .isBufferable = 1,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
            .accessPerm = MpuP_AP_ALL_R,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x80800000u, /* kernel bss */
        .size = MpuP_RegionSize_8M,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 1,
            .isBufferable = 1,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
            .accessPerm = MpuP_AP_S_RW,
            .subregionDisableMask = 0x0u
        },
    },
};

Additionally, prior to testing, I enabled the ECC function for ATCM and invoked the following code:

    SDL_ECC_UTILS_enableECCATCM();
    SDL_ECC_UTILS_enableECCB0TCM();
    SDL_ECC_UTILS_enableECCB1TCM();

    SDL_UTILS_enable_event_bus();

I believe my MPU and enable configurations are correct since 1-bit errors result in successful responses. The potential issue appears to be incorrect injection addresses. Could you please help me verify this?

Regards,

Jimmy

0 Jimmy over 1 year ago in reply to Linjun Meng

Prodigy 180 points

Hi Linjun

I modified the MPU permissions with the following configuration:

MpuP_RegionConfig gMpuRegionConfig[CONFIG_MPU_NUM_REGIONS + 4] =
{
    {
        .baseAddr = 0x0u, /* back groud */
        .size = MpuP_RegionSize_4G,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 0,
            .isBufferable = 0,
            .isSharable = 1,
            .isExecuteNever = 0,
            .tex = 0,
            .accessPerm = MpuP_AP_ALL_RW,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x0u, /* vectors */
        .size = MpuP_RegionSize_32K,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 1,
            .isBufferable = 1,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
            .accessPerm = MpuP_AP_ALL_RW,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x50000000u, /* gpmc area */
        .size = MpuP_RegionSize_16M,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 0,
            .isBufferable = 0,
            .isSharable = 1,
            .isExecuteNever = 0,
            .tex = 0,
            .accessPerm = MpuP_AP_ALL_RW,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x70000000u, /* msram background */
        .size = MpuP_RegionSize_2M,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 1,
            .isBufferable = 1,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
            .accessPerm = MpuP_AP_ALL_RW,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x80000000u, /* ddr background */
        .size = MpuP_RegionSize_2G,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 1,
            .isBufferable = 1,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
            .accessPerm = MpuP_AP_ALL_RW,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x70080000u, /* kernel code */
        .size = MpuP_RegionSize_512K,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 1,
            .isBufferable = 1,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
#ifndef BIULDING_RELEASE
            .accessPerm = MpuP_AP_S_RW,
#else
            .accessPerm = MpuP_AP_S_R,
#endif
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x70100000u, /* kernel data */
        .size = MpuP_RegionSize_512K,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 1,
            .isBufferable = 1,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
            .accessPerm = MpuP_AP_S_RW,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x78000000U, /* ATCM */
        .size = MpuP_RegionSize_64K,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 0,
            .isBufferable = 0,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
            .accessPerm = MpuP_AP_ALL_RW,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x70180000u, /* memheap */
        .size = MpuP_RegionSize_512K,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 1,
            .isBufferable = 1,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
            .accessPerm = MpuP_AP_S_RW_U_R,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x80000000u, /* rodata */
        .size = MpuP_RegionSize_8M,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 1,
            .isBufferable = 1,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
            .accessPerm = MpuP_AP_ALL_R,
            .subregionDisableMask = 0x0u
        },
    },
    {
        .baseAddr = 0x80800000u, /* kernel bss */
        .size = MpuP_RegionSize_8M,
        .attrs = {
            .isEnable = 1,
            .isCacheable = 1,
            .isBufferable = 1,
            .isSharable = 0,
            .isExecuteNever = 0,
            .tex = 1,
            .accessPerm = MpuP_AP_S_RW,
            .subregionDisableMask = 0x0u
        },
    },
};

After modifying the MPU, injecting double-bit errors still poses issues.

I've observed some patterns:
1. When attempting to inject double-bit errors into addresses that cause an execution error with `SDL_InjectEccError`, reading data from these addresses doesn't trigger a data abort.

stInjectErrorConfig.pErrMem = (RTS_UI32 *)(0x00000510UL);
            stInjectErrorConfig.flipBitMask = 0x02;
            stInjectErrorConfig.chkGrp = 0U;
            ulSubType = SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_RAM_ID;
            result = OS_SDL_InjectEccError(SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR,
                                        ulSubType,
                                        ulInjectErrorType,
                                        &stInjectErrorConfig);

2. Injecting double-bit errors into other addresses leads to `SDL_InjectEccError` functioning correctly, but upon data read triggering, it does enter a data abort.

stInjectErrorConfig.pErrMem = (RTS_UI32 *)(0x00000510UL);
            stInjectErrorConfig.flipBitMask = 0x05;
            stInjectErrorConfig.chkGrp = 0U;
            ulSubType = SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_RAM_ID;
            result = OS_SDL_InjectEccError(SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR,
                                        ulSubType,
                                        ulInjectErrorType,
                                        &stInjectErrorConfig);

Given that single-bit errors are handled without issue, I suspect the problem lies with my selection of address for injection. Could you please provide an example related to injecting double-bit ECC errors into ATCM?

Regards,

Jimmy

0 Linjun Meng over 1 year ago in reply to Jimmy

TI__Genius 9981 points

Hi Jimmy,

Here is a debug script, please run it after 2-bit ATCM bank0 injection data abort. Feedback the register dump here.

/cfs-file/__key/communityserver-discussions-components-files/908/5773.AM2432_5F00_esm_5F00_ecc_5F00_debug.gel

0 Jimmy over 1 year ago in reply to Linjun Meng

Prodigy 180 points

Hi Linjun

After I run this script, the output is as follows

MAIN_Cortex_R5_0_0: GEL Output: 
MAIN_Cortex_R5_0_0: GEL Output: MAIN ESM RAW DATA:
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420400 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420420 = 0x00000040
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420440 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420460 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420480 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x004204A0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: 
MAIN_Cortex_R5_0_0: GEL Output: clean MAIN ESM RAW DATA:
MAIN_Cortex_R5_0_0: GEL Output: 
MAIN_Cortex_R5_0_0: GEL Output: after clean MAIN ESM RAW DATA:
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420400 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420420 = 0x00000040
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420440 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420460 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420480 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x004204A0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: 
MAIN_Cortex_R5_0_0: GEL Output: MAIN ESM RAW DATA:
register_dump_ESM() cannot be evaluated.
Could not read 0x00420400: execution state prevented access
	 at regVal=*((unsigned int*) regAddr) [5773.AM2432_esm_ecc_debug.gel:60]
	 at register_dump_ESM()MAIN_Cortex_R5_0_0: GEL Output: 
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01000C : 0x0000001D
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000001
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000002
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000003
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000004
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000005
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000006
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000007
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000008
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000009
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x0000000A
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x0000000B
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x0000000C
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x0000000D
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x0000000E
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x0000000F
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000010
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000011
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000012
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000013
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000014
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000015
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000016
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000017
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000018
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x00000019
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x0000001A
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x0000001B
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: ram_id: 0x0000001C
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010010 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010014 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010018 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C01001C : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010020 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x3C010024 : 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: 
MAIN_Cortex_R5_0_0: GEL Output: MAIN ESM RAW DATA:
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420400 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420420 = 0x00000140
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420440 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420460 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420480 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x004204A0 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: 
MAIN_Cortex_R5_0_0: GEL Output: clean MAIN ESM RAW DATA:
MAIN_Cortex_R5_0_0: GEL Output: 
MAIN_Cortex_R5_0_0: GEL Output: after clean MAIN ESM RAW DATA:
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420400 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420420 = 0x00000140
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420440 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420460 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x00420480 = 0x00000000
MAIN_Cortex_R5_0_0: GEL Output: Reg_0x004204A0 = 0x00000000

Regards,

Jimmy

+1 Linjun Meng over 1 year ago in reply to Jimmy

TI__Genius 9981 points

Hi Jimmy,

According to the log, ESM bit40 is set by 2-bit TCM injection.

To your application, the issue is how to handle DED error in data abort mode. Please submit another ticket if needed.

Thanks.

Linjun

0 Jimmy over 1 year ago in reply to Linjun Meng

Prodigy 180 points

Hi Linjun

Sure, I understand the meaning. I will proceed with the next analysis.

Thank you for your help.

Regards,

Jimmy

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