TMS470MF06607: TMS470 DOZE

Hi Daniel,

  Unfortunately, the zip file is no longer available. Please follow the instructions shown in the TRM to enter doze mode.

2.2.2.1 Doze Mode Doze mode is defined as follows:

• The primary oscillator is enabled.

• The RTI clock can be either enabled or disabled (depends on user setting).

• The low-frequency clock (either the 32 KHz oscillator or the low-frequency low power oscillator (LF LPO)) source can be either enabled or disabled by the user.

• The voltage regulator (VREG), if present, must be put in LPM1 state.

Since the primary oscillator is still enabled in doze mode, the device will wake up much faster and start executing instructions in the fewest amount of cycles of any low power mode. Doze mode will also have the highest current of any of the low power modes. In order to enter doze mode, the following steps are required by the user software.

1. Software writes to the flash control registers to put all flash pumps to sleep. Flash pumps will not be disabled until all flash banks have been put to sleep.

Note: Which registers need to be written depends on the specific TMS470M Series device being used. Please consult device-specific datasheet to determine the proper TMS470M Series flash module specification.

2. Software writes to voltage regulator control register (VRCTL) to put the Voltage regulator in LPM1. The voltage regulator will not be put into LPM1 until all the clock domains assert their clock stop acknowledge signals.

Note: This only applies to devices with an internal voltage regulator. Consult the device specific TMS470M Series device datasheet.

3. Software writes to the clock source disable register (CSDIS) to disable the PLL clock source. Other sources may also be powered off, but the high-frequency oscillator must still be enabled to be considered to be in doze Mode.

Note: The source will not actually be disabled until the clock domains that use them are disabled (see the clock Definition section of the TMS470M Series Architecture specification Section 1.5.2).

4. Software writes to the clock domain disable register (CDDIS) to disable the GCLK (CPU clock), HCLK (system clock), VCLKP (peripheral VBUS clock), VCLK2 (peripheral VBUS clock2), VCLKA1 (asynchronous peripheral VBUS clock1), and VCLKA2 (asynchronous peripheral VBUS clock2). All these domains must be disabled in order to be considered in doze mode. A particular domain is not actually disabled until all modules using that domain assert their clockstop acknowledge signal (see the clock Definition section of the TMS470M Series Architecture specification Section 1.5.2). The RTI1CLK and RTI2CLK domains may or may not be disabled. Doze mode is normally used in conjunction with an RTI in order to wake up the device periodically from within.

Note: Some exceptions on which domains must be disabled in doze mode may exist, which are defined in the device-specific TMS470M Series datasheet.

5. Software “idles” the ARM core, then stops the core clock. The device will return to normal operation after a wakeup interrupt from doze mode from one of the sources mentioned in Section 1.5.4. Which clock source is used for which clock domain after wakeup is user programmable. Normally it would make sense to use the high-frequency oscillator for the GCLK, HCLK, and VCLK domains on wakeup to minimize the time to start executing instructions after wakeup from doze mode. If the PLL is used after returning to normal operation, a longer delay may occur since the PLL needs to relock. The PLL can be re-locked after waking up from doze mode in parallel with performing other operations. Once the PLL locks, the software can select the PLL as the source for the clock domains. If an interrupt is required, it can be programmed in the M3VIM for doze mode.