DCAN SWR Bit Reset Clock Cycle time once it is set

Hello, In DCAN DCANCTL Register for SWR bit I see the following definition: This bit will automatically get cleared after execution of SW reset after one VBUSP clock cycle. Can you please help me how many clock cycles [VCLK] it takes to reset using SWR? I am assuming only one VCLK cycle and SWR bit reverts back to ZERO. Is that always correct under all conditions? Thank you. Pashan