Other Parts Discussed in Thread: DP83869, SYSCONFIG
Tool/software:
Hi Team,
My customer is trying to perform an Ethernet compliance test and are configuring the registers as shown in the code below, but they cannot see any Ethernet signal waveform or MDIO signal waveform. Is the code below correct?
#include "ti_board_open_close.h"
#include <drivers/mdio.h>
#include <board/ethphy.h>
#include <board/ethphy/ethphy_dp83869.h>
// When they configure ETHPHY via SysConfig, CSL_ICSS_M_PR1_MDIO_V1P7_MDIO_REGS_BASE(0x00032400U) becomes undefined and causes a compiler error so they hard-coded the value
#define KC_TASK_LAN_MDIO_BASE_ADDRESS ( CSL_ICSSM0_INTERNAL_U_BASE + (0x00032400U) )
// ETHPHY address is 0x00
#define KC_TASK_LAN_DP83869_PHY_ADDRESS (0U)
static int32_t ethphy_reg_read(uint32_t regNum, uint16_t* regVal);
static int32_t ethphy_reg_write(uint32_t regNum, uint16_t regVal);
static void enable_compliance_test(void);
static int32_t ethphy_reg_read(uint32_t regNum, uint16_t* regVal)
{
int32_t status = SystemP_FAILURE;
// MDIO_phyRegRead() was listed in "APIs for MDIO" within the SDK
status = MDIO_phyRegRead(KC_TASK_LAN_MDIO_BASE_ADDRESS, NULL, KC_TASK_LAN_DP83869_PHY_ADDRESS, regNum, regVal);
return status;
}
static int32_t ethphy_reg_write(uint32_t regNum, uint16_t regVal)
{
int32_t status = SystemP_FAILURE;
// MDIO_phyRegWrite() was listed in "APIs for MDIO" within the SDK
status = MDIO_phyRegWrite(KC_TASK_LAN_MDIO_BASE_ADDRESS, NULL, KC_TASK_LAN_DP83869_PHY_ADDRESS, regNum, regVal);
return status;
}
// Task calls the enable_compliance_test function and performs a compliance test
static void enable_compliance_test(void)
{
int32_t status;
uint32_t regNum;
uint16_t regVal;
static uint16_t regVal_1DF;
static uint16_t regVal_1F_1;
static uint16_t regVal_00;
static uint16_t regVal_10;
static uint16_t regVal_1F_2;
static uint16_t regVal_02;
// MDIO_initClock() was listed in "APIs for MDIO" within the SDK
status = MDIO_initClock(KC_TASK_LAN_MDIO_BASE_ADDRESS);
DebugP_assert(status == SystemP_SUCCESS);
/*********************************************/
/***** Compliance Test 100 Base Standard *****/
/*********************************************/
// Reset PHY
regNum = 0x1F;
regVal = 0x8000;
status = ethphy_reg_write(regNum, regVal);
DebugP_assert(status == SystemP_SUCCESS);
// Calls ethphy_reg_read() which reads the register value configured in ethphy_reg_write above and return 0
status = ethphy_reg_read(regNum, ®Val_1F_1);
DebugP_assert(status == SystemP_SUCCESS);
// Programs DUT to 100Base-TX Mode
regNum = 0x00;
regVal = 0x2100;
status = ethphy_reg_write(regNum, regVal);
DebugP_assert(status == SystemP_SUCCESS);
status = ethphy_reg_read(regNum, ®Val_00);
DebugP_assert(status == SystemP_SUCCESS);
// Programs DUT to Forced MDI or MDIX mode (0x5028)
regNum = 0x10;
regVal = 0x5028;
status = ethphy_reg_write(regNum, regVal);
DebugP_assert(status == SystemP_SUCCESS);
status = ethphy_reg_read(regNum, ®Val_10);
DebugP_assert(status == SystemP_SUCCESS);
// Restart PHY
regNum = 0x1F;
regVal = 0x4000;
status = ethphy_reg_write(regNum, regVal);
DebugP_assert(status == SystemP_SUCCESS);
status = ethphy_reg_read(regNum, ®Val_1F_2);
DebugP_assert(status == SystemP_SUCCESS);
}
Best regards,
Mari Tsunoda