Tool/software:
I think I understand the physical layout and the logical structure of the memory. However, I want to make sure my assumptions are correct.
The datasheet of the Tiva TMC1294 says that it has four 32-bit interleaved SRAM banks (256 kB) (pg. 57 of the June 18, 2014 datasheet). Additionally, I am making the assumption that the SRAM banks distribute the words in a round robin approach (assuming the lecture from ECE 752 lecture from UW-Madison).
I am making the following assumptions for the banks:
- Bank0 stores bit0 to bit7 of all addresses – addresses increase by 4, therefore the least significant byte of all addresses has an address that belongs to bank0.
- Each bit position requires 2000 rows x32 bits each -> that is a total of 64,000 addresses (256 kB)
- Bank1 stores bit8 to bit15 of all addresses
- Bank2 stores bit16 to bit23 of all addresses
- Bank3 stores bit24 to bit31 of all addresses
- Furthermore, if address 0x2000 0000 stores the value 0xAAAAAAAA, then (this is round robin!):
- The least significant byte (xAA) is stored in 0x2000 0000
- The next byte (xAA) is stored in 0x2000 0001
- While, the most significant byte (xAA) is stored in 0x2000 0003
- Then the least significant byte of address 0x2000 0004 is stored in 0x2000 0004
- Bit0 of all addresses are stored in 2000 arrays with 32 bit columns- This corresponds to 64,000 addresses for a 256 kB SRAM memory.
- Each bit in columns 1 to 32 of all rows, store the same bit position of logically ascending addresses.
