MSPM0G3507: Timer Output Actions priorities?

Hi Jonas, 

In the G-series TRM the table you are looking for is table 25-24 the IIDX STAT lists the interrupt priority with 0x01 being the highest interrupt priority. 

Hello,

You are mentioning tables 25-24 and 25-25, which are part of sending interrupts to the CPU and Generic Events.

I cannot find anywhere in the Reference Manual or the Datasheet that mentions that the CCACT signals have the same priorities as they have in the Event module.

Further, the CCACT module has signals that are not mentioned in the IIDX register (eg: SWFRCACT).

How can I know the priority of signals that are not mentioned in Tables 25-24 and 25-25, but are present in CCACT.

Thanks,

Jonas

Hello Jonas,

Are you concerned here about the priority of the actual output of the capture compare pin or are you concerned about the capture compare pin generating an internal event? (if then, the internal event priorities would be governed by table 24-24 and 25-25). Also, the CCACT specifies what happens for a specific capture compare pin, so if for example CC0 and CC1 have the same capture compare value they will just happen at the same time on different pins. Also, the screenshot below from the TRM shows the Tima output block diagram. and usually, the Software Forced output generation and fault output generation will take priority over the capture compare outputs.

Hello,

I am not concerned about the general Event system (which, as you point out, is governed by Tables 25-24 and 25-25).

I am only interested in the system that generates output from a Timer peripheral. In the documentation for the CCACT register (Figure 25-91 and Table 25-78), each field has a 0h value that is "This event is disabled and a lower priority event is selected", but what actually is the priorities of the signals mentioned in the CCACT register.

Also, I understand that "Software Force Output" and "Fault Output" have higher priority than everything else. Those are not what I'm asking about.

Thanks,

Jonas

Hello,

Ok I understand better what the concern is, unfortunately, we do not have a table in the TRM that lists out the priority of all the signals in the CCACT Register, that's a gap in our documentation and I will file a ticket to get that updated, but looking at figure 25-27 in my previous response, SWFRCACT and the fault output generation bits such as FENACT and FEXACT will be higher priority than all the other signals in that register. Until we are able to publish the updates, I'd recommend using figure 25-26 to interpret the signals' priorities.