TMS570LC4357: Description of I2CPDR correct?

Hi Max,

To do this testing i configured the pins as below:

Mainly i want to disable the internal pull-up or pull-down, because the main difference between open drain enable and open drain disable is that when we disable the open drain then whatever the value (Logic-0/Logic-1) written on the DOUT register will get forwarded to the output GIO pin and also refects the same on DIN register.

Whereas if you enable the open drain then logic-0 will properly transmit to the output GIO pin and also reflects on DIN register but if you try to write Logic-1 then the pin will be in high state, and an external or internal pull will give the result now.

After doing above configurations, here are my test results:

1. Disabling Open drain and writing Logic-0:

So as i disabled open drain and written the logic-0 i got the same value on DIN

And also, my GIO output pin values are also logic-0 only.

2. Disabling Open drain and writing Logic-1:

Similarly, when i disabled open drain and write logic-1 i got the same value in DIN

And my GIO output value also reflecting the same:

3. Enabling Open drain and writing Logic-0:

As we discussed earlier, for open drain enable case also logic-0 will get properly transmitted to the output GIO pin and DIN register.

So, the same behavior was reflected:

4. Enabling Open drain and writing Logic-1:

This is the important condition, and this is where the output should be in high impedance state. As you can see even though i write logic-1 on the DOUT register, it is showing logic-0 in DIN register. This is because of high impedance state.

And you can also see logic analyzer output also, it is also showing no voltage on GIO pin:

So, as you can see the high impedance state or open drain condition occurs when the PDR value becomes zero right. That means datasheet description was correct:

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Thanks & regards,
Jagadish.

Hi Max,

I also found a mistake with HALCoGen GUI and generated code:

1. As you can see i didn't enable the open-drain checkboxes in HALCoGen, that means open drain is in disabled state according to the GUI right?

However, if you verify the generated code, it is writing logic-0 to the PDR register for both SDA and SCL, that means it is enabling the open drain as per the tastings in my last comment.

2. Similarly, now i am enabling the open drain according to the HALCoGen GUI:

Now it is writing logic-1 to the PDR register, that means open drain disable according to datasheet and our testing results.

I am also suspecting that, may be in silicon hardware level they implemented in reverse, because if you verify the other peripherals PDR registers like SCI and MibSPI etc.

Usually writing logic-1 will enable the open-drain and writing logic-0 will disable the open drain, however for this i2c peripheral it is working in reverse. So, there might be some issue in hardware that is the reason maybe they reversed the description.

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Thanks & regards,
Jagadish.

Hi Max,

And one more very important thing is that the above HALCoGen issue or silicon hardware issue doesn't affect the behavior of the i2c.

Because if the SDA or SCL pins are configured as i2c functionality then irrespective of the value of PDR register the pins will always act as open drain. Ony when these pins were configured as GIO then only this issue comes into the picture.

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Thanks & regards,
Jagadish.