FreeRTOS support

Hello Durga,

I am looking at your queries and you may expect reply in one or two days ,

Regards,

Anil.

Hello Durga,

Durga Choudhury said:

Is this a TI-proprietary port that is not pushed to the mainstream FreeRTOS kernel?

Yes, your understanding is correct.

We did not plan to push to the main stream, and I am working with an internal Team and seeing how we can push these changes to the mainstream.

Durga Choudhury said:

And does it support SMP across the multiple cores? Is there any documentation on how to use SMP in chips with more than 1 core?

Currently, SMP is not supported for R5F cores in AM243X devices.

Regards,

Anil.

Thanks for the clarification, but I have follow up questions:

Since SMP is not supported, AMP must be the only way to leverage the cores. So that means handling a timer interrupt on each of the cores independently.

Is there any limitation on this? A few example of such possible limitation maybe:

1. Can the different cores be clocked from different timers, e.g. one from an internal and one from an external clock source?

2. How will cache coherency be impacted by AMP?

Is there any documentation on how to program the individual cores? Usually such documentation is not provided because SMP handles this transparently, but it seems that is not the case here.

Hello Durga,

Durga Choudhury said:

Since SMP is not supported, AMP must be the only way to leverage the cores. So that means handling a timer interrupt on each of the cores independently.

Yes, your understanding is correct.

In Multicore processors, you can treat  single core as a unique core and don't mix peripheral usage with other cores.

For example, you need a Timer in one core. So, Timer clock and Timer parameters initiations  and Timer interrupt processing should be done in one core only.

If you need another Timer in different cores, use a different timers and don't configure the already used timer.

This procedure is the same for all peripherals.

Currently, in our MCU+SDK, there are different examples, and  you can look at them.

Mostly, examples are available on R5F0_0 cores. If you need same example on different cores, then the same examples need to be integrated in on the different  core. Other than this, you don't need to do anything when you work on different cores.

Durga Choudhury said:

2. How will cache coherency be impacted by AMP?

In my view, the cache coherence is followed by the internal SOC protocol.

So, when you try to access the memory location and, core will read the updated data only.

Please let me know if you need any other details.

Regards,

Anil.

Regards,

Anil.