Tool/software:
Trying to do an interrupt driven half-duplex IrDA link using IRDA mode of the UART0 module of the MSPM0G1507 processor.
We are having issues with disabling the RX and when it is reenable we catch a couple of the last couple of characters shifted out.
We are using a baud rate of 115200.
We are using the 40 MHz ULPCK source for the UART0 module.
We are using the CLKDIV2 register which we have set to 1, as per the manual.
The sequence we are aiming for is:
1. When a transmit is started, we use the DMA to send out all the data. Before the transfer is started, the RX is disabled using the
These steps as outline in the MSPM0 manual:
2. Then once the DMA is finished (We wait for the DMA_DONE_TX interrupt) We also wait for UART is Busy is the STAT register to be cleared and then we reenable the RX on the UART0 peripheral.
3. We have tried waiting for the EOT interrupt, however this interrupt does not seem to trigger without disabling the UART module (Is there something we are missing?) Per chance is there an Errata sheet for the IrDA?
4. We have observed that the RX does function for us, we were able to receive commands to our software.
5. However the TX is non-functional.
6. Our IRDA Settings are as follows:
- IRRXPL register is set to 1h
- IRTXPL register is set to 9h for setting the pulse length
- IRTXCLK register is set to 1 (using the baud rate clock)
- IR/EN enabled.
The IRDA part we are using is at : https://www.vishay.com/docs/82633/tfbs4711.pdf
In our IO_MUX we are not inverting the Uart_RX line as per the vishay part. It inverts and mirrors the TX data. Our understanding is that by setting the IRRXPL register to 1h this will be done for us. And from what we can see, it does appear to so. (Please correct me if I am wrong).
We think we were getting a spurious read back on the RX line from the TX on the IrDA part.
Our FIFO levels in the UART are configured as UART_RXIFLSEL is 7h >=1 1 entry available. This is triggering the UART RX interrupt which reads in the bytes from the UART_RX into our application memory space.
The TX fifo is 7h, TX FIFO >= 1 entry free which is used to trigger our DMA to shift the data out into the UART_TX register.
We found the example projects for this processor, using IrDA, but they will not work for our half - duplex operation.
