AM2632: How to flush the fifo of UART and MCSPI?

xiaoxue zhang

Part Number: AM2632

Tool/software:

There is a method to flush the fifo of UART and MCSPI: read all of the data until the fifo is empty.

Is there another way to flush or reset the fifo of UART and MCSPI? Is there a register which can implement the function?

over 1 year ago

0 Shaunak Deshpande over 1 year ago

TI__Genius 16452 points

Hi Xiaoxue Zhang,

UART:

If you are using UART LLD, you can call the API: UART_lld_flushTxFifo()

From registers point of view:

The UART_FCR register has the 2nd Bit for clearing the TX_FIFO and the 1st bit for clearing the RX_FIFO

McSPI:

I'm not the expert on McSPI, I will wait for the appropriate expert to answer the mechanisms to reset/clear the McSPI FIFO

Regards,
Shaunak

0 QJ Wang over 1 year ago in reply to Shaunak Deshpande

TI__Guru**** 197036 points

Hi Xiaoxue,

You don't have to clear the FIFO or data register before next transmission. You can use the interrupt status (RX_FULL and TX_EMPTY in IRQSTATUS register) and TX or RX count. The end of transfer depends on the transfer mode.

Please refer to 13.1.3.5 MCSPI Programming Guide of device TRM (Page 1036)

AM263x Sitara Microcontroller Technical Reference Manual (Rev. F) (ti.com)

Arm-based microcontrollers

Arm-based microcontrollers forum

AM2632: How to flush the fifo of UART and MCSPI?