AM2431: Regarding TRM "8.1.4.3.2 ECC Cache Flush", the content of ECC Cache Flush for SDRAM is unclear.

Hello ,

I am looking at your queries and you may expect reply in one or two days .

Regards,

Anil.

Hello,

AM243X devices have cache memory.

So, when the CPU wants to read data from MSRAM/DDR they read from the cache to improve the read/write performance.

Similarly, DDR inline ECC bits are stored in the ECC cache. So, will read / write ECC bits instead of DDR reads from  ECC Cache to improve performance.

Now, you can check the points below .

For low power modes, the bridge supports flushing the cache when DDRSS stop clock request is asserted. When a clock stop is requested, the bridge will start issuing writes to the DRAM until all dirty cache locations are written to the DRAM. Once the writes are complete, the bridge asserts an acknowledge signal to let the subsystem know that the operation is complete. The subsystem uses this acknowledge signal along with acknowledgments from other submodules to generate the final DDRSS stop clock acknowledge to the system.

Regards,

Anil.