AM2431: There is something unclear about TRM "9.2.1.1.1 GICSS Features"

Hello 

?? ?? said:

I would like to know more about "affinity-based interrupt routing."

Thanks for your query.

The GIC-500 interrupt controller provides registers for managing interrupt sources, interrupt behavior, and interrupt routing to one or more cores. 

It supports Programmable interrupt routing that is based on affinity. It has 1-32 Number of affinity-level 1 clusters.

The ARM architecture defines a register in a core that identifies the logical address of the core in the system. This register, which is known as the Multiprocessor Affinity Register (MPIDR), has a hierarchical format. Each level of the hierarchy is known as an affinity level, with the highest affinity levels specified first:

For more information on the above features, please refer to ARM GIC-500 interrupt controller TRM.

Please refer About-GIC-500-controller. 

Regards,

Tushar