Other Parts Discussed in Thread: ADS1292R, ADS1292
Tool/software:
Hello Fellows,
I have a. big problem with a red board MSP432P401R, I am trying configure it to interface it with analog front end , this deveice work with SPI comunication.
The requirements of the slave device is... the microcontroller should act like a master, the clock CPOL = 0 and CPHA = 1. My clock system is configured to 24MHz (MCLK) and SPI clock source 12MHz (SMCLK).
so the SPI clock is 500KHz(SPI Clock=Source Clock/BRW =>BRW= Source Clock/SPI clocK). But unfortunately something wrong is happening.
The mosi line sends correctlly the data, but the miso line only brings me 0xFF, so this gives me a idea that's its a bad implementention on the code, i hope someone can help me to solve this. I share the SPI integration code and screenshoot of the comunication.
void initialize_spi(void) {
/*INITIALIZE PORT REGISTERS*/
// 4. Configure SPI pins: P1.5 (SCLK), P1.6 (MOSI), P1.7 (MISO)
P1->SEL0 |= (BIT5 | BIT6 | BIT7); // Select primary module function for P1.5, P1.6, and P1.7
P1->SEL1 &= ~(BIT5 | BIT6 | BIT7); // Clear P1SEL1 for those bits to use SPI functionality
/* set CLK and MOSI as outputs */
P1->DIR |= (BIT5 | BIT6);
P1->OUT |= (BIT5 | BIT6);
/* set MISO as input */
P1->DIR &= ~(BIT7);
EUSCI_B0->CTLW1 |= EUSCI_B_CTLW0_SWRST;
// 2. Configure eUSCI_B0 in SPI master mode, 3-pin SPI (no STE pin), synchronous mode
EUSCI_B0->CTLW0 = EUSCI_B_CTLW0_SWRST // Keep eUSCI in reset
| EUSCI_B_CTLW0_MST // Master mode
| EUSCI_B_CTLW0_MSB // MSB first
| EUSCI_B_CTLW0_SYNC // Synchronous mode
| EUSCI_B_CTLW0_SSEL__SMCLK // Use SMCLK (12 MHz)
| EUSCI_B_CTLW0_CKPL
| EUSCI_B_CTLW0_CKPH; // Clock Phase: Data changed on the first clock edge, captured on the next (CPHA = 0)
// 3. Set SPI clock divider for 500 KHz baud rate (12 MHz SMCLK / 24 = 1/2 MHz)
EUSCI_B0->BRW = 24; // Clock prescaler
// 5. Take eUSCI_B0 out of reset mode
EUSCI_B0->CTLW0 &= ~EUSCI_B_CTLW0_SWRST;
EUSCI_B0->CTLW1 &= ~EUSCI_B_CTLW0_SWRST;
}
Thanks in advance.
