MCU-PLUS-SDK-AM243X: DDR4 Test Fail

Kevin, instead of the spreadsheet, can you send the .syscfg from the DDR register config tool?  Also, can you try performing the memory test with ECC disabled.  It would be better to establish correct functionality with ECC disabled.  Once that is verified, you can enable ECC.  This will help determine if the problem is with the memory transactions or with ECC itself.

Regards,

James

Hi James,

Thanks for your suggestion!

Please see the .sysconfig files customer used below, the first two are generated from DDR register config tool, and the last one is generated from CCS.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/DDR4_2D00_1600_5F00_800MHz_5F00_03_5F00_untitled.syscfg

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/DDR4_2D00_1600_5F00_800MHz_5F00_03_5F00_settings_5F00_info.syscfg

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/CCS_5F00_example.syscfg

According to your suggestion, customer disabled the ECC for the testing, but the problem is quite similar, please see the log below for disabling the ECC.

[MAIN_Cortex_R5_0_0] 10
Pattern 0x00000001, Writing memory size 0x00004E20
DDR addr 0x8000089C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR addr 0x800047FC failed. Write value: 0x00000001, read value: 0x00FF0001
Flip Pattern: pattern 0xFFFFFFFE, Writing memory size 0x00004E20
DDR addr 0x800019BC failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
DDR addr 0x800027BC failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
DDR addr 0x8000D5FC failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
Pattern 0x00000003, Writing memory size 0x00004E20
DDR addr 0x8000021C failed. Write value: 0x00000003, read value: 0x00FF0003
DDR addr 0x8000221C failed. Write value: 0x00000003, read value: 0x00FF0003
Flip Pattern: pattern 0xFFFFFFFC, Writing memory size 0x00004E20
DDR addr 0x800012FC failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
DDR addr 0x80002B1C failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
Pattern 0x00000007, Writing memory size 0x00004E20
DDR addr 0x8000399C failed. Write value: 0x00000007, read value: 0x00FF0007
DDR addr 0x8000539C failed. Write value: 0x00000007, read value: 0x00FF0007
DDR addr 0x8000715C failed. Write value: 0x00000007, read value: 0x00FF0007
DDR addr 0x8000877C failed. Write value: 0x00000007, read value: 0x00FF0007
Flip Pattern: pattern 0xFFFFFFF8, Writing memory size 0x00004E20
DDR addr 0x80002D1C failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8
Pattern 0x0000000F, Writing memory size 0x00004E20
DDR addr 0x8000A17C failed. Write value: 0x0000000F, read value: 0x00FF000F
DDR addr 0x8000A71C failed. Write value: 0x0000000F, read value: 0x00FF000F
DDR addr 0x8000A95C failed. Write value: 0x0000000F, read value: 0x00FF000F
Flip Pattern: pattern 0xFFFFFFF0, Writing memory size 0x00004E20
Pattern 0x00000005, Writing memory size 0x00004E20
Flip Pattern: pattern 0xFFFFFFFA, Writing memory size 0x00004E20
DDR addr 0x8000073C failed. Write value: 0xFFFFFFFA, read value: 0xFF00FFFA
DDR addr 0x8000A87C failed. Write value: 0xFFFFFFFA, read value: 0xFF00FFFA
Pattern 0x00000015, Writing memory size 0x00004E20
DDR addr 0x8000209C failed. Write value: 0x00000015, read value: 0x00FF0015
DDR addr 0x800085FC failed. Write value: 0x00000015, read value: 0x00FF0015
Flip Pattern: pattern 0xFFFFFFEA, Writing memory size 0x00004E20
DDR addr 0x80002F7C failed. Write value: 0xFFFFFFEA, read value: 0xFF00FFEA
Pattern 0x00000055, Writing memory size 0x00004E20
DDR addr 0x80000A5C failed. Write value: 0x00000055, read value: 0x00FF0055
DDR addr 0x8000357C failed. Write value: 0x00000055, read value: 0x00FF0055
DDR addr 0x8000837C failed. Write value: 0x00000055, read value: 0x00FF0055
DDR addr 0x8001213C failed. Write value: 0x00000055, read value: 0x00FF0055
Flip Pattern: pattern 0xFFFFFFAA, Writing memory size 0x00004E20
DDR addr 0x800102DC failed. Write value: 0xFFFFFFAA, read value: 0xFF00FFAA
Pattern 0x0000AAAA, Writing memory size 0x00004E20
DDR addr 0x8000005C failed. Write value: 0x0000AAAA, read value: 0x00FFAAAA
DDR addr 0x80001D3C failed. Write value: 0x0000AAAA, read value: 0x00FFAAAA
DDR addr 0x8000365C failed. Write value: 0x0000AAAA, read value: 0x00FFAAAA
DDR addr 0x800049BC failed. Write value: 0x0000AAAA, read value: 0x00FFAAAA
DDR addr 0x8000A99C failed. Write value: 0x0000AAAA, read value: 0x00FFAAAA
DDR addr 0x8001133C failed. Write value: 0x0000AAAA, read value: 0x00FFAAAA
Flip Pattern: pattern 0xFFFF5555, Writing memory size 0x00004E20
DDR read & write completed
ERROR: ddr_ecc_test_main:403: Some tests have failed
5
Pattern 0x00000001, Writing memory size 0x00002710
DDR addr 0x8000083C failed. Write value: 0x00000001, read value: 0x00FF0001
Flip Pattern: pattern 0xFFFFFFFE, Writing memory size 0x00002710
Pattern 0x00000003, Writing memory size 0x00002710
DDR addr 0x800021FC failed. Write value: 0x00000003, read value: 0x00FF0003
DDR addr 0x80006D5C failed. Write value: 0x00000003, read value: 0x00FF0003
DDR addr 0x8000793C failed. Write value: 0x00000003, read value: 0x00FF0003
DDR addr 0x800091FC failed. Write value: 0x00000003, read value: 0x00FF0003
Flip Pattern: pattern 0xFFFFFFFC, Writing memory size 0x00002710
Pattern 0x00000007, Writing memory size 0x00002710
DDR addr 0x80003B5C failed. Write value: 0x00000007, read value: 0x00FF0007
Flip Pattern: pattern 0xFFFFFFF8, Writing memory size 0x00002710
Pattern 0x0000000F, Writing memory size 0x00002710
Flip Pattern: pattern 0xFFFFFFF0, Writing memory size 0x00002710
DDR addr 0x800025BC failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
DDR addr 0x8000749C failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
Pattern 0x00000005, Writing memory size 0x00002710
DDR addr 0x800014DC failed. Write value: 0x00000005, read value: 0x00FF0005
Flip Pattern: pattern 0xFFFFFFFA, Writing memory size 0x00002710
Pattern 0x00000015, Writing memory size 0x00002710
DDR addr 0x800076BC failed. Write value: 0x00000015, read value: 0x00190015
Flip Pattern: pattern 0xFFFFFFEA, Writing memory size 0x00002710
Pattern 0x00000055, Writing memory size 0x00002710
Flip Pattern: pattern 0xFFFFFFAA, Writing memory size 0x00002710
Pattern 0x0000AAAA, Writing memory size 0x00002710
DDR addr 0x8000321C failed. Write value: 0x0000AAAA, read value: 0x00FFAAAA
DDR addr 0x8000729C failed. Write value: 0x0000AAAA, read value: 0x00FFAAAA
Flip Pattern: pattern 0xFFFF5555, Writing memory size 0x00002710
DDR addr 0x8000529C failed. Write value: 0xFFFF5555, read value: 0xFF005555
DDR read & write completed
ERROR: ddr_ecc_test_main:403: Some tests have failed
4
Pattern 0x00000001, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFFE, Writing memory size 0x00001F40
DDR addr 0x80003B9C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
Pattern 0x00000003, Writing memory size 0x00001F40
DDR addr 0x800061FC failed. Write value: 0x00000003, read value: 0x00FF0003
Flip Pattern: pattern 0xFFFFFFFC, Writing memory size 0x00001F40
Pattern 0x00000007, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFF8, Writing memory size 0x00001F40
Pattern 0x0000000F, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFF0, Writing memory size 0x00001F40
Pattern 0x00000005, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFFA, Writing memory size 0x00001F40
Pattern 0x00000015, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFEA, Writing memory size 0x00001F40
Pattern 0x00000055, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFAA, Writing memory size 0x00001F40
Pattern 0x0000AAAA, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFF5555, Writing memory size 0x00001F40
DDR read & write completed
ERROR: ddr_ecc_test_main:403: Some tests have failed
4
Pattern 0x00000001, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFFE, Writing memory size 0x00001F40
Pattern 0x00000003, Writing memory size 0x00001F40
DDR addr 0x80000A1C failed. Write value: 0x00000003, read value: 0x00DB0003
Flip Pattern: pattern 0xFFFFFFFC, Writing memory size 0x00001F40
Pattern 0x00000007, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFF8, Writing memory size 0x00001F40
Pattern 0x0000000F, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFF0, Writing memory size 0x00001F40
Pattern 0x00000005, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFFA, Writing memory size 0x00001F40
Pattern 0x00000015, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFEA, Writing memory size 0x00001F40
Pattern 0x00000055, Writing memory size 0x00001F40
DDR addr 0x800062DC failed. Write value: 0x00000055, read value: 0x00FF0055
Flip Pattern: pattern 0xFFFFFFAA, Writing memory size 0x00001F40
Pattern 0x0000AAAA, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFF5555, Writing memory size 0x00001F40
DDR read & write completed
ERROR: ddr_ecc_test_main:403: Some tests have failed
4
Pattern 0x00000001, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFFE, Writing memory size 0x00001F40
Pattern 0x00000003, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFFC, Writing memory size 0x00001F40
Pattern 0x00000007, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFF8, Writing memory size 0x00001F40
Pattern 0x0000000F, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFF0, Writing memory size 0x00001F40
Pattern 0x00000005, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFFA, Writing memory size 0x00001F40
Pattern 0x00000015, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFEA, Writing memory size 0x00001F40
Pattern 0x00000055, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFAA, Writing memory size 0x00001F40
Pattern 0x0000AAAA, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFF5555, Writing memory size 0x00001F40
DDR read & write completed
All tests have passed!!
4
Pattern 0x00000001, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFFE, Writing memory size 0x00001F40
Pattern 0x00000003, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFFC, Writing memory size 0x00001F40
Pattern 0x00000007, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFF8, Writing memory size 0x00001F40
Pattern 0x0000000F, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFF0, Writing memory size 0x00001F40
Pattern 0x00000005, Writing memory size 0x00001F40
DDR addr 0x8000313C failed. Write value: 0x00000005, read value: 0x00FF0005
Flip Pattern: pattern 0xFFFFFFFA, Writing memory size 0x00001F40
Pattern 0x00000015, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFEA, Writing memory size 0x00001F40
Pattern 0x00000055, Writing memory size 0x00001F40
DDR addr 0x800070FC failed. Write value: 0x00000055, read value: 0x00FF0055
Flip Pattern: pattern 0xFFFFFFAA, Writing memory size 0x00001F40
DDR addr 0x800025BC failed. Write value: 0xFFFFFFAA, read value: 0xFF00FFAA
Pattern 0x0000AAAA, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFF5555, Writing memory size 0x00001F40
DDR read & write completed
ERROR: ddr_ecc_test_main:403: Some tests have failed
4
Pattern 0x00000001, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFFE, Writing memory size 0x00001F40
Pattern 0x00000003, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFFC, Writing memory size 0x00001F40
Pattern 0x00000007, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFF8, Writing memory size 0x00001F40
Pattern 0x0000000F, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFF0, Writing memory size 0x00001F40
DDR addr 0x800017FC failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
Pattern 0x00000005, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFFA, Writing memory size 0x00001F40
Pattern 0x00000015, Writing memory size 0x00001F40
Flip Pattern: pattern 0xFFFFFFEA, Writing memory size 0x00001F40
Pattern 0x00000055, Writing memory size 0x00001F40
DDR addr 0x800022DC failed. Write value: 0x00000055, read value: 0x00FF0055
Flip Pattern: pattern 0xFFFFFFAA, Writing memory size 0x00001F40
Pattern 0x0000AAAA, Writing memory size 0x00001F40
DDR addr 0x800022FC failed. Write value: 0x0000AAAA, read value: 0x00FFAAAA
Flip Pattern: pattern 0xFFFF5555, Writing memory size 0x00001F40
DDR read & write completed
ERROR: ddr_ecc_test_main:403: Some tests have failed

Could you please let us know the next step to debug?

Thanks,

Kevin

Hi Kevin, sorry for the delay in replying.  Here are some changes that need to be made in the configuration

CL=14:  Need to change this CAS latency to 14.  This is valid for 800MHz operation when read DBI is enabled

tXPR_tCK = 5 :  this is the tCK component in the datasheet

Did you use simulations to come up with the drive strength and termination settings?  I noticed you changed AC driver to 80ohm, memory read DQ driver to 48ohm, and processor read DQ odt to 40ohm.  Were these values from simulation?

Regards,

James

Hi James,

Thanks for your reply!

Customer now has modified CL=14, CWL=11 per your suggestion. But they still keep tXPR to be 216 tCK. The reason is that as you could see from the datasheet of this DDR, at 800MHz, the minimum value of txPR is the maximum value between 5nCK & tRFCmin+10ns. And since tRFCmin=260ns，so the tXPR = (260+10)/1.25 = 216 tCK.

3731.11201405001907_GDQ2BFAA-WQ_4Gb DDR4 SDRAM_v1.7.pdf

And customer make both the AC driver and ODT values as the default one. Also they used the oscilloscope to measure the signal quality and it meets their requirement. 

The updated sysconfig file is shown below.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/DDR4_2D00_1600_5F00_800MHz_5F00_CL14_5F00_CWL11_5F00_RPRCD175_5F00_settings_5F00_info.syscfg

Based on the above setup, they have done they following experiments.

1: Start from address 0x80000000, write & read 4096 * 32bits data every time, the test is okay

2: Start from address 0x80000000, write & read 8192 * 32bits data every time, the test is failed for some data

3: Start from address 0x80001000, write & read 4096 * 32bits data every time, the test is okay

4: Start from address 0x80001000, write & read 8192 * 32bits data every time, the test is failed for some data

The below log shows case 4, and we found that the corresponding DDR address of all the failed position ends with the character "C" in hexadecimal.

  
Starting OSPI Bootloader 0327 ... 
readDataCapDelay max, min: 2, 0
readDataCapDelay: 1

DMSC Firmware Version 9.1.6--v09.01.06 (Kool Koala)
DMSC Firmware revision 0x9
DMSC ABI revision 3.1

certLen:1623
imageLen:108712
[BOOTLOADER_PROFILE] Boot Media       : NOR SPI FLASH 
[BOOTLOADER_PROFILE] Boot Media Clock : 200.000 MHz 
[BOOTLOADER_PROFILE] Boot Image Size  : 0 KB 
[BOOTLOADER_PROFILE] Cores present    : 
r5f0-0
[BOOTLOADER PROFILE] SYSFW init                       :      12150us 
[BOOTLOADER PROFILE] System_init                      :     349515us 
[BOOTLOADER PROFILE] Drivers_open                     :        319us 
[BOOTLOADER PROFILE] Board_driversOpen                :       8708us 
[BOOTLOADER PROFILE] Sciclient Get Version            :      10021us 
[BOOTLOADER PROFILE] CPU load                         :       3411us 
[BOOTLOADER_PROFILE] SBL Total Time Taken             :     384128us 

Image loading done, switching to application ...
DDR addr 0x8000303C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR addr 0x8000403C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x80008A5C failed. Write value: 0xAAAAAAAA, read value: 0xAA55AAAA
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x8000661C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR addr 0x8000223C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR addr 0x8000105C failed. Write value: 0x00000015, read value: 0x00FF0015
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR addr 0x800024BC failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
DDR addr 0x80001F7C failed. Write value: 0x00000005, read value: 0x00FF0005
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR addr 0x800064FC failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x800044BC failed. Write value: 0x00000007, read value: 0x000A0007
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR addr 0x800084DC failed. Write value: 0x00000007, read value: 0x00FF0007
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x800044BC failed. Write value: 0xAAAAAAAA, read value: 0xAA55AAAA
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000311C failed. Write value: 0x00000003, read value: 0x00FF0003
DDR addr 0x8000649C failed. Write value: 0x00000003, read value: 0x00FF0003
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x800044DC failed. Write value: 0x00000055, read value: 0x00FB0055
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x8000649C failed. Write value: 0x00000003, read value: 0x00FF0003
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR addr 0x8000449C failed. Write value: 0x0000000F, read value: 0x00FF000F
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000503C failed. Write value: 0x00000007, read value: 0x00FF0007
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x8000425C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000451C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000505C failed. Write value: 0x00000055, read value: 0x00FF0055
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x800064BC failed. Write value: 0x00000007, read value: 0x00FF0007
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x8000303C failed. Write value: 0x00000055, read value: 0x00FF0055
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000249C failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8
DDR addr 0x800024DC failed. Write value: 0xAAAAAAAA, read value: 0xAA55AAAA
DDR addr 0x80007EDC failed. Write value: 0xAAAAAAAA, read value: 0xAA55AAAA
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x8000833C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR addr 0x80002A5C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR addr 0x8000703C failed. Write value: 0xFFFFFFAA, read value: 0xFF00FFAA
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000253C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000303C failed. Write value: 0x00000015, read value: 0x00FF0015
DDR addr 0x8000817C failed. Write value: 0x00000055, read value: 0x00FF0055
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x800064FC failed. Write value: 0x00000003, read value: 0x00FF0003
DDR addr 0x8000423C failed. Write value: 0x0000000F, read value: 0x00FF000F
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000653C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x800064DC failed. Write value: 0x0000000F, read value: 0x00FF000F
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x800023BC failed. Write value: 0x00000003, read value: 0x00FF0003
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000247C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000649C failed. Write value: 0xAAAAAAAA, read value: 0xAA55AAAA
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000451C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000229C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000295C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR addr 0x8000505C failed. Write value: 0x00000003, read value: 0x00FF0003
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x800044DC failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000703C failed. Write value: 0x0000000F, read value: 0x00FF000F
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x800061BC failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR addr 0x8000835C failed. Write value: 0x00000003, read value: 0x00FF0003
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x80006FFC failed. Write value: 0x00000015, read value: 0x00FF0015
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x800044DC failed. Write value: 0x00000007, read value: 0x00FF0007
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x800064DC failed. Write value: 0x00000015, read value: 0x00DF0015
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x800044BC failed. Write value: 0x00000007, read value: 0x00FF0007
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000451C failed. Write value: 0x00000003, read value: 0x00DB0003
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000471C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR addr 0x8000871C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000503C failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000505C failed. Write value: 0x00000003, read value: 0x00FF0003
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x800084BC failed. Write value: 0x00000005, read value: 0x00080005
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x80004F9C failed. Write value: 0xAAAAAAAA, read value: 0xAA55AAAA
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x80004F9C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x8000101C failed. Write value: 0x00000005, read value: 0x00FF0005
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x800064DC failed. Write value: 0x00000055, read value: 0x00FF0055
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x800023BC failed. Write value: 0x00000001, read value: 0x00FF0001
DDR addr 0x8000619C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x800084BC failed. Write value: 0x00000007, read value: 0x00FF0007
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000111C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR addr 0x8000653C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR addr 0x8000449C failed. Write value: 0x55555555, read value: 0x55AA5555
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000849C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x80006A5C failed. Write value: 0x00000055, read value: 0x00FF0055
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x8000103C failed. Write value: 0x00000007, read value: 0x00FF0007
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000827C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x800084BC failed. Write value: 0x00000055, read value: 0x00080055
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000451C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x80004FDC failed. Write value: 0x00000001, read value: 0x00FF0001
DDR addr 0x8000249C failed. Write value: 0x00000007, read value: 0x00FF0007
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR addr 0x80003EDC failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x800064DC failed. Write value: 0x00000001, read value: 0x00DF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000303C failed. Write value: 0x0000000F, read value: 0x00FF000F
DDR addr 0x800024BC failed. Write value: 0x00000015, read value: 0x00FF0015
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR addr 0x800024DC failed. Write value: 0x55555555, read value: 0x55AA5555
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x8000253C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR addr 0x8000431C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x80008F9C failed. Write value: 0xAAAAAAAA, read value: 0xAA55AAAA
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x800064BC failed. Write value: 0x0000000F, read value: 0x00FF000F
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x800024DC failed. Write value: 0x0000000F, read value: 0x00FF000F
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x8000305C failed. Write value: 0xFFFFFFFA, read value: 0xFF00FFFA
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR addr 0x8000105C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000449C failed. Write value: 0x00000007, read value: 0x00FF0007
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000505C failed. Write value: 0x00000003, read value: 0x00FF0003
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x800084BC failed. Write value: 0x00000007, read value: 0x00FF0007
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x8000421C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x800044DC failed. Write value: 0x00000005, read value: 0x00FF0005
DDR addr 0x800064BC failed. Write value: 0x00000055, read value: 0x00FF0055
DDR addr 0x80008A3C failed. Write value: 0x00000055, read value: 0x00FF0055
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x800084DC failed. Write value: 0x00000015, read value: 0x00FF0015
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x800023FC failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x8000505C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x8000247C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000303C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000621C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR addr 0x800024DC failed. Write value: 0x00000055, read value: 0x00FF0055
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000305C failed. Write value: 0x00000007, read value: 0x00FF0007
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000105C failed. Write value: 0x00000015, read value: 0x00FF0015
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000105C failed. Write value: 0x00000003, read value: 0x00FF0003
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR addr 0x80002FFC failed. Write value: 0x00000007, read value: 0x00FF0007
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR addr 0x800024BC failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR read & write completed
All tests have passed!!
DDR addr 0x8000235C failed. Write value: 0x00000001, read value: 0x00FF0001
DDR read & write completed
ERROR: ddr_ecc_test_main:503: Some tests have failed
DDR read & write completed
All tests have passed!!
DDR addr 0x8000223C failed. Write value: 0x00000003, read v

The corresponding test code is below. The main function only uses ddr_ecc_test_main function in the below code file.

/*
 *  Copyright (C) 2022 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <stdio.h>
#include <kernel/dpl/DebugP.h>
#include "ti_drivers_config.h"
#include "ti_drivers_open_close.h"
#include "ti_board_open_close.h"

#include <drivers/esm.h>
#include <drivers/ddr.h>

/*******************************************************************************
This example simulates a 1b and 2b ECC error in DDR  ECC enabled region.
The application receives a Low priority interrupt through the ESM module as
configured in SysCfg when a 1b error is generated.
A high priority interrupt is received through ESM module as configured in SysCfg
when a 2b error is generated.

The single bit ECC errors will be corrected by the DDR, but the dual bit ECC
errors is only detected and is not corrected.
User could do a warm reset or do necessaryy corrective action to resolve the
dual bit ECC errors
*******************************************************************************/

#define DDR_START_ADDR (0x90000000u)
#define DDR_START_ADDR_1 (0x80000001u)
#define DDR_START_ADDR_3 (0x80000003u)

//#define TEST_SIZE       6400000000000000000000
#define TEST_SIZE       200000
#define LOOP_CYCLES     1000
#define TEST_PATTERN    0x00000001

/* Memory block for which ECC is calculated (256 Bytes) */
#define DDR_EMIF_ECC_MEM_BLOCK_SIZE       0x100
/* ECC data size per block (32 Bytes) */
#define DDR_EMIF_ECC_DATA_SIZE_PER_BLOCK  0x20

//#define DDR_ECC_TEST_ADDR               (DDR_START_ADDR + DDR_ECC_REGION0_START \
                                        + DDR_EMIF_ECC_MEM_BLOCK_SIZE)
#define DDR_ECC_TEST_ADDR  (0x80000000u)

/* esm_lvl_event for DDR single error */
#define DDR_ECC_AGGR0_SEC_ERR_EVENT    (CSLR_ESM0_ESM_LVL_EVENT_DDR16SS0_DDRSS_DRAM_ECC_CORR_ERR_LVL_0)
/* esm_lvl_event for DDR double error */
#define DDR_ECC_AGGR0_DED_ERR_EVENT    (CSLR_ESM0_ESM_LVL_EVENT_DDR16SS0_DDRSS_DRAM_ECC_UNCORR_ERR_LVL_0)

volatile uint32_t gSecTestPass;
volatile uint32_t gDedTestPass;

volatile uint32_t *gTest_Addr = NULL;
volatile uint32_t testVal;

uintptr_t DDRGetTranslatedAddress (uintptr_t memAddress)
{
    uint32_t memIndex;
    uintptr_t translatedMemAddr;

    memIndex = (memAddress - DDR_START_ADDR)/DDR_EMIF_ECC_MEM_BLOCK_SIZE;

    if ((memIndex & 0x1u) == 0)
    {
        translatedMemAddr = memAddress + ((memIndex)*DDR_EMIF_ECC_DATA_SIZE_PER_BLOCK);
    }
    else
    {
        translatedMemAddr = memAddress + ((memIndex+1u)*DDR_EMIF_ECC_DATA_SIZE_PER_BLOCK);
    }
    return  translatedMemAddr;
}

/* Handler for single bit ECC error */
void DDR_secHandler (void *args)
{
    int32_t status = SystemP_SUCCESS;
    DDR_ECCErrorInfo ECCErrorInfo;

    /* Read ECC registers and double check address */
    status = DDR_getECCErrorInfo (&ECCErrorInfo);

    if (status == SystemP_SUCCESS)
    {
        if ((ECCErrorInfo.singlebitErrorAddress & (~0x7u))
            == ((DDR_ECC_TEST_ADDR - DDR_START_ADDR) & (~0x7u)))
        {
            gSecTestPass = TRUE;
        }

        /* Clear Specific ECC error */
        status = DDR_clearECCError (DDR_ECC_1B_ERROR);
    }
}

/* Handler for double bit ECC error */
void DDR_dedHandler (void *args)
{
    int32_t status = SystemP_SUCCESS;
    DDR_ECCErrorInfo ECCErrorInfo;
    volatile uint32_t *translatedMemPtr;

    status = DDR_getECCErrorInfo (&ECCErrorInfo);

    if (status == SystemP_SUCCESS)
    {
        if ((ECCErrorInfo.doublebitErrorAddress & (~0x7u))
            == ((DDR_ECC_TEST_ADDR - DDR_START_ADDR) & (~0x7u)))
        {
            gDedTestPass = TRUE;

            /* This section corrects the ECC error simulated */
            /* In a real application the user must take necessary corrective action */
            /******************************************************************/

            /* Disable Inline ECC */
            DDR_enableInlineECC(0);

            translatedMemPtr = (volatile uint32_t *)(DDRGetTranslatedAddress ((uintptr_t)gTest_Addr));

            /* Now replace location with original value as 2b errors are not corrected */
            *(translatedMemPtr) = testVal;

            /* Write back any pending writes */
            CacheP_wbInv ((void *)translatedMemPtr, 4, CacheP_TYPE_ALL);

            /* Enable back ECC */
            DDR_enableInlineECC (1);

            /******************************************************************/
        }

        /* Clear specific error */
        status = DDR_clearECCError (DDR_ECC_2B_ERROR);
    }

}

int32_t DDR_secErrTest (void)
{
    int32_t status = SystemP_SUCCESS;
    volatile uint32_t testVal2;
    volatile uint32_t *translatedMemPtr;
    uint32_t waitCount = 0;

    gSecTestPass = FALSE;

    /* Clear any residual ECC errors */
    DDR_clearECCError (DDR_ECC_ERR_ALL);

    /* Inject error */
    gTest_Addr = (uint32_t *) (DDR_ECC_TEST_ADDR);

    /* Write back any pending writes */
    CacheP_wbInv ((void *)gTest_Addr, 4, CacheP_TYPE_ALL);

    /* Read value from test location */
    testVal = gTest_Addr[0];

    /* Flip one bit to introduce error */
    testVal2 = testVal ^ 0x00010000u;

    /* Calculate translated address */
    translatedMemPtr = (volatile uint32_t *)(DDRGetTranslatedAddress ((uintptr_t)gTest_Addr));

    /* Generating a 1b ECC error */
    /* NOTE: The following section should NOT be useed in actual application */
    /* ================================================================================ */

    /* Temporarily disable ECC */
    DDR_enableInlineECC (0);

    /* Now corrupt the value */
    *(translatedMemPtr) = testVal2;
    CacheP_wbInv ((void *)translatedMemPtr, 4, CacheP_TYPE_ALL);

    /* Enable back ECC */
    DDR_enableInlineECC (1);

    /* ================================================================================ */

    /* Invalidate cache */
    CacheP_inv ((void *)gTest_Addr, 4, CacheP_TYPE_ALL);

    /* Read value to trigger error */
    testVal2 = gTest_Addr[0];

    DebugP_log ("Waiting on Single bit Error Correction Interrupt...\r\n");

    while ((gSecTestPass == FALSE) && (waitCount++ < 100u))
    {
        ClockP_usleep(10);
    }

    if (gSecTestPass == TRUE)
    {
        DebugP_log ("1b ECC error detected and corrected\r\n");
        status = SystemP_SUCCESS;
    }
    else
    {
        DebugP_logError ("1b Inline ECC test failed timedout ...\r\n");
    }

    /* Restore original value */
    gTest_Addr[0] = testVal;

    /* Write back any pending writes */
    CacheP_wbInv ((void *)gTest_Addr, 4, CacheP_TYPE_ALL);

    return status;
}

int32_t DDR_dedErrTest (void)
{
    int32_t status = SystemP_SUCCESS;
    volatile uint32_t testVal;
    volatile uint32_t testVal2;
    volatile uint32_t *translatedMemPtr;
    uint32_t waitCount = 0;

    gDedTestPass = FALSE;

    /* Clear any residual ECC errors */
    DDR_clearECCError (DDR_ECC_ERR_ALL);

    gTest_Addr = (uint32_t *) (DDR_ECC_TEST_ADDR);

    CacheP_wbInv ((void *)gTest_Addr, 4, CacheP_TYPE_ALL);
    /* Read reference value */
    testVal       = gTest_Addr[0];
    /* flip 2 bits */
    testVal2       = testVal ^ 0x00101000u;
    /* Calculate translated address */
    translatedMemPtr = (volatile uint32_t *)(DDRGetTranslatedAddress ((uintptr_t)gTest_Addr));

    /* Generating a 2b ECC error */
    /* NOTE: The following section should NOT be useed in actual application */
    /* ================================================================================ */

    /* Temporarily disable ECC */
    DDR_enableInlineECC (0);

    /* Now corrupt the value */
    *(translatedMemPtr) = testVal2;

    /* Make sure the values are written back */
    CacheP_wbInv ((void *)translatedMemPtr, 4, CacheP_TYPE_ALL);

    /* Enable back ECC */
    DDR_enableInlineECC (1);

    /* ================================================================================ */

    /* Invalidate cache */
    CacheP_inv ((void *)gTest_Addr, 4, CacheP_TYPE_ALL);

    /* Read value to trigger error */
    testVal2 = gTest_Addr[0];

    DebugP_log ("Waiting on Dual bit error detection Interrupt...\r\n");

    while ((gDedTestPass == FALSE) && (waitCount++ < 100u))
    {
        ClockP_usleep (100);
    }

    if (gDedTestPass == TRUE)
    {
        DebugP_log ("2b ECC error detected\r\n");
        status = SystemP_SUCCESS;
    }
    else
    {
        DebugP_logError ("2b Inline ECC Test failed timedout ...\r\n");
        status = SystemP_FAILURE;
    }

    /* Restore original value */
    gTest_Addr[0] = testVal;

    return status;
}

int32_t ddr_read_write_test(uint64_t SIZE, uint32_t StartAddress)
{
    int32_t status = SystemP_SUCCESS;
    //uint32_t *ddr_ptr = (uint32_t *)DDR_START_ADDR;
    uint32_t *ddr_ptr = (uint32_t *)StartAddress;
    uint64_t i, j, n;
    uint32_t flip_test_pattern;
    uint32_t pattern[] = {0x01, 0x03, 0x07, 0x0F, 0x05, 0x15, 0x55, 0xAAAAAAAA};
    uint32_t test_pattern;
    uint16_t BA, Col, Row;
    uint32_t Addr_Failed;
    //DebugP_log ("%d\r\n", loop_cycles);

    for(j = 0; j < 8; j++)
    {
        test_pattern = pattern[j];
        //DebugP_log("Pattern 0x%04X, Writing memory size 0x%04X\r\n", test_pattern, TEST_SIZE*loop_cycles);
/*        for(n = 0; n < TEST_SIZE; n++)
        {
            for(i = 0; i < TEST_SIZE; i++)
            {
                ddr_ptr[TEST_SIZE * n + i] = test_pattern;
                //ClockP_usleep (1);
            }
        }*/

        for(i = 0; i < SIZE; i++)
        {
            ddr_ptr[i] = test_pattern;
        }

        //CacheP_wbInv ((void *)ddr_ptr, 4, TEST_SIZE * n);
        n = 0;

        //CacheP_inv ((void *)ddr_ptr, 4, TEST_SIZE);
        //for(i = 0; i < TEST_SIZE*loop_cycles; i++)
        for(i = 0; i < SIZE; i++)
        {
            if(ddr_ptr[i] != test_pattern)
            {
                Addr_Failed = (uint32_t)&ddr_ptr[i];
                Col = Addr_Failed & 0x3FF;
                BA = (Addr_Failed >> 10) & 0x03;
                Row = (Addr_Failed >> 12) & 0x7FFF;
                DebugP_log("DDR addr 0x%08X failed. Write value: 0x%08X, read value: 0x%08X\r\n", (uint32_t)&ddr_ptr[i], test_pattern, ddr_ptr[i]);
                //DebugP_log("DDR addr 0x%08X failed. Write value: 0x%04X, read value: 0x%04X\r\nDDR addr: BA: %d, COL: 0x%04X, ROW: 0x%04X\r\n", Addr_Failed, test_pattern, ddr_ptr[i], BA, Col, Row);

                status = SystemP_FAILURE;
            }
            //ClockP_usleep (1);
        }

        flip_test_pattern = ~test_pattern;
        //DebugP_log("Flip Pattern: pattern 0x%04X, Writing memory size 0x%08X\r\n", flip_test_pattern, TEST_SIZE*loop_cycles);

/*        for(n = 0; n < loop_cycles; n++)
        {
            for(i = 0; i < TEST_SIZE; i++)
            {
                ddr_ptr[TEST_SIZE * n + i] = flip_test_pattern;
            }
        }*/
        for(i = 0; i < SIZE; i++)
        {
            ddr_ptr[i] = flip_test_pattern;
        }

        CacheP_wbInv ((void *)ddr_ptr, 4, TEST_SIZE);
        //CacheP_inv ((void *)ddr_ptr, 4, TEST_SIZE);

        //for(i = 0; i < TEST_SIZE*loop_cycles; i++)
        for(i = 0; i < SIZE; i++)
        {
            if(ddr_ptr[i] != flip_test_pattern )
            {
                DebugP_log("DDR addr 0x%08X failed. Write value: 0x%08X, read value: 0x%08X\r\n", (uint32_t)&ddr_ptr[i], flip_test_pattern, ddr_ptr[i]);
                Addr_Failed = (uint32_t)&ddr_ptr[i];
                Col = Addr_Failed & 0x3FF;
                BA = (Addr_Failed >> 10) & 0x03;
                Row = (Addr_Failed >> 12) & 0x7FFF;
                //DebugP_log("DDR addr 0x%08X failed. Write value: 0x%04X, read value: 0x%04X\r\nDDR addr: BA: %d, COL: 0x%04X, ROW: 0x%04X\r\n", Addr_Failed, flip_test_pattern, ddr_ptr[i], BA, Col, Row);
                status = SystemP_FAILURE;
            }
            //ClockP_usleep (1);
        }
    }

    DebugP_log ("DDR read & write completed\r\n");
    return status;
}

void ddr_test(void)
{
    uint32_t pattern_32[] = {0x48FB02D6, 0x12345678, 0x2468B0DF, 0x13579ACE};
    uint16_t pattern_16[] = {0x1357, 0x9ACE, 0x2468, 0xB0DF, 0x1234, 0x5678, 0x48FB, 0x02D6};
    uint32_t *ddr_ptr_write = (uint32_t *)DDR_START_ADDR_1;
    uint16_t *ddr_ptr_read = (uint16_t *)DDR_START_ADDR_1;

    uint32_t *ddr_ptr_write_test_1 = (uint32_t *)DDR_START_ADDR_1;
    uint32_t *ddr_ptr_write_test_2 = (uint32_t *)(DDR_START_ADDR_1 + 1);
    uint32_t *ddr_ptr_write_test_3 = (uint32_t *)(DDR_START_ADDR_1 + 2);
    uint32_t *ddr_ptr_write_test_4 = (uint32_t *)(DDR_START_ADDR_1 + 3);

    uint16_t *ddr_ptr_read_test_1 = (uint16_t *)DDR_START_ADDR_1;
    uint16_t *ddr_ptr_read_test_2 = (uint16_t *)(DDR_START_ADDR_1 + 1);
    uint16_t *ddr_ptr_read_test_3 = (uint16_t *)(DDR_START_ADDR_1 + 2);
    uint16_t *ddr_ptr_read_test_4 = (uint16_t *)(DDR_START_ADDR_1 + 3);

    int16_t i = 0;
    DebugP_log ("\r\n");

/*    for(i = 0; i < 4; i++)
    {
        ddr_ptr_write[i] = pattern_16[i];
        //ClockP_usleep (1);
    }*/

    i = 0;

    //CacheP_inv ((void *)ddr_ptr, 4, TEST_SIZE);
/*    for(i = 0; i < 10; i++)
    {
        //DebugP_log("DDR addr 0x%08X failed. Write value: 0x%04X, read value: 0x%04X\r\n", (uint32_t)&ddr_ptr[i], test_pattern, ddr_ptr[i]);



        //ClockP_usleep (1);
    }*/



    ddr_ptr_write_test_1[0] = pattern_32[0];
    DebugP_log("DDR addr 0x80000001. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[0], ddr_ptr_read_test_1[0]);
    DebugP_log("DDR addr 0x80000002. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[0], ddr_ptr_read_test_2[0]);
    DebugP_log("DDR addr 0x80000003. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[0], ddr_ptr_read_test_3[0]);
    DebugP_log("DDR addr 0x80000004. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[0], ddr_ptr_read_test_4[0]);

    ddr_ptr_write_test_2[0] = pattern_32[1];
    DebugP_log("DDR addr 0x80000001. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[1], ddr_ptr_read_test_1[0]);
    DebugP_log("DDR addr 0x80000002. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[1], ddr_ptr_read_test_2[0]);
    DebugP_log("DDR addr 0x80000003. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[1], ddr_ptr_read_test_3[0]);
    DebugP_log("DDR addr 0x80000004. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[1], ddr_ptr_read_test_4[0]);
    ddr_ptr_write_test_3[0] = pattern_32[2];
    DebugP_log("DDR addr 0x80000001. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[2], ddr_ptr_read_test_1[0]);
    DebugP_log("DDR addr 0x80000002. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[2], ddr_ptr_read_test_2[0]);
    DebugP_log("DDR addr 0x80000003. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[2], ddr_ptr_read_test_3[0]);
    DebugP_log("DDR addr 0x80000004. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[2], ddr_ptr_read_test_4[0]);

    ddr_ptr_write_test_4[0] = pattern_32[3];
    DebugP_log("DDR addr 0x80000001. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[3], ddr_ptr_read_test_1[0]);
    DebugP_log("DDR addr 0x80000002. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[3], ddr_ptr_read_test_2[0]);
    DebugP_log("DDR addr 0x80000003. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[3], ddr_ptr_read_test_3[0]);
    DebugP_log("DDR addr 0x80000004. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[3], ddr_ptr_read_test_4[0]);





}

void ddr_ecc_test_main (void *args)
{
    int32_t status;
    uint64_t size = 8192;
    uint32_t startAdd = 0x80001000;

    /* Open drivers to open the UART driver for console */
    Drivers_open ();
    Board_driversOpen ();

    gSecTestPass = FALSE;
    gDedTestPass = FALSE;

/*    status = DDR_secErrTest ();

    if (status == SystemP_SUCCESS)
    {
        status = DDR_dedErrTest ();
    }*/
    while(1)
    {
        status = ddr_read_write_test(size, startAdd);
        //ddr_test();

        if (status == SystemP_SUCCESS)
        {
            DebugP_log ("All tests have passed!!\r\n");
        }
        else
        {
            DebugP_logError ("Some tests have failed\r\n");
        }
    }

    Board_driversClose ();
    Drivers_close ();
}

Customer also made another try, this time after they write a 32bits data they read back 8bits data for 4 times. By doing so, we found that the corresponding DDR address of all the failed position ends with the character "E" in hexadecimal. Please see the corresponding code and log below, thanks!

/*
 *  Copyright (C) 2022 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <stdio.h>
#include <kernel/dpl/DebugP.h>
#include "ti_drivers_config.h"
#include "ti_drivers_open_close.h"
#include "ti_board_open_close.h"

#include <drivers/esm.h>
#include <drivers/ddr.h>

/*******************************************************************************
This example simulates a 1b and 2b ECC error in DDR  ECC enabled region.
The application receives a Low priority interrupt through the ESM module as
configured in SysCfg when a 1b error is generated.
A high priority interrupt is received through ESM module as configured in SysCfg
when a 2b error is generated.

The single bit ECC errors will be corrected by the DDR, but the dual bit ECC
errors is only detected and is not corrected.
User could do a warm reset or do necessaryy corrective action to resolve the
dual bit ECC errors
*******************************************************************************/

#define DDR_START_ADDR (0x90000000u)
#define DDR_START_ADDR_1 (0x80000001u)
#define DDR_START_ADDR_3 (0x80000003u)

//#define TEST_SIZE       6400000000000000000000
#define TEST_SIZE       200000
#define LOOP_CYCLES     1000
#define TEST_PATTERN    0x00000001

/* Memory block for which ECC is calculated (256 Bytes) */
#define DDR_EMIF_ECC_MEM_BLOCK_SIZE       0x100
/* ECC data size per block (32 Bytes) */
#define DDR_EMIF_ECC_DATA_SIZE_PER_BLOCK  0x20

//#define DDR_ECC_TEST_ADDR               (DDR_START_ADDR + DDR_ECC_REGION0_START \
                                        + DDR_EMIF_ECC_MEM_BLOCK_SIZE)
#define DDR_ECC_TEST_ADDR  (0x80000000u)

/* esm_lvl_event for DDR single error */
#define DDR_ECC_AGGR0_SEC_ERR_EVENT    (CSLR_ESM0_ESM_LVL_EVENT_DDR16SS0_DDRSS_DRAM_ECC_CORR_ERR_LVL_0)
/* esm_lvl_event for DDR double error */
#define DDR_ECC_AGGR0_DED_ERR_EVENT    (CSLR_ESM0_ESM_LVL_EVENT_DDR16SS0_DDRSS_DRAM_ECC_UNCORR_ERR_LVL_0)

volatile uint32_t gSecTestPass;
volatile uint32_t gDedTestPass;

volatile uint32_t *gTest_Addr = NULL;
volatile uint32_t testVal;

uintptr_t DDRGetTranslatedAddress (uintptr_t memAddress)
{
    uint32_t memIndex;
    uintptr_t translatedMemAddr;

    memIndex = (memAddress - DDR_START_ADDR)/DDR_EMIF_ECC_MEM_BLOCK_SIZE;

    if ((memIndex & 0x1u) == 0)
    {
        translatedMemAddr = memAddress + ((memIndex)*DDR_EMIF_ECC_DATA_SIZE_PER_BLOCK);
    }
    else
    {
        translatedMemAddr = memAddress + ((memIndex+1u)*DDR_EMIF_ECC_DATA_SIZE_PER_BLOCK);
    }
    return  translatedMemAddr;
}

/* Handler for single bit ECC error */
void DDR_secHandler (void *args)
{
    int32_t status = SystemP_SUCCESS;
    DDR_ECCErrorInfo ECCErrorInfo;

    /* Read ECC registers and double check address */
    status = DDR_getECCErrorInfo (&ECCErrorInfo);

    if (status == SystemP_SUCCESS)
    {
        if ((ECCErrorInfo.singlebitErrorAddress & (~0x7u))
            == ((DDR_ECC_TEST_ADDR - DDR_START_ADDR) & (~0x7u)))
        {
            gSecTestPass = TRUE;
        }

        /* Clear Specific ECC error */
        status = DDR_clearECCError (DDR_ECC_1B_ERROR);
    }
}

/* Handler for double bit ECC error */
void DDR_dedHandler (void *args)
{
    int32_t status = SystemP_SUCCESS;
    DDR_ECCErrorInfo ECCErrorInfo;
    volatile uint32_t *translatedMemPtr;

    status = DDR_getECCErrorInfo (&ECCErrorInfo);

    if (status == SystemP_SUCCESS)
    {
        if ((ECCErrorInfo.doublebitErrorAddress & (~0x7u))
            == ((DDR_ECC_TEST_ADDR - DDR_START_ADDR) & (~0x7u)))
        {
            gDedTestPass = TRUE;

            /* This section corrects the ECC error simulated */
            /* In a real application the user must take necessary corrective action */
            /******************************************************************/

            /* Disable Inline ECC */
            DDR_enableInlineECC(0);

            translatedMemPtr = (volatile uint32_t *)(DDRGetTranslatedAddress ((uintptr_t)gTest_Addr));

            /* Now replace location with original value as 2b errors are not corrected */
            *(translatedMemPtr) = testVal;

            /* Write back any pending writes */
            CacheP_wbInv ((void *)translatedMemPtr, 4, CacheP_TYPE_ALL);

            /* Enable back ECC */
            DDR_enableInlineECC (1);

            /******************************************************************/
        }

        /* Clear specific error */
        status = DDR_clearECCError (DDR_ECC_2B_ERROR);
    }

}

int32_t DDR_secErrTest (void)
{
    int32_t status = SystemP_SUCCESS;
    volatile uint32_t testVal2;
    volatile uint32_t *translatedMemPtr;
    uint32_t waitCount = 0;

    gSecTestPass = FALSE;

    /* Clear any residual ECC errors */
    DDR_clearECCError (DDR_ECC_ERR_ALL);

    /* Inject error */
    gTest_Addr = (uint32_t *) (DDR_ECC_TEST_ADDR);

    /* Write back any pending writes */
    CacheP_wbInv ((void *)gTest_Addr, 4, CacheP_TYPE_ALL);

    /* Read value from test location */
    testVal = gTest_Addr[0];

    /* Flip one bit to introduce error */
    testVal2 = testVal ^ 0x00010000u;

    /* Calculate translated address */
    translatedMemPtr = (volatile uint32_t *)(DDRGetTranslatedAddress ((uintptr_t)gTest_Addr));

    /* Generating a 1b ECC error */
    /* NOTE: The following section should NOT be useed in actual application */
    /* ================================================================================ */

    /* Temporarily disable ECC */
    DDR_enableInlineECC (0);

    /* Now corrupt the value */
    *(translatedMemPtr) = testVal2;
    CacheP_wbInv ((void *)translatedMemPtr, 4, CacheP_TYPE_ALL);

    /* Enable back ECC */
    DDR_enableInlineECC (1);

    /* ================================================================================ */

    /* Invalidate cache */
    CacheP_inv ((void *)gTest_Addr, 4, CacheP_TYPE_ALL);

    /* Read value to trigger error */
    testVal2 = gTest_Addr[0];

    DebugP_log ("Waiting on Single bit Error Correction Interrupt...\r\n");

    while ((gSecTestPass == FALSE) && (waitCount++ < 100u))
    {
        ClockP_usleep(10);
    }

    if (gSecTestPass == TRUE)
    {
        DebugP_log ("1b ECC error detected and corrected\r\n");
        status = SystemP_SUCCESS;
    }
    else
    {
        DebugP_logError ("1b Inline ECC test failed timedout ...\r\n");
    }

    /* Restore original value */
    gTest_Addr[0] = testVal;

    /* Write back any pending writes */
    CacheP_wbInv ((void *)gTest_Addr, 4, CacheP_TYPE_ALL);

    return status;
}

int32_t DDR_dedErrTest (void)
{
    int32_t status = SystemP_SUCCESS;
    volatile uint32_t testVal;
    volatile uint32_t testVal2;
    volatile uint32_t *translatedMemPtr;
    uint32_t waitCount = 0;

    gDedTestPass = FALSE;

    /* Clear any residual ECC errors */
    DDR_clearECCError (DDR_ECC_ERR_ALL);

    gTest_Addr = (uint32_t *) (DDR_ECC_TEST_ADDR);

    CacheP_wbInv ((void *)gTest_Addr, 4, CacheP_TYPE_ALL);
    /* Read reference value */
    testVal       = gTest_Addr[0];
    /* flip 2 bits */
    testVal2       = testVal ^ 0x00101000u;
    /* Calculate translated address */
    translatedMemPtr = (volatile uint32_t *)(DDRGetTranslatedAddress ((uintptr_t)gTest_Addr));

    /* Generating a 2b ECC error */
    /* NOTE: The following section should NOT be useed in actual application */
    /* ================================================================================ */

    /* Temporarily disable ECC */
    DDR_enableInlineECC (0);

    /* Now corrupt the value */
    *(translatedMemPtr) = testVal2;

    /* Make sure the values are written back */
    CacheP_wbInv ((void *)translatedMemPtr, 4, CacheP_TYPE_ALL);

    /* Enable back ECC */
    DDR_enableInlineECC (1);

    /* ================================================================================ */

    /* Invalidate cache */
    CacheP_inv ((void *)gTest_Addr, 4, CacheP_TYPE_ALL);

    /* Read value to trigger error */
    testVal2 = gTest_Addr[0];

    DebugP_log ("Waiting on Dual bit error detection Interrupt...\r\n");

    while ((gDedTestPass == FALSE) && (waitCount++ < 100u))
    {
        ClockP_usleep (100);
    }

    if (gDedTestPass == TRUE)
    {
        DebugP_log ("2b ECC error detected\r\n");
        status = SystemP_SUCCESS;
    }
    else
    {
        DebugP_logError ("2b Inline ECC Test failed timedout ...\r\n");
        status = SystemP_FAILURE;
    }

    /* Restore original value */
    gTest_Addr[0] = testVal;

    return status;
}

int32_t ddr_read_write_test(uint64_t SIZE, uint32_t StartAddress)
{
    int32_t status = SystemP_SUCCESS;
    //uint32_t *ddr_ptr = (uint32_t *)DDR_START_ADDR;
    uint32_t *ddr_ptr = (uint32_t *)StartAddress;
    uint8_t *ddr_ptr_rd = (uint8_t *)StartAddress;
    uint64_t i, j, n;
    uint32_t flip_test_pattern;
    uint32_t pattern[] = {0x01, 0x03, 0x07, 0x0F, 0x05, 0x15, 0x55, 0xAAAAAAAA};
    uint32_t test_pattern;
    uint16_t BA, Col, Row;
    uint32_t Addr_Failed;
    uint8_t write;
    //DebugP_log ("%d\r\n", loop_cycles);

    for(j = 0; j < 8; j++)
    {
        test_pattern = pattern[j];
        //DebugP_log("Pattern 0x%04X, Writing memory size 0x%04X\r\n", test_pattern, TEST_SIZE*loop_cycles);
/*        for(n = 0; n < TEST_SIZE; n++)
        {
            for(i = 0; i < TEST_SIZE; i++)
            {
                ddr_ptr[TEST_SIZE * n + i] = test_pattern;
                //ClockP_usleep (1);
            }
        }*/

        for(i = 0; i < SIZE; i++)
        {
            ddr_ptr[i] = test_pattern;
        }

        //CacheP_wbInv ((void *)ddr_ptr, 4, TEST_SIZE * n);
        n = 0;

        //CacheP_inv ((void *)ddr_ptr, 4, TEST_SIZE);
        //for(i = 0; i < TEST_SIZE*loop_cycles; i++)
        for(i = 0; i < SIZE*4; i++)
        {
/*            if(ddr_ptr[i] != test_pattern)
            {
                Addr_Failed = (uint32_t)&ddr_ptr[i];
                Col = Addr_Failed & 0x3FF;
                BA = (Addr_Failed >> 10) & 0x03;
                Row = (Addr_Failed >> 12) & 0x7FFF;
                DebugP_log("DDR addr 0x%08X failed. Write value: 0x%08X, read value: 0x%08X\r\n", (uint32_t)&ddr_ptr[i], test_pattern, ddr_ptr[i]);
                //DebugP_log("DDR addr 0x%08X failed. Write value: 0x%04X, read value: 0x%04X\r\nDDR addr: BA: %d, COL: 0x%04X, ROW: 0x%04X\r\n", Addr_Failed, test_pattern, ddr_ptr[i], BA, Col, Row);

                status = SystemP_FAILURE;
            }*/

                write = (uint8_t)(test_pattern >> (8 * n));
                if(ddr_ptr_rd[i] != write)
                {
                    DebugP_log("DDR addr 0x%08X failed. Write value: 0x%04X, read value: 0x%04X\r\n", (uint32_t)&ddr_ptr_rd[i], write, ddr_ptr_rd[i]);
                    //DebugP_log("DDR addr 0x%08X failed. Write value: 0x%04X, read value: 0x%04X\r\nDDR addr: BA: %d, COL: 0x%04X, ROW: 0x%04X\r\n", Addr_Failed, test_pattern, ddr_ptr[i], BA, Col, Row);

                    status = SystemP_FAILURE;
                }
                n ++;
                if(n == 4)
                    n = 0;
            //ClockP_usleep (1);
        }

        flip_test_pattern = ~test_pattern;
        n = 0;
        //DebugP_log("Flip Pattern: pattern 0x%04X, Writing memory size 0x%08X\r\n", flip_test_pattern, TEST_SIZE*loop_cycles);

/*        for(n = 0; n < loop_cycles; n++)
        {
            for(i = 0; i < TEST_SIZE; i++)
            {
                ddr_ptr[TEST_SIZE * n + i] = flip_test_pattern;
            }
        }*/
        for(i = 0; i < SIZE; i++)
        {
            ddr_ptr[i] = flip_test_pattern;
        }

        CacheP_wbInv ((void *)ddr_ptr, 4, TEST_SIZE);
        //CacheP_inv ((void *)ddr_ptr, 4, TEST_SIZE);

        //for(i = 0; i < TEST_SIZE*loop_cycles; i++)
        for(i = 0; i < SIZE*4; i++)
        {
/*            if(ddr_ptr[i] != flip_test_pattern )
            {
                DebugP_log("DDR addr 0x%08X failed. Write value: 0x%08X, read value: 0x%08X\r\n", (uint32_t)&ddr_ptr[i], flip_test_pattern, ddr_ptr[i]);
                Addr_Failed = (uint32_t)&ddr_ptr[i];
                Col = Addr_Failed & 0x3FF;
                BA = (Addr_Failed >> 10) & 0x03;
                Row = (Addr_Failed >> 12) & 0x7FFF;
                //DebugP_log("DDR addr 0x%08X failed. Write value: 0x%04X, read value: 0x%04X\r\nDDR addr: BA: %d, COL: 0x%04X, ROW: 0x%04X\r\n", Addr_Failed, flip_test_pattern, ddr_ptr[i], BA, Col, Row);
                status = SystemP_FAILURE;
            }*/
            //ClockP_usleep (1);
            write = (uint8_t)(flip_test_pattern >> (8 * n));
            if(ddr_ptr_rd[i] != write)
            {
                DebugP_log("DDR addr 0x%08X failed. Write value: 0x%04X, read value: 0x%04X\r\n", (uint32_t)&ddr_ptr_rd[i], write, ddr_ptr_rd[i]);
                //DebugP_log("DDR addr 0x%08X failed. Write value: 0x%04X, read value: 0x%04X\r\nDDR addr: BA: %d, COL: 0x%04X, ROW: 0x%04X\r\n", Addr_Failed, test_pattern, ddr_ptr[i], BA, Col, Row);

                status = SystemP_FAILURE;
            }
            n ++;
            if(n == 4)
                n = 0;
        }
    }

    DebugP_log ("DDR read & write completed\r\n");
    return status;
}

void ddr_test(void)
{
    uint32_t pattern_32[] = {0x48FB02D6, 0x12345678, 0x2468B0DF, 0x13579ACE};
    uint16_t pattern_16[] = {0x1357, 0x9ACE, 0x2468, 0xB0DF, 0x1234, 0x5678, 0x48FB, 0x02D6};
    uint32_t *ddr_ptr_write = (uint32_t *)DDR_START_ADDR_1;
    uint16_t *ddr_ptr_read = (uint16_t *)DDR_START_ADDR_1;

    uint32_t *ddr_ptr_write_test_1 = (uint32_t *)DDR_START_ADDR_1;
    uint32_t *ddr_ptr_write_test_2 = (uint32_t *)(DDR_START_ADDR_1 + 1);
    uint32_t *ddr_ptr_write_test_3 = (uint32_t *)(DDR_START_ADDR_1 + 2);
    uint32_t *ddr_ptr_write_test_4 = (uint32_t *)(DDR_START_ADDR_1 + 3);

    uint16_t *ddr_ptr_read_test_1 = (uint16_t *)DDR_START_ADDR_1;
    uint16_t *ddr_ptr_read_test_2 = (uint16_t *)(DDR_START_ADDR_1 + 1);
    uint16_t *ddr_ptr_read_test_3 = (uint16_t *)(DDR_START_ADDR_1 + 2);
    uint16_t *ddr_ptr_read_test_4 = (uint16_t *)(DDR_START_ADDR_1 + 3);

    int16_t i = 0;
    DebugP_log ("\r\n");

/*    for(i = 0; i < 4; i++)
    {
        ddr_ptr_write[i] = pattern_16[i];
        //ClockP_usleep (1);
    }*/

    i = 0;

    //CacheP_inv ((void *)ddr_ptr, 4, TEST_SIZE);
/*    for(i = 0; i < 10; i++)
    {
        //DebugP_log("DDR addr 0x%08X failed. Write value: 0x%04X, read value: 0x%04X\r\n", (uint32_t)&ddr_ptr[i], test_pattern, ddr_ptr[i]);



        //ClockP_usleep (1);
    }*/



    ddr_ptr_write_test_1[0] = pattern_32[0];
    DebugP_log("DDR addr 0x80000001. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[0], ddr_ptr_read_test_1[0]);
    DebugP_log("DDR addr 0x80000002. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[0], ddr_ptr_read_test_2[0]);
    DebugP_log("DDR addr 0x80000003. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[0], ddr_ptr_read_test_3[0]);
    DebugP_log("DDR addr 0x80000004. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[0], ddr_ptr_read_test_4[0]);

    ddr_ptr_write_test_2[0] = pattern_32[1];
    DebugP_log("DDR addr 0x80000001. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[1], ddr_ptr_read_test_1[0]);
    DebugP_log("DDR addr 0x80000002. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[1], ddr_ptr_read_test_2[0]);
    DebugP_log("DDR addr 0x80000003. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[1], ddr_ptr_read_test_3[0]);
    DebugP_log("DDR addr 0x80000004. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[1], ddr_ptr_read_test_4[0]);
    ddr_ptr_write_test_3[0] = pattern_32[2];
    DebugP_log("DDR addr 0x80000001. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[2], ddr_ptr_read_test_1[0]);
    DebugP_log("DDR addr 0x80000002. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[2], ddr_ptr_read_test_2[0]);
    DebugP_log("DDR addr 0x80000003. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[2], ddr_ptr_read_test_3[0]);
    DebugP_log("DDR addr 0x80000004. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[2], ddr_ptr_read_test_4[0]);

    ddr_ptr_write_test_4[0] = pattern_32[3];
    DebugP_log("DDR addr 0x80000001. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[3], ddr_ptr_read_test_1[0]);
    DebugP_log("DDR addr 0x80000002. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[3], ddr_ptr_read_test_2[0]);
    DebugP_log("DDR addr 0x80000003. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[3], ddr_ptr_read_test_3[0]);
    DebugP_log("DDR addr 0x80000004. Write value: 0x%08X, read value: 0x%08X\r\n", pattern_32[3], ddr_ptr_read_test_4[0]);





}

void ddr_ecc_test_main (void *args)
{
    int32_t status;
    uint64_t size = 10000;
    uint32_t startAdd = 0x80000000;

    /* Open drivers to open the UART driver for console */
    Drivers_open ();
    Board_driversOpen ();

    gSecTestPass = FALSE;
    gDedTestPass = FALSE;

/*    status = DDR_secErrTest ();

    if (status == SystemP_SUCCESS)
    {
        status = DDR_dedErrTest ();
    }*/
    while(1)
    {
        status = ddr_read_write_test(size, startAdd);
        //ddr_test();

        if (status == SystemP_SUCCESS)
        {
            DebugP_log ("All tests have passed!!\r\n");
        }
        else
        {
            DebugP_logError ("Some tests have failed\r\n");
        }
    }

    Board_driversClose ();
    Drivers_close ();
}

DDR addr 0x80000C1E failed. Write value: 0x0000, read value: 0x0008
DDR addr 0x8000461E failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x800073DE failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x80002C7E failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x80002F7E failed. Write value: 0x0000, read value: 0x00D9
DDR addr 0x800031FE failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x80007B7E failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x8000537E failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x8000555E failed. Write value: 0x0000, read value: 0x00DF
DDR addr 0x8000759E failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x80007C3E failed. Write value: 0x0000, read value: 0x00DF
DDR addr 0x800086DE failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x80008EFE failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x800012BE failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x8000267E failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x80002B3E failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x80003BDE failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x80006D1E failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x800030DE failed. Write value: 0x00FF, read value: 0x0000
DDR addr 0x8000685E failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x800087DE failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x80000F1E failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x8000145E failed. Write value: 0x0000, read value: 0x00DF
DDR addr 0x80002EFE failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x80002FFE failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x80004B1E failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x80009BDE failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x8000029E failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x80002D3E failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x80004CFE failed. Write value: 0x0000, read value: 0x00FF
DDR addr 0x80002D1E failed. Write value: 0x00AA, read value: 0x0055
DDR addr 0x80007B3E failed. Write value: 0x00AA, read value: 0x0055
DDR read & write completed
ERROR: ddr_ecc_test_main:529: Some tests have failed

Could you please provide us with some suggestions?

Thanks,

Kevin

Kevin,

for tXPR, the formula is the max of 5tCK or tRFCmin+10.  The tool will perform all of the necessary calculations.  You only need to input 5tCK, the tool will determine if 5tCK or tRFCmin+10 is the maximum.  In your case, at 800MHz operation, 

5 * 1.25ns = 6.25ns

tRFCmin+10 = 260+10 = 270ns

So the tool will use tXPR = 270ns

How many boards are you testing?  Do multiple boards show the same error?

Can you try with the following changes:

1. change CWL=9 and retest

2.change frequency = 667MHz and CWL=9 and CL=12, and retest

Regards,

James

Hi James,

Thanks for your suggestion!

Customer has tried two different tests shown below.

Consecutive Test: consecutively write 4096 32bits data and read back to compare

Inconsecutive Test: write 4096 32bits data, and read back the data with the time interval 1us. Which means for each data read back there is a time delay 1us between them.

Now, customer followed your suggestions to conduct the following experiments based on consecutive test and inconsecutive test.

Case 1:  800MHz,  CL=14, CWL=9, tXPR= 5tCK,  tRP=tRCD=13.75ns, consecutive test.

Result: Similar to the problem before, the frequency of having the problem is similar as before. The corresponding DDR address of all the failed position ends with the character "C" in hexadecimal, and all happen in the second Byte.

Sysconfig

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/Case1_5F00_DDR4_2D00_1600_5F00_800MHz_5F00_CL14_5F00_CWL9_5F00_RPRCD1375_5F00_XPR5_5F00_settings_5F00_info.syscfg

Log

Date: 2024-09-25
DDR4-1600_800MHz_CL14_CWL9_RPRCD1375_XPR5
No delay
start addr: 0x80000000
.....................................................................................................................................................................
Fail DDR addr 0x800A677C failed. Write value: 0x55555555, read value: 0x55AA5555
................................................................................................................................................................................
Fail DDR addr 0x801566DC failed. Write value: 0xFFFFFFEA, read value: 0xFF00FFEA
..........
Fail DDR addr 0x80160FFC failed. Write value: 0xFFFFFFAA, read value: 0xFF00FFAA
...............
Fail DDR addr 0x8016FE5C failed. Write value: 0x55555555, read value: 0x55AA5555
......................................................................
Fail DDR addr 0x801B5E3C failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0

Fail DDR addr 0x801B5EDC failed. Write value: 0xFFFFFFF0, read value: 0xFF75FFF0

Fail DDR addr 0x801B753C failed. Write value: 0xFFFFFFF0, read value: 0xFF55FFF0
.....................
Fail DDR addr 0x801CAF1C failed. Write value: 0x55555555, read value: 0x55AA5555
.................
Fail DDR addr 0x801DB75C failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
............................................................
Fail DDR addr 0x80217D5C failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
.............
Fail DDR addr 0x80226C1C failed. Write value: 0x00000001, read value: 0x008A0001
.............
Fail DDR addr 0x8023125C failed. Write value: 0x55555555, read value: 0x55AA5555
......................
Fail DDR addr 0x8024709C failed. Write value: 0x55555555, read value: 0x55AA5555
......
Fail DDR addr 0x8024DF9C failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC

Fail DDR addr 0x8024F39C failed. Write value: 0xFFFFFFFC, read value: 0xFFAAFFFC
..
Fail DDR addr 0x8024FCFC failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
...
Fail DDR addr 0x80252D9C failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8
.......................................
Fail DDR addr 0x8027947C failed. Write value: 0xFFFFFFEA, read value: 0xFF00FFEA
..........................................................................
Fail DDR addr 0x802C377C failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
........................................................................................................................................................................................................................................................................................................
Fail DDR addr 0x803EBFDC failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
..........................
Fail DDR addr 0x8040509C failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
..........................................................
Fail DDR addr 0x8043F1FC failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
............................................................................................
Fail DDR addr 0x8049BD1C failed. Write value: 0xFFFFFFAA, read value: 0xFF00FFAA
....................................
Fail DDR addr 0x804BF13C failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8

Fail DDR addr 0x804BFE5C failed. Write value: 0xFFFFFFF8, read value: 0xFFAAFFF8
..........................................................................................................................................
Fail DDR addr 0x8054975C failed. Write value: 0xFFFFFFFA, read value: 0xFF00FFFA
............................................................
Fail DDR addr 0x8058579C failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8

Fail DDR addr 0x8058739C failed. Write value: 0xFFFFFFF8, read value: 0xFFAAFFF8
.......
Fail DDR addr 0x8058C29C failed. Write value: 0xFFFFFFEA, read value: 0xFF00FFEA

Fail DDR addr 0x8058CADC failed. Write value: 0xFFFFFFEA, read value: 0xFF75FFEA
...............................................................................................................
Fail DDR addr 0x805FB1BC failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
................................................................................
Fail DDR addr 0x8064BF7C failed. Write value: 0xFFFFFFAA, read value: 0xFF00FFAA

Fail DDR addr 0x8064DC9C failed. Write value: 0xFFFFFFAA, read value: 0xFFAAFFAA
............................................................
Fail DDR addr 0x806891BC failed. Write value: 0x00000001, read value: 0x00FF0001
....................................
Fail DDR addr 0x806AB4BC failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
..
Fail DDR addr 0x806AD7FC failed. Write value: 0x55555555, read value: 0x55AA5555
......
Fail DDR addr 0x806B385C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
............
Fail DDR addr 0x806BF3DC failed. Write value: 0xFFFFFFFA, read value: 0xFF00FFFA

Fail DDR addr 0x806BFABC failed. Write value: 0xFFFFFFFA, read value: 0xFFAAFFFA
............................................................................................................................................................................................................................
Fail DDR addr 0x8079BF3C failed. Write value: 0xFFFFFFFA, read value: 0xFF00FFFA
........
Fail DDR addr 0x807A3B7C failed. Write value: 0xFFFFFFFA, read value: 0xFF00FFFA
................................
Fail DDR addr 0x807C3FDC failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
............................................................
Fail DDR addr 0x807FF25C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
..........
Fail DDR addr 0x808093FC failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
.........................................................................................................
Fail DDR addr 0x80872D5C failed. Write value: 0x00000001, read value: 0x00FF0001
...........................
Fail DDR addr 0x8088DCFC failed. Write value: 0xFFFFFFEA, read value: 0xFF00FFEA

Fail DDR addr 0x8088DF5C failed. Write value: 0xFFFFFFEA, read value: 0xFF55FFEA
.......
Fail DDR addr 0x80894C9C failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
.............................
Fail DDR addr 0x808B199C failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
......................................................
Fail DDR addr 0x808E711C failed. Write value: 0x00000001, read value: 0x00FF0001
...................................
Fail DDR addr 0x8090A65C failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
...............................
Fail DDR addr 0x80929FBC failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0

Fail DDR addr 0x8092B0BC failed. Write value: 0xFFFFFFF0, read value: 0xFF55FFF0
................................
Fail DDR addr 0x8094959C failed. Write value: 0x55555555, read value: 0x55AA5555
......................................
Fail DDR addr 0x8096FA5C failed. Write value: 0xFFFFFFAA, read value: 0xFF00FFAA
............................................................................
Fail DDR addr 0x809BB25C failed. Write value: 0xFFFFFFFE, read value: 0xFF55FFFE
..........
Fail DDR addr 0x809C559C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE

Fail DDR addr 0x809C59DC failed. Write value: 0xFFFFFFFE, read value: 0xFF55FFFE
....................
Fail DDR addr 0x809D941C failed. Write value: 0x00000001, read value: 0x00FF0001
....................................
Fail DDR addr 0x809FD05C failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
.................
Fail DDR addr 0x80A0E07C failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8

Fail DDR addr 0x80A0EB7C failed. Write value: 0xFFFFFFF8, read value: 0xFF55FFF8
.............................................................................................................
Fail DDR addr 0x80A7B49C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
...............
Fail DDR addr 0x80A8A91C failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
.
Fail DDR addr 0x80A8B53C failed. Write value: 0xFFFFFFAA, read value: 0xFF00FFAA

Fail DDR addr 0x80A8BEBC failed. Write value: 0xFFFFFFAA, read value: 0xFFAAFFAA
..............................................
Fail DDR addr 0x80AB92FC failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
................................
Fail DDR addr 0x80AD9A7C failed. Write value: 0xFFFFFFEA, read value: 0xFF00FFEA
............
Fail DDR addr 0x80AE57BC failed. Write value: 0x55555555, read value: 0x55AA5555
................................................................
Fail DDR addr 0x80B253BC failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8
..................................................................................................................
Fail DDR addr 0x80B97FFC failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
....................................................................................
Fail DDR addr 0x80BEB35C failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8

Fail DDR addr 0x80BED57C failed. Write value: 0xFFFFFFF8, read value: 0xFF55FFF8
............
Fail DDR addr 0x80BF75FC failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
....
Fail DDR addr 0x80BFB73C failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8
..............................................................................................................................
Fail DDR addr 0x80C7937C failed. Write value: 0xFFFFFFEA, read value: 0xFF00FFEA
............................
Fail DDR addr 0x80C95C5C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
...................................
Fail DDR addr 0x80CB863C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
....................
Fail DDR addr 0x80CCCDFC failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x80CCF99C failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8
................
Fail DDR addr 0x80CDFD1C failed. Write value: 0xFFFFFFEA, read value: 0xFF00FFEA
...................................................................................................................................................................................................................................................................................................................................
Fail DDR addr 0x80E2291C failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
...............................................................
Fail DDR addr 0x80E61F1C failed. Write value: 0x55555555, read value: 0x55AA5555
................................
Fail DDR addr 0x80E8125C failed. Write value: 0xFFFFFFFA, read value: 0xFF00FFFA
..........................................................................................................
Fail DDR addr 0x80EEB4DC failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
.................................................
Fail DDR addr 0x80F1C33C failed. Write value: 0x55555555, read value: 0x55AA5555
.............................
Fail DDR addr 0x80F3983C failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8

Fail DDR addr 0x80F3BA9C failed. Write value: 0xFFFFFFF8, read value: 0xFF55FFF8
..............
Fail DDR addr 0x80F47B9C failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
............
Fail DDR addr 0x80F5365C failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
..................
Fail DDR addr 0x80F65A9C failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
..........................................................................................
Fail DDR addr 0x80FBF93C failed. Write value: 0x55555555, read value: 0x55AA5555
............
Fail DDR addr 0x80FCBBFC failed. Write value: 0xFFFFFFFA, read value: 0xFF00FFFA
......................................................start addr: 0x81000000
........
Fail DDR addr 0x81009CBC failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
..........
Fail DDR addr 0x81013C3C failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
............................................................................................
Fail DDR addr 0x8106F91C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE

Fail DDR addr 0x8107181C failed. Write value: 0xFFFFFFFE, read value: 0xFFF5FFFE
......
Fail DDR addr 0x8107551C failed. Write value: 0xFFFFFFFA, read value: 0xFF00FFFA
......
Fail DDR addr 0x8107B47C failed. Write value: 0xFFFFFFAA, read value: 0xFF00FFAA
..................
Fail DDR addr 0x8108DD9C failed. Write value: 0xFFFFFFFA, read value: 0xFF00FFFA
.............
Fail DDR addr 0x8109A49C failed. Write value: 0x00000001, read value: 0x00FF0001
...................
Fail DDR addr 0x810AD33C failed. Write value: 0xFFFFFFAA, read value: 0xFF00FFAA
................................................
Fail DDR addr 0x810DD83C failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0

Fail DDR addr 0x810DD95C failed. Write value: 0xFFFFFFF0, read value: 0xFF55FFF0
..............................................
Fail DDR addr 0x8110B6FC failed. Write value: 0xFFFFFFFA, read value: 0xFF00FFFA
..................................
Fail DDR addr 0x8112D7BC failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0

Fail DDR addr 0x8112FD7C failed. Write value: 0xFFFFFFF0, read value: 0xFF75FFF0
........................................................................................................................................................................................
Fail DDR addr 0x811E5CFC failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
......................................................
Fail DDR addr 0x8121B7BC failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8
......................................................................
Fail DDR addr 0x8126155C failed. Write value: 0x55555555, read value: 0x55AA5555
..............................................
Fail DDR addr 0x8128F0DC failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8
..........
Fail DDR addr 0x812993DC failed. Write value: 0x00000001, read value: 0x008A0001
..............
Fail DDR addr 0x812A779C failed. Write value: 0x55555555, read value: 0x55AA5555
..........................................................................................................................................................................................................................................
Fail DDR addr 0x8139169C failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8

Fail DDR addr 0x81393ADC failed. Write value: 0xFFFFFFF8, read value: 0xFF75FFF8
........................
Fail DDR addr 0x813A9E9C failed. Write value: 0xFFFFFFFA, read value: 0xFF00FFFA
....................................................................................................
Fail DDR addr 0x8140D03C failed. Write value: 0x55555555, read value: 0x55AA5555
........................................................................................................................
Fail DDR addr 0x814859DC failed. Write value: 0xFFFFFFAA, read value: 0xFF00FFAA

Fail DDR addr 0x8148739C failed. Write value: 0xFFFFFFAA, read value: 0xFF55FFAA

Case 2:  800MHz,  CL=14, CWL=9, tXPR= 5tCK,  tRP=tRCD=17.5ns (recommended by DDR vendor), consecutive test.

Result: Same as case 1.

Sysconfig

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/Case2_5F00_DDR4_2D00_1600_5F00_800MHz_5F00_CL14_5F00_CWL9_5F00_RPRCD175_5F00_XPR5_5F00_settings_5F00_info.syscfg

Log

Date: 2024-09-25
DDR4-1600_800MHz_CL14_CWL9_RPRCD175_XPR5
No delay
start addr: 0x80000000
......
Fail DDR addr 0x800078BC failed. Write value: 0xFFFFFFAA, read value: 0xFF00FFAA
........
Fail DDR addr 0x8000F31C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
............................................................................
Fail DDR addr 0x8005B31C failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0

Fail DDR addr 0x8005B71C failed. Write value: 0xFFFFFFF0, read value: 0xFF55FFF0
............................................................
Fail DDR addr 0x80097E5C failed. Write value: 0xFFFFFFFA, read value: 0xFF00FFFA
........................................................................................................................
Fail DDR addr 0x8010FFBC failed. Write value: 0xFFFFFFFA, read value: 0xFF00FFFA
.........................................................................................................
Fail DDR addr 0x801782DC failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8
.
Fail DDR addr 0x80179A9C failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8
..................................
Fail DDR addr 0x8019B63C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
..................................
Fail DDR addr 0x801BDF7C failed. Write value: 0xFFFFFFAA, read value: 0xFF00FFAA
......................................................................................................................
Fail DDR addr 0x80233B1C failed. Write value: 0x55555555, read value: 0x55AA5555
............
Fail DDR addr 0x8023FFBC failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
..............
Fail DDR addr 0x8024DC9C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
........................................................................................................................................................................
Fail DDR addr 0x802F58FC failed. Write value: 0x55555555, read value: 0x55AA5555
....................................................................................................................................................................................................
Fail DDR addr 0x803B9CBC failed. Write value: 0x55555555, read value: 0x55AA5555
..............................
Fail DDR addr 0x803D70FC failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
....................
Fail DDR addr 0x803EB69C failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
............
Fail DDR addr 0x803F7C9C failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8
....................................
Fail DDR addr 0x8041BBBC failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8
....................................
Fail DDR addr 0x8043F57C failed. Write value: 0xFFFFFFAA, read value: 0xFF00FFAA
.............................
Fail DDR addr 0x8045C3FC failed. Write value: 0x55555555, read value: 0x55AA5555
.........
Fail DDR addr 0x8046591C failed. Write value: 0xFFFFFFEA, read value: 0xFF00FFEA
......................................................................................................................................................................................
Fail DDR addr 0x8051BC3C failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8
........................
Fail DDR addr 0x8053343C failed. Write value: 0x00000001, read value: 0x00FF0001
...........
Fail DDR addr 0x8053E99C failed. Write value: 0xFFFFFFFE, read value: 0xFFAAFFFE
...............................................................
Fail DDR addr 0x8057D3BC failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
......
Fail DDR addr 0x80583C3C failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
..................................................
Fail DDR addr 0x805B52FC failed. Write value: 0x55555555, read value: 0x55AA5555
................
Fail DDR addr 0x805C5DBC failed. Write value: 0x00000001, read value: 0x00FF0001
......................................................................................
Fail DDR addr 0x8061B17C failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
................
Fail DDR addr 0x8062BC9C failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
......
Fail DDR addr 0x80631FBC failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
......................................................................................................................
Fail DDR addr 0x806A777C failed. Write value: 0xFFFFFFFE, read value: 0xFF55FFFE
...........................................................................................................................................................
Fail DDR addr 0x80742BDC failed. Write value: 0xFFFFFFF8, read value: 0xFF00FFF8
..........................
Fail DDR addr 0x8075CB9C failed. Write value: 0xFFFFFFEA, read value: 0xFF00FFEA
............................................................................
Fail DDR addr 0x807A805C failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
.......................................................................................................................................................................
Fail DDR addr 0x8084F91C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
...................................................
Fail DDR addr 0x8088223C failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
...................................................................................................................................................
Fail DDR addr 0x80915B1C failed. Write value: 0xFFFFFFFA, read value: 0xFF00FFFA
................................................................................................................................................................
Fail DDR addr 0x809B5F1C failed. Write value: 0x00000001, read value: 0x00FF0001

Case 3:  800MHz,  CL=14, CWL=11, tXPR= 5tCK,  tRP=tRCD=13.75ns, consecutive test.

Result: Same as case 1.

Sysconfig

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/Case3_5F00_DDR4_2D00_1600_5F00_800MHz_5F00_CL14_5F00_CWL11_5F00_RPRCD1375_5F00_XPR5_5F00_settings_5F00_info.syscfg

Log

Date: 2024-09-25
File: DDR4-1600_800MHz_CL14_CWL11_RPRCD1375_XPR5
Delay: NO
start addr: 0x80000000
...............................
Fail DDR addr 0x8002081C failed. Write value: 0xFFFFFFFE, read value: 0xFF75FFFE
..........
Fail DDR addr 0x8002A4FC failed. Write value: 0x00000001, read value: 0x00AA0001
........
Fail DDR addr 0x8003285C failed. Write value: 0x00000001, read value: 0x00AA0001
................
Fail DDR addr 0x800420DC failed. Write value: 0x00000001, read value: 0x00AA0001
.....
Fail DDR addr 0x800471FC failed. Write value: 0x00000001, read value: 0x00FF0001
.......
Fail DDR addr 0x8004E87C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8004EEBC failed. Write value: 0x00000001, read value: 0x008A0001

Fail DDR addr 0x8004EF5C failed. Write value: 0x00000001, read value: 0x00FF0001
...................
Fail DDR addr 0x80061CBC failed. Write value: 0x00000001, read value: 0x00FF0001
..
Fail DDR addr 0x80063ADC failed. Write value: 0x00000001, read value: 0x00FF0001
..........
Fail DDR addr 0x8006D67C failed. Write value: 0x00000001, read value: 0x00AA0001
.....
Fail DDR addr 0x80072EBC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x80074BFC failed. Write value: 0x00000001, read value: 0x00AA0001
..
Fail DDR addr 0x8007461C failed. Write value: 0x00000001, read value: 0x00DB0001
......
Fail DDR addr 0x8007A05C failed. Write value: 0x00000001, read value: 0x00FF0001
.....................
Fail DDR addr 0x8009109C failed. Write value: 0x00000001, read value: 0x00AA0001
........
Fail DDR addr 0x800974FC failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x800986DC failed. Write value: 0x00000001, read value: 0x00FF0001
..
Fail DDR addr 0x8009C19C failed. Write value: 0x00000001, read value: 0x00AA0001
......
Fail DDR addr 0x800A063C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
.
Fail DDR addr 0x800A133C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x800A173C failed. Write value: 0x00000001, read value: 0x00AA0001
........
Fail DDR addr 0x800A9C3C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x800A9D1C failed. Write value: 0x00000001, read value: 0x00FF0001
........
Fail DDR addr 0x800B113C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x800B131C failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x800B449C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x800B479C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x800B4A3C failed. Write value: 0x00000001, read value: 0x00AA0001
....
Fail DDR addr 0x800B823C failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x800B91BC failed. Write value: 0x00000001, read value: 0x00FF0001
...
Fail DDR addr 0x800BCF1C failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x800BD79C failed. Write value: 0x00000001, read value: 0x00FF0001
..................
Fail DDR addr 0x800CFB9C failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
..........
Fail DDR addr 0x800D9F1C failed. Write value: 0x0000000F, read value: 0x00FF000F

Fail DDR addr 0x800DB7BC failed. Write value: 0x0000000F, read value: 0x00AA000F
.....
Fail DDR addr 0x800DE0DC failed. Write value: 0x00000001, read value: 0x008A0001

Fail DDR addr 0x800DE15C failed. Write value: 0x00000001, read value: 0x00FF0001
..........
Fail DDR addr 0x800E8DDC failed. Write value: 0x00000001, read value: 0x00AA0001
...........
Fail DDR addr 0x800F3BBC failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
...
Fail DDR addr 0x800F6CDC failed. Write value: 0x00000001, read value: 0x00FF0001
....................
Fail DDR addr 0x8010A0BC failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x8010A0DC failed. Write value: 0x00000001, read value: 0x008A0001
...
Fail DDR addr 0x8010D69C failed. Write value: 0x00000001, read value: 0x00FF0001
........
Fail DDR addr 0x80115E9C failed. Write value: 0x00000001, read value: 0x00AA0001
.................
Fail DDR addr 0x8012695C failed. Write value: 0x00000001, read value: 0x00AA0001
..
Fail DDR addr 0x8012843C failed. Write value: 0x00000001, read value: 0x00FF0001
........
Fail DDR addr 0x801300FC failed. Write value: 0x00000001, read value: 0x00FF0001
....
Fail DDR addr 0x801364BC failed. Write value: 0x00000001, read value: 0x008A0001
....................
Fail DDR addr 0x8014863C failed. Write value: 0x00000001, read value: 0x008A0001

Fail DDR addr 0x80148F3C failed. Write value: 0x00000001, read value: 0x00AA0001
.......................
Fail DDR addr 0x8015F57C failed. Write value: 0x00000001, read value: 0x00FF0001
......
Fail DDR addr 0x8016561C failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x801666FC failed. Write value: 0x00000001, read value: 0x00AA0001
.....
Fail DDR addr 0x8016B57C failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x8016E07C failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x8016F53C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
..................................
Fail DDR addr 0x80191E3C failed. Write value: 0x00000001, read value: 0x00AA0001
..................
Fail DDR addr 0x801A3C7C failed. Write value: 0x00000003, read value: 0x00FF0003

Fail DDR addr 0x801A559C failed. Write value: 0x00000003, read value: 0x008A0003
.....
Fail DDR addr 0x801A8F5C failed. Write value: 0x00000001, read value: 0x00AA0001
.....
Fail DDR addr 0x801AF0DC failed. Write value: 0x00000001, read value: 0x00AA0001
.......
Fail DDR addr 0x801B403C failed. Write value: 0x00000001, read value: 0x00FF0001
.......
Fail DDR addr 0x801BD07C failed. Write value: 0x00000001, read value: 0x00AA0001
..........
Fail DDR addr 0x801C529C failed. Write value: 0x00000001, read value: 0x00FF0001
...........
Fail DDR addr 0x801D0FFC failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x801D1B3C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x801D1D1C failed. Write value: 0x00000001, read value: 0x00DF0001
..............
Fail DDR addr 0x801DF2FC failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x801E29DC failed. Write value: 0x00000001, read value: 0x00FF0001
....
Fail DDR addr 0x801E6C1C failed. Write value: 0x00000015, read value: 0x00FF0015
.....
Fail DDR addr 0x801EB17C failed. Write value: 0x00000001, read value: 0x00FF0001
......
Fail DDR addr 0x801F165C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x801F18DC failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x801F209C failed. Write value: 0x00000001, read value: 0x00AA0001
...........
Fail DDR addr 0x801FD25C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x801FDCBC failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x801FDF7C failed. Write value: 0x00000001, read value: 0x00AA0001
..
Fail DDR addr 0x801FF21C failed. Write value: 0x00000001, read value: 0x000A0001
...............
Fail DDR addr 0x8020EFDC failed. Write value: 0x00000001, read value: 0x00AA0001
.......................
Fail DDR addr 0x80225A9C failed. Write value: 0x00000003, read value: 0x00FF0003
..
Fail DDR addr 0x802272BC failed. Write value: 0x00000001, read value: 0x00FF0001
...........
Fail DDR addr 0x8023287C failed. Write value: 0x00000001, read value: 0x00AA0001
.......
Fail DDR addr 0x8023933C failed. Write value: 0x00000001, read value: 0x00AA0001
...........
Fail DDR addr 0x8024483C failed. Write value: 0xFFFFFFFE, read value: 0xFF75FFFE
.............
Fail DDR addr 0x80251BBC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x802539BC failed. Write value: 0x00000001, read value: 0x008A0001
.............
Fail DDR addr 0x8025EBBC failed. Write value: 0x00000001, read value: 0x00FF0001
..........
Fail DDR addr 0x802689FC failed. Write value: 0x00000001, read value: 0x00AA0001
....
Fail DDR addr 0x8026C0FC failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x8026F2FC failed. Write value: 0x00000001, read value: 0x00AA0001
.........
Fail DDR addr 0x8027857C failed. Write value: 0x00000001, read value: 0x00AA0001
..
Fail DDR addr 0x8027AEBC failed. Write value: 0x00000001, read value: 0x00AA0001
.......
Fail DDR addr 0x80281D1C failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x8028419C failed. Write value: 0x00000001, read value: 0x00AA0001
....
Fail DDR addr 0x8028809C failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x802893FC failed. Write value: 0x00000001, read value: 0x00FF0001
.....
Fail DDR addr 0x8028EADC failed. Write value: 0x00000001, read value: 0x00FF0001
...
Fail DDR addr 0x802912DC failed. Write value: 0x00000001, read value: 0x00AA0001
.....
Fail DDR addr 0x8029655C failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x802994FC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8029981C failed. Write value: 0x00000001, read value: 0x00DB0001

Fail DDR addr 0x8029985C failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x8029CDFC failed. Write value: 0x00000001, read value: 0x00FF0001
..
Fail DDR addr 0x8029E73C failed. Write value: 0x00000005, read value: 0x00FF0005
.
Fail DDR addr 0x8029FE3C failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
....
Fail DDR addr 0x802A37DC failed. Write value: 0x00000001, read value: 0x00AA0001
..
Fail DDR addr 0x802A543C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x802A553C failed. Write value: 0x00000001, read value: 0x00AA0001
.....
Fail DDR addr 0x802AAF1C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x802ACC1C failed. Write value: 0x00000001, read value: 0x000A0001
..
Fail DDR addr 0x802ACD3C failed. Write value: 0x00000003, read value: 0x00FF0003
..........
Fail DDR addr 0x802B6C7C failed. Write value: 0x00000001, read value: 0x00AA0001
....
Fail DDR addr 0x802BAB3C failed. Write value: 0x00000001, read value: 0x00FF0001
..
Fail DDR addr 0x802BCBFC failed. Write value: 0x00000001, read value: 0x008A0001
.............
Fail DDR addr 0x802C945C failed. Write value: 0x00000001, read value: 0x00AA0001
.....
Fail DDR addr 0x802CE09C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x802CE2BC failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x802D317C failed. Write value: 0xFFFFFFFE, read value: 0xFF55FFFE
.....
Fail DDR addr 0x802D6C9C failed. Write value: 0x00000001, read value: 0x00FF0001
......
Fail DDR addr 0x802DC17C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x802DC2BC failed. Write value: 0x00000001, read value: 0x00FF0001
...........
Fail DDR addr 0x802E7DBC failed. Write value: 0x00000003, read value: 0x00FF0003
........
Fail DDR addr 0x802EFA3C failed. Write value: 0x00000003, read value: 0x00FF0003

Fail DDR addr 0x802EFC7C failed. Write value: 0x00000003, read value: 0x00FF0003
........................
Fail DDR addr 0x8030747C failed. Write value: 0x00000001, read value: 0x00FF0001
...
Fail DDR addr 0x8030A97C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x8030A99C failed. Write value: 0x00000001, read value: 0x008A0001
.......................................
Fail DDR addr 0x803319DC failed. Write value: 0x00000001, read value: 0x00AA0001
.............
Fail DDR addr 0x8033E8BC failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x803410DC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x80341FDC failed. Write value: 0x00000001, read value: 0x00AA0001
............
Fail DDR addr 0x8034DC5C failed. Write value: 0x00000003, read value: 0x00FF0003
....................
Fail DDR addr 0x80361ABC failed. Write value: 0x00000001, read value: 0x00FF0001
...
Fail DDR addr 0x80364F3C failed. Write value: 0x00000001, read value: 0x00AA0001
......
Fail DDR addr 0x8036A1BC failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x8036BC1C failed. Write value: 0x00000001, read value: 0x001B0001
.
Fail DDR addr 0x8036C71C failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x8036DD7C failed. Write value: 0x00000001, read value: 0x00AA0001
...............
Fail DDR addr 0x8037CC3C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x8037CF9C failed. Write value: 0x00000001, read value: 0x00AA0001
.....
Fail DDR addr 0x8038169C failed. Write value: 0x00000001, read value: 0x00FF0001
....
Fail DDR addr 0x803850BC failed. Write value: 0x00000003, read value: 0x00FF0003
...
Fail DDR addr 0x803888DC failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x8038AA3C failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x8038B07C failed. Write value: 0x00000001, read value: 0x00AA0001
...........
Fail DDR addr 0x80394C7C failed. Write value: 0x00000001, read value: 0x00AA0001
..
Fail DDR addr 0x80396B9C failed. Write value: 0x00000001, read value: 0x00FF0001
........
Fail DDR addr 0x8039EB1C failed. Write value: 0x00000001, read value: 0x00AA0001
.......
Fail DDR addr 0x803A5ABC failed. Write value: 0x00000001, read value: 0x00FF0001
.....
Fail DDR addr 0x803AA03C failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x803AB4BC failed. Write value: 0x00000003, read value: 0x00FF0003

Fail DDR addr 0x803ABD1C failed. Write value: 0x00000003, read value: 0x00AA0003
.
Fail DDR addr 0x803ACABC failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x803AF7BC failed. Write value: 0x00000001, read value: 0x00FF0001
............
Fail DDR addr 0x803BBF5C failed. Write value: 0x00000001, read value: 0x00FF0001
........
Fail DDR addr 0x803C519C failed. Write value: 0x00000001, read value: 0x00AA0001
..
Fail DDR addr 0x803C52FC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x803C5ADC failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x803C5EDC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x803C5FBC failed. Write value: 0x00000001, read value: 0x00FF0001
......
Fail DDR addr 0x803CBADC failed. Write value: 0x00000001, read value: 0x00AA0001
....
Fail DDR addr 0x803CF17C failed. Write value: 0x00000001, read value: 0x00FF0001
..................................
Fail DDR addr 0x803F121C failed. Write value: 0x00000001, read value: 0x00FF0001
.........................
Fail DDR addr 0x8040A1BC failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x8040BADC failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x8040E2BC failed. Write value: 0x00000001, read value: 0x00FF0001
.........
Fail DDR addr 0x8041777C failed. Write value: 0x00000001, read value: 0x00AA0001
.........
Fail DDR addr 0x804206DC failed. Write value: 0x00000055, read value: 0x00FF0055
.......
Fail DDR addr 0x8042703C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x804272BC failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x80427BBC failed. Write value: 0x00000001, read value: 0x00AA0001
......
Fail DDR addr 0x8042D93C failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x8042E39C failed. Write value: 0x00000001, read value: 0x00AA0001
.......
Fail DDR addr 0x8043577C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
............
Fail DDR addr 0x8044143C failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x8044407C failed. Write value: 0xFFFFFFFE, read value: 0xFF75FFFE
......................
Fail DDR addr 0x8045AE1C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8045AF3C failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x8045D17C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8045D8FC failed. Write value: 0x00000001, read value: 0x00AA0001
.....
Fail DDR addr 0x8046233C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x80462A9C failed. Write value: 0x00000001, read value: 0x00AA0001
..
Fail DDR addr 0x8046473C failed. Write value: 0x00000001, read value: 0x00AA0001
......
Fail DDR addr 0x8046A93C failed. Write value: 0x00000001, read value: 0x00FF0001
....
Fail DDR addr 0x8046E7BC failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x8046E8FC failed. Write value: 0x00000001, read value: 0x00AA0001
........
Fail DDR addr 0x8047625C failed. Write value: 0x00000001, read value: 0x00FF0001
.......
Fail DDR addr 0x8047D85C failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x8047EEBC failed. Write value: 0x00000001, read value: 0x00AA0001
.....................
Fail DDR addr 0x8049379C failed. Write value: 0x00000001, read value: 0x00FF0001
..........
Fail DDR addr 0x8049F27C failed. Write value: 0x00000001, read value: 0x00AA0001
.....
Fail DDR addr 0x804A2C9C failed. Write value: 0x00000001, read value: 0x00FF0001
.....
Fail DDR addr 0x804A713C failed. Write value: 0x00000001, read value: 0x00AA0001
........
Fail DDR addr 0x804AFCBC failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x804B003C failed. Write value: 0x00000001, read value: 0x00FF0001
........
Fail DDR addr 0x804B87FC failed. Write value: 0x00000001, read value: 0x00AA0001
.......
Fail DDR addr 0x804BF45C failed. Write value: 0x00000001, read value: 0x00FF0001
......
Fail DDR addr 0x804C575C failed. Write value: 0x00000001, read value: 0x00FF0001
.........
Fail DDR addr 0x804CE59C failed. Write value: 0x00000003, read value: 0x00FF0003
...............
Fail DDR addr 0x804DD5BC failed. Write value: 0x00000001, read value: 0x00AA0001
....
Fail DDR addr 0x804E187C failed. Write value: 0x00000001, read value: 0x00FF0001
..
Fail DDR addr 0x804E3AFC failed. Write value: 0x00000007, read value: 0x00FF0007
.......
Fail DDR addr 0x804EA6BC failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
.....
Fail DDR addr 0x804EFA9C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
.......
Fail DDR addr 0x804F6B7C failed. Write value: 0x00000001, read value: 0x008A0001

Fail DDR addr 0x804F6C7C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x804F6CDC failed. Write value: 0x00000001, read value: 0x00AA0001
......
Fail DDR addr 0x804FEFDC failed. Write value: 0x00000001, read value: 0x00AA0001
......................
Fail DDR addr 0x8051225C failed. Write value: 0x00000001, read value: 0x00FF0001
.............
Fail DDR addr 0x8051F5FC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8051F9BC failed. Write value: 0x00000001, read value: 0x00FF0001
..................
Fail DDR addr 0x8053113C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x805313FC failed. Write value: 0x00000001, read value: 0x00FF0001
......
Fail DDR addr 0x805375DC failed. Write value: 0xFFFFFFFC, read value: 0xFF00FFFC
.....
Fail DDR addr 0x8053CA9C failed. Write value: 0x00000001, read value: 0x00AA0001
..........
Fail DDR addr 0x80546CDC failed. Write value: 0x00000001, read value: 0x00AA0001
.........
Fail DDR addr 0x8054F75C failed. Write value: 0x00000007, read value: 0x00FF0007

Fail DDR addr 0x8054FB9C failed. Write value: 0x00000007, read value: 0x00AA0007
.........
Fail DDR addr 0x805587FC failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x80558C1C failed. Write value: 0x00000001, read value: 0x000A0001
..
Fail DDR addr 0x8055ABBC failed. Write value: 0x00000001, read value: 0x00AA0001
................
Fail DDR addr 0x8056AEDC failed. Write value: 0x00000001, read value: 0x00FF0001
..........
Fail DDR addr 0x8057493C failed. Write value: 0x00000001, read value: 0x00FF0001
.............
Fail DDR addr 0x805813DC failed. Write value: 0x00000007, read value: 0x00FF0007
..........
Fail DDR addr 0x8058B89C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
..
Fail DDR addr 0x8058F17C failed. Write value: 0x00000001, read value: 0x00FF0001
.....
Fail DDR addr 0x805926FC failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x8059273C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x805929DC failed. Write value: 0x00000001, read value: 0x00FF0001
.................
Fail DDR addr 0x805A367C failed. Write value: 0x00000001, read value: 0x00FF0001
.....
Fail DDR addr 0x805A809C failed. Write value: 0x00000001, read value: 0x00FF0001
.....
Fail DDR addr 0x805AD41C failed. Write value: 0x00000001, read value: 0x00AA0001
........
Fail DDR addr 0x805B533C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x805B5CFC failed. Write value: 0x00000001, read value: 0x00AA0001
......
Fail DDR addr 0x805BBEDC failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x805BC4DC failed. Write value: 0x00000001, read value: 0x00AA0001
....
Fail DDR addr 0x805C043C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x805C079C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x805C089C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x805C0CFC failed. Write value: 0x00000001, read value: 0x00AA0001
.......................
Fail DDR addr 0x805D737C failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x805D813C failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x805DB0BC failed. Write value: 0x00000001, read value: 0x00FF0001
........
Fail DDR addr 0x805E367C failed. Write value: 0x00000003, read value: 0x00FF0003
...........
Fail DDR addr 0x805EE85C failed. Write value: 0x00000001, read value: 0x00AA0001
..............
Fail DDR addr 0x805FC03C failed. Write value: 0x00000001, read value: 0x00FF0001
..........
Fail DDR addr 0x806061BC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x806062FC failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x8060945C failed. Write value: 0x00000001, read value: 0x00FF0001
..........................
Fail DDR addr 0x80623E1C failed. Write value: 0x00000003, read value: 0x00FF0003

Fail DDR addr 0x80623FDC failed. Write value: 0x00000003, read value: 0x00FF0003
.
Fail DDR addr 0x80624A9C failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x8062559C failed. Write value: 0x00000001, read value: 0x00FF0001
................
Fail DDR addr 0x8063503C failed. Write value: 0x00000001, read value: 0x00AA0001
..
Fail DDR addr 0x806373BC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8063775C failed. Write value: 0x00000001, read value: 0x00AA0001
...............
Fail DDR addr 0x806461FC failed. Write value: 0x00000001, read value: 0x00FF0001
................
Fail DDR addr 0x8065617C failed. Write value: 0x00000001, read value: 0x00AA0001
.....
Fail DDR addr 0x8065B2DC failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x8065BAFC failed. Write value: 0x00000001, read value: 0x00AA0001
........
Fail DDR addr 0x806632DC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x80663EBC failed. Write value: 0x00000001, read value: 0x00AA0001
...........
Fail DDR addr 0x8066E8FC failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x8066ED7C failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x80671B3C failed. Write value: 0x00000001, read value: 0x00AA0001
.............
Fail DDR addr 0x8067E0BC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x806800BC failed. Write value: 0x00000001, read value: 0x00AA0001
..
Fail DDR addr 0x8068083C failed. Write value: 0x00000001, read value: 0x00AA0001
.....
Fail DDR addr 0x8068537C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x806855DC failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x80685B9C failed. Write value: 0x00000001, read value: 0x00FF0001
........................
Fail DDR addr 0x8069D7FC failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x8069E8FC failed. Write value: 0x00000001, read value: 0x00FF0001
...
Fail DDR addr 0x806A371C failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x806A4B1C failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x806A717C failed. Write value: 0x00000001, read value: 0x00AA0001
....
Fail DDR addr 0x806A97FC failed. Write value: 0x00000001, read value: 0x00FF0001
..........
Fail DDR addr 0x806B36DC failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x806B3C5C failed. Write value: 0x00000001, read value: 0x00AA0001
...........
Fail DDR addr 0x806BEE1C failed. Write value: 0x00000001, read value: 0x00FF0001
.......
Fail DDR addr 0x806C50DC failed. Write value: 0x00000001, read value: 0x00FF0001
..
Fail DDR addr 0x806C775C failed. Write value: 0x00000001, read value: 0x00AA0001
......
Fail DDR addr 0x806CD7DC failed. Write value: 0x00000001, read value: 0x00AA0001
............
Fail DDR addr 0x806D917C failed. Write value: 0x00000003, read value: 0x00FF0003
.
Fail DDR addr 0x806DA8FC failed. Write value: 0x00000001, read value: 0x00AA0001
......
Fail DDR addr 0x806E073C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x806E08FC failed. Write value: 0x00000001, read value: 0x00080001
...........
Fail DDR addr 0x806EB4FC failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x806EE05C failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x806EF15C failed. Write value: 0x00000001, read value: 0x00FF0001
....................
Fail DDR addr 0x80703CBC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x80703D5C failed. Write value: 0x00000001, read value: 0x00AA0001
..........
Fail DDR addr 0x8070D27C failed. Write value: 0x00000001, read value: 0x00FF0001
..................
Fail DDR addr 0x8071F2FC failed. Write value: 0x00000001, read value: 0x00AA0001
..
Fail DDR addr 0x8072185C failed. Write value: 0x00000003, read value: 0x00FF0003
........
Fail DDR addr 0x807290BC failed. Write value: 0x00000001, read value: 0x00FF0001
..
Fail DDR addr 0x8072B6BC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8072B53C failed. Write value: 0xFFFFFFFE, read value: 0xFF55FFFE
.....
Fail DDR addr 0x80730EDC failed. Write value: 0x00000001, read value: 0x00AA0001
....
Fail DDR addr 0x80734F5C failed. Write value: 0x00000001, read value: 0x00FF0001
......
Fail DDR addr 0x8073C1FC failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x8073B3BC failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x8073BCBC failed. Write value: 0x00000001, read value: 0x008A0001
..
Fail DDR addr 0x8073D65C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8073DC1C failed. Write value: 0x00000001, read value: 0x00AA0001
......
Fail DDR addr 0x807434FC failed. Write value: 0x00000003, read value: 0x00FF0003
....
Fail DDR addr 0x80747D3C failed. Write value: 0x00000001, read value: 0x00AA0001
.............
Fail DDR addr 0x8075429C failed. Write value: 0x00000001, read value: 0x00FF0001
.........
Fail DDR addr 0x8075D13C failed. Write value: 0x00000001, read value: 0x00FF0001
............
Fail DDR addr 0x8076989C failed. Write value: 0x00000003, read value: 0x00FF0003

Fail DDR addr 0x80769E1C failed. Write value: 0x00000003, read value: 0x00FF0003
....
Fail DDR addr 0x8076D61C failed. Write value: 0x00000007, read value: 0x00DF0007
.......
Fail DDR addr 0x80774EDC failed. Write value: 0x00000001, read value: 0x00FF0001
..........
Fail DDR addr 0x8077ED3C failed. Write value: 0x00000003, read value: 0x00FF0003
..
Fail DDR addr 0x807805FC failed. Write value: 0x00000001, read value: 0x00FF0001
........
Fail DDR addr 0x8078867C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8078877C failed. Write value: 0x00000001, read value: 0x00FF0001
................
Fail DDR addr 0x8079ABDC failed. Write value: 0x00000001, read value: 0x00AA0001
......................................
Fail DDR addr 0x807C091C failed. Write value: 0x00000001, read value: 0x00AA0001
........
Fail DDR addr 0x807C6F9C failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x807C7D7C failed. Write value: 0x00000001, read value: 0x00FF0001
..
Fail DDR addr 0x807C9C3C failed. Write value: 0x00000001, read value: 0x00AA0001
.............
Fail DDR addr 0x807D6CDC failed. Write value: 0x00000001, read value: 0x008A0001
...
Fail DDR addr 0x807D97FC failed. Write value: 0x00000001, read value: 0x00AA0001
.......
Fail DDR addr 0x807E0E9C failed. Write value: 0x00000001, read value: 0x00AA0001
.............
Fail DDR addr 0x807EDE1C failed. Write value: 0x00000001, read value: 0x00DB0001
....
Fail DDR addr 0x807F159C failed. Write value: 0x00000001, read value: 0x00FF0001
....
Fail DDR addr 0x807F5ABC failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x807F6BDC failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x807F9F3C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x807FB1DC failed. Write value: 0x00000001, read value: 0x00AA0001
......
Fail DDR addr 0x807FFE1C failed. Write value: 0x00000001, read value: 0x00DB0001

Fail DDR addr 0x80801C9C failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x80802EBC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x80802EDC failed. Write value: 0x00000001, read value: 0x00DF0001
....
Fail DDR addr 0x8080665C failed. Write value: 0x00000001, read value: 0x00FF0001
......
Fail DDR addr 0x8080CA9C failed. Write value: 0x00000001, read value: 0x00AA0001
.............
Fail DDR addr 0x8081969C failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x8081C4FC failed. Write value: 0x00000007, read value: 0x00FF0007
..........
Fail DDR addr 0x8082631C failed. Write value: 0x00000001, read value: 0x00FF0001
.....
Fail DDR addr 0x8082BCFC failed. Write value: 0x00000003, read value: 0x00FF0003
.........
Fail DDR addr 0x8083485C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x808348FC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8083639C failed. Write value: 0x00000001, read value: 0x00AA0001
....
Fail DDR addr 0x80838CDC failed. Write value: 0x00000001, read value: 0x00AA0001
.......
Fail DDR addr 0x8083F2BC failed. Write value: 0x00000001, read value: 0x00FF0001
..
Fail DDR addr 0x80841DBC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x80841E1C failed. Write value: 0x00000001, read value: 0x008A0001
..
Fail DDR addr 0x8084347C failed. Write value: 0x00000001, read value: 0x00FF0001
.....
Fail DDR addr 0x808485DC failed. Write value: 0x00000001, read value: 0x00FF0001
......................
Fail DDR addr 0x8085E29C failed. Write value: 0x00000001, read value: 0x00FF0001
..............
Fail DDR addr 0x8086CEFC failed. Write value: 0x00000001, read value: 0x00AA0001
...............
Fail DDR addr 0x8087D33C failed. Write value: 0x00000001, read value: 0x00AA0001
................
Fail DDR addr 0x8088B81C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8088BFBC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8088BFFC failed. Write value: 0x00000001, read value: 0x00FF0001
...........
Fail DDR addr 0x8089625C failed. Write value: 0x00000001, read value: 0x00AA0001
......
Fail DDR addr 0x8089C31C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x8089CEBC failed. Write value: 0x00000001, read value: 0x00AA0001
.........
Fail DDR addr 0x808A5ABC failed. Write value: 0x00000001, read value: 0x00FF0001
..
Fail DDR addr 0x808A75FC failed. Write value: 0x00000001, read value: 0x00FF0001
..
Fail DDR addr 0x808A965C failed. Write value: 0x00000001, read value: 0x00AA0001
.....
Fail DDR addr 0x808AE33C failed. Write value: 0x00000001, read value: 0x00FF0001
..........
Fail DDR addr 0x808B8DFC failed. Write value: 0x00000001, read value: 0x00AA0001
..........
Fail DDR addr 0x808C287C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x808C293C failed. Write value: 0x00000001, read value: 0x00FF0001
........................
Fail DDR addr 0x808DAA3C failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x808DBB1C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
..
Fail DDR addr 0x808DD81C failed. Write value: 0x00000001, read value: 0x008A0001
.....
Fail DDR addr 0x808E217C failed. Write value: 0x00000001, read value: 0x00AA0001
..........
Fail DDR addr 0x808EC7BC failed. Write value: 0x00000001, read value: 0x00AA0001
.........
Fail DDR addr 0x808F43FC failed. Write value: 0x00000001, read value: 0x00AA0001
............................
Fail DDR addr 0x80911C7C failed. Write value: 0x00000001, read value: 0x00AA0001
............................
Fail DDR addr 0x8092DD1C failed. Write value: 0x00000003, read value: 0x00FF0003
....................
Fail DDR addr 0x8094197C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
..
Fail DDR addr 0x8094377C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x8094389C failed. Write value: 0x00000001, read value: 0x00FF0001
........
Fail DDR addr 0x8094BE1C failed. Write value: 0x00000001, read value: 0x00AA0001
............................
Fail DDR addr 0x80967F5C failed. Write value: 0x00000001, read value: 0x00FF0001
.......
Fail DDR addr 0x8096E9FC failed. Write value: 0x00000001, read value: 0x00FF0001
..........
Fail DDR addr 0x80978B5C failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x8097B67C failed. Write value: 0x00000003, read value: 0x00FF0003

Fail DDR addr 0x8097BC7C failed. Write value: 0x00000003, read value: 0x00FF0003
.
Fail DDR addr 0x8097CC3C failed. Write value: 0x00000001, read value: 0x00FF0001
.....
Fail DDR addr 0x80981CDC failed. Write value: 0x00000001, read value: 0x00FF0001
....
Fail DDR addr 0x8098579C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x8098595C failed. Write value: 0x00000001, read value: 0x008A0001
.......
Fail DDR addr 0x8098C09C failed. Write value: 0x00000001, read value: 0x00AA0001
......
Fail DDR addr 0x809927FC failed. Write value: 0x00000001, read value: 0x00FF0001
...........
Fail DDR addr 0x8099D8DC failed. Write value: 0x00000001, read value: 0x00AA0001
........
Fail DDR addr 0x809A547C failed. Write value: 0x00000001, read value: 0x00AA0001
.........
Fail DDR addr 0x809AE5BC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x809AEDFC failed. Write value: 0x00000001, read value: 0x00AA0001
..............................
Fail DDR addr 0x809CCE1C failed. Write value: 0x00000001, read value: 0x00FF0001
....................
Fail DDR addr 0x809E05DC failed. Write value: 0x00000001, read value: 0x00AA0001
..............
Fail DDR addr 0x809EE97C failed. Write value: 0x00000005, read value: 0x00FF0005
......
Fail DDR addr 0x809F407C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x809F465C failed. Write value: 0x00000001, read value: 0x00FF0001
.........
Fail DDR addr 0x809FD39C failed. Write value: 0x00000001, read value: 0x00FF0001
.........................
Fail DDR addr 0x80A16B5C failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x80A1795C failed. Write value: 0x00000003, read value: 0x00FF0003

Fail DDR addr 0x80A17DDC failed. Write value: 0x00000003, read value: 0x00AA0003
.
Fail DDR addr 0x80A1A1FC failed. Write value: 0x00000001, read value: 0x00AA0001
........
Fail DDR addr 0x80A20A5C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x80A20BFC failed. Write value: 0x00000001, read value: 0x00AA0001
........
Fail DDR addr 0x80A28E9C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x80A28EBC failed. Write value: 0x00000001, read value: 0x00080001
.
Fail DDR addr 0x80A29B3C failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x80A2A8BC failed. Write value: 0x00000001, read value: 0x00FF0001
......
Fail DDR addr 0x80A30DFC failed. Write value: 0x00000001, read value: 0x00AA0001
.....................
Fail DDR addr 0x80A4553C failed. Write value: 0x00000001, read value: 0x00AA0001
....
Fail DDR addr 0x80A496BC failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x80A4CA7C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x80A4CFBC failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x80A4DB9C failed. Write value: 0x00000001, read value: 0x00AA0001
..........
Fail DDR addr 0x80A5777C failed. Write value: 0x00000001, read value: 0x00AA0001
..........
Fail DDR addr 0x80A61E3C failed. Write value: 0x00000001, read value: 0x00FF0001
....
Fail DDR addr 0x80A653BC failed. Write value: 0x00000001, read value: 0x00AA0001
......
Fail DDR addr 0x80A6B2DC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x80A6BD3C failed. Write value: 0x00000001, read value: 0x00AA0001
....
Fail DDR addr 0x80A713FC failed. Write value: 0x00000001, read value: 0x008A0001
..
Fail DDR addr 0x80A7149C failed. Write value: 0x00000001, read value: 0x00FF0001
..
Fail DDR addr 0x80A7313C failed. Write value: 0x00000001, read value: 0x00FF0001
........
Fail DDR addr 0x80A7BEBC failed. Write value: 0x00000001, read value: 0x00FF0001
....
Fail DDR addr 0x80A7F8DC failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x80A80D1C failed. Write value: 0x00000001, read value: 0x00FF0001
..................................
Fail DDR addr 0x80AA20FC failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x80AA39BC failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
..............
Fail DDR addr 0x80AB1A7C failed. Write value: 0x00000001, read value: 0x00FF0001
.........
Fail DDR addr 0x80ABA25C failed. Write value: 0x00000001, read value: 0x00FF0001
.........................
Fail DDR addr 0x80AD309C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x80AD3CDC failed. Write value: 0x00000001, read value: 0x00AA0001
...................
Fail DDR addr 0x80AE80FC failed. Write value: 0x00000001, read value: 0x00AA0001
....
Fail DDR addr 0x80AEA9BC failed. Write value: 0x00000001, read value: 0x00AA0001
....
Fail DDR addr 0x80AEE2DC failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x80AEF69C failed. Write value: 0x00000001, read value: 0x00AA0001
........
Fail DDR addr 0x80AF7B1C failed. Write value: 0x00000001, read value: 0x00FF0001
..
Fail DDR addr 0x80AF9B5C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x80AF9DFC failed. Write value: 0x00000001, read value: 0x00FF0001

Case 4:  667MHz,  CL=12, CWL=9, tXPR= 5tCK,  tRP=tRCD=13.75ns, consecutive test.

Result: Same as case 1.

Sysconfig

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/Case4_5F00_DDR4_2D00_1600_5F00_667MHz_5F00_CL12_5F00_CWL9_5F00_RPRCD1375_5F00_settings_5F00_info.syscfg

Log

Date: 2024-09-25
File: DDR4-1600_667MHz_CL12_CWL9_RPRCD1375
Delay: NO
start addr: 0x80000000
.........
Fail DDR addr 0x8000AE7C failed. Write value: 0x00000001, read value: 0x00AA0001
.......................
Fail DDR addr 0x8002127C failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x80022ABC failed. Write value: 0x00000001, read value: 0x00FF0001
.........
Fail DDR addr 0x8002BD9C failed. Write value: 0x00000003, read value: 0x00FF0003
.....
Fail DDR addr 0x800306DC failed. Write value: 0x00000001, read value: 0x00AA0001
......
Fail DDR addr 0x80036A9C failed. Write value: 0x00000001, read value: 0x00FF0001
.........................
Fail DDR addr 0x8004F0DC failed. Write value: 0x00000003, read value: 0x00FF0003
....
Fail DDR addr 0x8005315C failed. Write value: 0x00000001, read value: 0x00FF0001
.....
Fail DDR addr 0x80058DDC failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x8005DC1C failed. Write value: 0x00000001, read value: 0x00080001
.
Fail DDR addr 0x8005C0FC failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x8005D87C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x8005F8DC failed. Write value: 0x00000001, read value: 0x00AA0001
..
Fail DDR addr 0x8005FD3C failed. Write value: 0x00000001, read value: 0x00AA0001
.....
Fail DDR addr 0x80064A7C failed. Write value: 0x00000001, read value: 0x00AA0001
....
Fail DDR addr 0x80068DFC failed. Write value: 0x00000001, read value: 0x00FF0001
.....
Fail DDR addr 0x8006F2DC failed. Write value: 0x00000001, read value: 0x00AA0001
..
Fail DDR addr 0x8006F59C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x8006FCDC failed. Write value: 0x00000001, read value: 0x00AA0001
......
Fail DDR addr 0x80075BBC failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x8007851C failed. Write value: 0x00000001, read value: 0x00AA0001
.....
Fail DDR addr 0x8007D07C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x8007D65C failed. Write value: 0x00000001, read value: 0x00FF0001
..........
Fail DDR addr 0x8008735C failed. Write value: 0x00000003, read value: 0x00FF0003
.
Fail DDR addr 0x800885FC failed. Write value: 0x00000007, read value: 0x00FF0007
........
Fail DDR addr 0x80090FFC failed. Write value: 0x00000001, read value: 0x00FF0001
........
Fail DDR addr 0x80098D5C failed. Write value: 0x00000001, read value: 0x00AA0001
...........
Fail DDR addr 0x800A3E5C failed. Write value: 0x00000001, read value: 0x00FF0001

Case 5:  667MHz,  CL=12, CWL=9, tXPR= 5tCK,  tRP=tRCD=17.5ns (suggested by DDR vendor), consecutive test.

Result: Same as case 1.

Sysconfig

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/Case5_5F00_DDR4_2D00_1600_5F00_667MHz_5F00_CL12_5F00_CWL9_5F00_RPRCD175_5F00_settings_5F00_info.syscfg

Log

Date: 2024-09-25
File: DDR4-1600_667MHz_CL12_CWL9_RPRCD175
Delay: NO
start addr: 0x80000000
....................
Fail DDR addr 0x800151DC failed. Write value: 0x00000001, read value: 0x00FF0001
.............
Fail DDR addr 0x80022C7C failed. Write value: 0x00000001, read value: 0x00FF0001
..........................
Fail DDR addr 0x8003C3BC failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x8003D9BC failed. Write value: 0x00000001, read value: 0x00AA0001
....
Fail DDR addr 0x80041B5C failed. Write value: 0x00000001, read value: 0x00FF0001
.............
Fail DDR addr 0x8004ECFC failed. Write value: 0x00000007, read value: 0x00FF0007
.........
Fail DDR addr 0x8005753C failed. Write value: 0x00000001, read value: 0x00AA0001
....
Fail DDR addr 0x8005BDBC failed. Write value: 0x00000001, read value: 0x00AA0001
......
Fail DDR addr 0x8006137C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x80061EDC failed. Write value: 0x00000001, read value: 0x00AA0001
......
Fail DDR addr 0x800675FC failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x80068C7C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x8006ADDC failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x8006AEFC failed. Write value: 0x00000001, read value: 0x00AA0001
..
Fail DDR addr 0x8006AE7C failed. Write value: 0x00000001, read value: 0x00FF0001
................
Fail DDR addr 0x8007A77C failed. Write value: 0x00000001, read value: 0x00FF0001
..
Fail DDR addr 0x8007CDDC failed. Write value: 0x00000001, read value: 0x00AA0001
....
Fail DDR addr 0x8008093C failed. Write value: 0x00000001, read value: 0x00AA0001
.....
Fail DDR addr 0x80085AFC failed. Write value: 0x00000001, read value: 0x00DF0001

Fail DDR addr 0x80085DDC failed. Write value: 0x00000001, read value: 0x00AA0001
........
Fail DDR addr 0x8008DE7C failed. Write value: 0x00000001, read value: 0x000A0001
.....
Fail DDR addr 0x8009257C failed. Write value: 0x00000001, read value: 0x00AA0001
.......
Fail DDR addr 0x8009931C failed. Write value: 0x00000001, read value: 0x00FF0001
.............
Fail DDR addr 0x800A677C failed. Write value: 0x00000001, read value: 0x00FF0001
........
Fail DDR addr 0x800AE13C failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x800AF2FC failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE

Fail DDR addr 0x800B105C failed. Write value: 0xFFFFFFFE, read value: 0xFF55FFFE
.
Fail DDR addr 0x800B07FC failed. Write value: 0x00000001, read value: 0x00FF0001
..................
Fail DDR addr 0x800C20BC failed. Write value: 0x00000005, read value: 0x00FF0005
.................
Fail DDR addr 0x800D3ADC failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x800D463C failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x800D5ABC failed. Write value: 0x00000001, read value: 0x00AA0001
..........
Fail DDR addr 0x800DF07C failed. Write value: 0x00000003, read value: 0x00FF0003

Fail DDR addr 0x800DF0BC failed. Write value: 0x00000003, read value: 0x00AA0003
......................
Fail DDR addr 0x800F7F9C failed. Write value: 0x00000001, read value: 0x00AA0001
............
Fail DDR addr 0x801016FC failed. Write value: 0x00000003, read value: 0x00FF0003
........
Fail DDR addr 0x8010923C failed. Write value: 0x00000001, read value: 0x00AA0001
..............
Fail DDR addr 0x8011727C failed. Write value: 0x00000001, read value: 0x00FF0001
.......................
Fail DDR addr 0x8012E73C failed. Write value: 0x00000005, read value: 0x00FF0005
..........
Fail DDR addr 0x80138E9C failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x8013BABC failed. Write value: 0x00000001, read value: 0x000A0001
.........
Fail DDR addr 0x80144E5C failed. Write value: 0x00000001, read value: 0x00FF0001
..
Fail DDR addr 0x80146E1C failed. Write value: 0x00000001, read value: 0x00FF0001
...
Fail DDR addr 0x8014841C failed. Write value: 0x00000003, read value: 0x00DF0003

Fail DDR addr 0x8014B4FC failed. Write value: 0x00000003, read value: 0x00AA0003

Fail DDR addr 0x8014BEFC failed. Write value: 0x00000003, read value: 0x00AA0003
.
Fail DDR addr 0x8014A1BC failed. Write value: 0x00000001, read value: 0x00AA0001
.......
Fail DDR addr 0x80151C5C failed. Write value: 0xFFFFFFFE, read value: 0xFF00FFFE
..
Fail DDR addr 0x8015363C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8015387C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x801553DC failed. Write value: 0x00000001, read value: 0x00AA0001
.................
Fail DDR addr 0x80164F1C failed. Write value: 0x00000001, read value: 0x00FF0001
................
Fail DDR addr 0x80176A7C failed. Write value: 0x00000001, read value: 0x00AA0001
..
Fail DDR addr 0x8017631C failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x801773FC failed. Write value: 0x00000001, read value: 0x00FF0001
................
Fail DDR addr 0x8018715C failed. Write value: 0x00000005, read value: 0x00FF0005
.........
Fail DDR addr 0x8019081C failed. Write value: 0x00000001, read value: 0x000A0001

Fail DDR addr 0x801929BC failed. Write value: 0x00000001, read value: 0x00AA0001
................
Fail DDR addr 0x801A05DC failed. Write value: 0x00000001, read value: 0x00FF0001
........
Fail DDR addr 0x801A8D3C failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x801A8DDC failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x801A8EBC failed. Write value: 0x00000001, read value: 0x00FF0001
.........
Fail DDR addr 0x801B1C7C failed. Write value: 0x00000003, read value: 0x00FF0003
.....................................
Fail DDR addr 0x801D61FC failed. Write value: 0x00000001, read value: 0x00AA0001
...
Fail DDR addr 0x801D903C failed. Write value: 0x00000001, read value: 0x008A0001
..
Fail DDR addr 0x801DB13C failed. Write value: 0xFFFFFFFE, read value: 0xFFAAFFFE
.......
Fail DDR addr 0x801E2C1C failed. Write value: 0x00000001, read value: 0x008A0001
.
Fail DDR addr 0x801E327C failed. Write value: 0x00000007, read value: 0x00FF0007
...
Fail DDR addr 0x801E677C failed. Write value: 0x00000001, read value: 0x00FF0001
.....
Fail DDR addr 0x801EB2FC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x801ED17C failed. Write value: 0x00000001, read value: 0x00AA0001
..........
Fail DDR addr 0x801F58BC failed. Write value: 0x00000007, read value: 0x00FF0007
....
Fail DDR addr 0x801F905C failed. Write value: 0x00000001, read value: 0x00FF0001
........................................
Fail DDR addr 0x80221BBC failed. Write value: 0xFFFFFFF0, read value: 0xFF00FFF0
...
Fail DDR addr 0x80224B3C failed. Write value: 0x00000001, read value: 0x00AA0001
.........
Fail DDR addr 0x8022D7DC failed. Write value: 0x00000001, read value: 0x00AA0001
.......
Fail DDR addr 0x8023465C failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x80234F3C failed. Write value: 0x00000001, read value: 0x00FF0001
...
Fail DDR addr 0x80237E7C failed. Write value: 0x00000001, read value: 0x00AA0001
.....
Fail DDR addr 0x8023CABC failed. Write value: 0x00000001, read value: 0x008A0001
...............
Fail DDR addr 0x8024BFBC failed. Write value: 0x00000001, read value: 0x00FF0001
..........
Fail DDR addr 0x802550FC failed. Write value: 0x00000001, read value: 0x00FF0001
......
Fail DDR addr 0x8025B41C failed. Write value: 0x00000003, read value: 0x00FF0003

Fail DDR addr 0x8025B71C failed. Write value: 0x00000003, read value: 0x00AA0003
......
Fail DDR addr 0x8026171C failed. Write value: 0x00000001, read value: 0x00AA0001
.
Fail DDR addr 0x80262B1C failed. Write value: 0x00000001, read value: 0x00FF0001
.
Fail DDR addr 0x8026311C failed. Write value: 0x00000003, read value: 0x00FF0003
...
Fail DDR addr 0x802666FC failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x80266C3C failed. Write value: 0x00000001, read value: 0x00AA0001
..................
Fail DDR addr 0x8027AA5C failed. Write value: 0x00000001, read value: 0x00AA0001
................................
Fail DDR addr 0x802980DC failed. Write value: 0x00000001, read value: 0x00FF0001
.............................
Fail DDR addr 0x802B519C failed. Write value: 0x00000001, read value: 0x00AA0001
..
Fail DDR addr 0x802B787C failed. Write value: 0x00000001, read value: 0x00AA0001
............
Fail DDR addr 0x802C317C failed. Write value: 0x00000015, read value: 0x00FF0015
...
Fail DDR addr 0x802C65BC failed. Write value: 0x00000001, read value: 0x00FF0001
......
Fail DDR addr 0x802CCCFC failed. Write value: 0x00000001, read value: 0x00FF0001
.............
Fail DDR addr 0x802D9F9C failed. Write value: 0x00000001, read value: 0x00FF0001
......
Fail DDR addr 0x802DF5FC failed. Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x802DF8FC failed. Write value: 0x00000001, read value: 0x00AA0001

Fail DDR addr 0x802DFABC failed. Write value: 0x00000001, read value: 0x00AA0001

Case 6:  800MHz,  CL=14, CWL=9, tXPR= 5tCK,  tRP=tRCD=13.75ns, inconsecutive test.

Result: The number of times having the problem decreases a lot. However, the corresponding DDR address of all the failed position still ends with the character "C" in hexadecimal, and all happen in the second Byte.

Log

File: DDR4-1600_800MHz_CL14_CWL9_RPRCD1375_XPR5
Delay: YES
start addr: 0x80000000
......................................................................................
Fail DDR addr 0x807CD27C failed. Write value: 0x00000001, read value: 0x00AA0001
..................................................................................
Fail DDR addr 0x80BC6E5C failed. Write value: 0x00000001, read value: 0x000A0001
...............................................................................................................................................
Fail DDR addr 0x80C5527C failed. Write value: 0x00000001, read value: 0x00DF0001
.................................................................................

As you could see, only 3 times having the problem after using the inconsecutive test.

Customer has test 4 boards, and all of them have the same problem.

Customer also measured the DDR signal and see that the preamble for the write is 2 cycles, and for the read is only 1 cycle. As seeing from our previous experiment results, all the problems happen on the "read" side. Hence customer wants to try increase the preamble for the read to 2 cycle. But they do not know how to do that. Seeing from the TRM, we find the below information.

However, in the SysConfig Tool, we do not find the configuration option to do that, could you help us for a try?

And one more question from my side, in Jacinto series LPDDR4 has DBI configuration which could help solve some bit flip problems. May I know in DDR4, do we also have this as customer's problem relates to the bit flip.

Thanks a lot!

Kevin

Kevin, does the same issue occur on multiple boards?

Regards,

James

Hi James,  

Thanks a lot for the support.  I'm the customer Kevin mentioned.  Yes, the same issue occur on multiple boards.

Regards,

Larry

Hi Larry, ok thanks.  Do you have JTAG access and can successfully bring up Code Composer? 

I would like to get a register dump after DDR initialization to see if there are any issues with the training.  Load the attached GEL from the A53 core and run  

DDRSS_CTL_PI_PHY_RegDump() script

Regards,

James

Hi James,

Yes, we have the JTAG access and can bring up CCS successfully.  

Did yo upload a GEL file?  I don't see the attachment.  And we are using AM2431 with MCU+SDK.  It only has R5F core and M4 core.

By the way, would you pls advice how to change the Read/Write preamble to 2 cycles?   I wonder whether 2cycle Read preamble may have some effect on this issue.

Best regards,

Larry

Hi James,

Thanks for your reply！

Seems that you missed uploading the GEL file, could you resend it to customer please?

Customer is working on AM243x, so not having A53 core. Could you also let customer know how to use this GEL file on AM243x?

Many thanks!

Kevin

Sorry forgot to attach.  The GEL will work from the R5F cores as well.

/cfs-file/__key/communityserver-discussions-components-files/908/AM64x_5F00_AM62x_5F00_DDRSS_5F00_RegDump.gel

You can change read preamble in PREAMBLE_SUPPORT_F0 in the following register.

Regards,

James

Hi James,

Here is the register dump when the DDR test program run to just before the DDR write and read start:

MAIN_Cortex_R5_0_0: GEL Output: 0x0F308000 0x10460A01  //DDRSS_CTL_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308004 0x5D1AF3C3  //DDRSS_CTL_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308008 0x0171A610  //DDRSS_CTL_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30800C 0x40020A11  //DDRSS_CTL_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308010 0x00052006  //DDRSS_CTL_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308014 0x02050020  //DDRSS_CTL_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308018 0x03070101  //DDRSS_CTL_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30801C 0x00089070  //DDRSS_CTL_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308020 0x00000000  //DDRSS_CTL_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308024 0x00000000  //DDRSS_CTL_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308028 0x00000000  //DDRSS_CTL_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30802C 0x00089070  //DDRSS_CTL_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308030 0x00000000  //DDRSS_CTL_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308034 0x00000000  //DDRSS_CTL_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308038 0x00000000  //DDRSS_CTL_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30803C 0x00089070  //DDRSS_CTL_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308040 0x00000000  //DDRSS_CTL_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308044 0x00000000  //DDRSS_CTL_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308048 0x00000000  //DDRSS_CTL_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30804C 0x01010100  //DDRSS_CTL_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308050 0x01000101  //DDRSS_CTL_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308054 0x01000110  //DDRSS_CTL_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308058 0x02010002  //DDRSS_CTL_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30805C 0x00027100  //DDRSS_CTL_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308060 0x00061A80  //DDRSS_CTL_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308064 0x02550255  //DDRSS_CTL_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308068 0x00000255  //DDRSS_CTL_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30806C 0x00000000  //DDRSS_CTL_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308070 0x00000000  //DDRSS_CTL_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308074 0x00000000  //DDRSS_CTL_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308078 0x00000000  //DDRSS_CTL_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30807C 0x00000000  //DDRSS_CTL_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308080 0x00000000  //DDRSS_CTL_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308084 0x00000000  //DDRSS_CTL_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308088 0x00000000  //DDRSS_CTL_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30808C 0x00000000  //DDRSS_CTL_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308090 0x00000000  //DDRSS_CTL_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308094 0x00000000  //DDRSS_CTL_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308098 0x04000B16  //DDRSS_CTL_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30809C 0x1C1C1C1C  //DDRSS_CTL_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A0 0x04000B16  //DDRSS_CTL_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A4 0x1C1C1C1C  //DDRSS_CTL_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A8 0x04000B16  //DDRSS_CTL_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080AC 0x1C1C1C1C  //DDRSS_CTL_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B0 0x05050404  //DDRSS_CTL_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B4 0x00002706  //DDRSS_CTL_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B8 0x0602001D  //DDRSS_CTL_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080BC 0x05001D0B  //DDRSS_CTL_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C0 0x00270605  //DDRSS_CTL_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C4 0x0602001D  //DDRSS_CTL_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C8 0x05001D0B  //DDRSS_CTL_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080CC 0x00270605  //DDRSS_CTL_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D0 0x0602001D  //DDRSS_CTL_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D4 0x07001D0B  //DDRSS_CTL_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D8 0x00180807  //DDRSS_CTL_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080DC 0x0400DB60  //DDRSS_CTL_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E0 0x07070009  //DDRSS_CTL_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E4 0x00001808  //DDRSS_CTL_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E8 0x0400DB60  //DDRSS_CTL_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080EC 0x07070009  //DDRSS_CTL_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F0 0x00001808  //DDRSS_CTL_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F4 0x0400DB60  //DDRSS_CTL_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F8 0x03000009  //DDRSS_CTL_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080FC 0x0D0C0002  //DDRSS_CTL_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308100 0x0D0C0D0C  //DDRSS_CTL_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308104 0x01010000  //DDRSS_CTL_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308108 0x03191919  //DDRSS_CTL_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30810C 0x0B0B0B0B  //DDRSS_CTL_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308110 0x00000B0B  //DDRSS_CTL_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308114 0x00000101  //DDRSS_CTL_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308118 0x00000000  //DDRSS_CTL_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30811C 0x01000000  //DDRSS_CTL_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308120 0x00D00803  //DDRSS_CTL_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308124 0x00001860  //DDRSS_CTL_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308128 0x000000D0  //DDRSS_CTL_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30812C 0x00001860  //DDRSS_CTL_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308130 0x000000D0  //DDRSS_CTL_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308134 0x00001860  //DDRSS_CTL_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308138 0x00000005  //DDRSS_CTL_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30813C 0x00000000  //DDRSS_CTL_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308140 0x00000000  //DDRSS_CTL_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308144 0x00000000  //DDRSS_CTL_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308148 0x00000000  //DDRSS_CTL_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30814C 0x00000000  //DDRSS_CTL_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308150 0x00000000  //DDRSS_CTL_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308154 0x00000000  //DDRSS_CTL_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308158 0x00000000  //DDRSS_CTL_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30815C 0x00090009  //DDRSS_CTL_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308160 0x00000009  //DDRSS_CTL_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308164 0x00000000  //DDRSS_CTL_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308168 0x00000000  //DDRSS_CTL_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30816C 0x00000000  //DDRSS_CTL_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308170 0x00000000  //DDRSS_CTL_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308174 0x00000000  //DDRSS_CTL_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308178 0x00010001  //DDRSS_CTL_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30817C 0x00025501  //DDRSS_CTL_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308180 0x025500D8  //DDRSS_CTL_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308184 0x025500D8  //DDRSS_CTL_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308188 0x00D800D8  //DDRSS_CTL_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30818C 0x00D800D8  //DDRSS_CTL_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308190 0x00000000  //DDRSS_CTL_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308194 0x00000000  //DDRSS_CTL_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308198 0x00000000  //DDRSS_CTL_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30819C 0x00000000  //DDRSS_CTL_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A0 0x00000000  //DDRSS_CTL_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A4 0x00000000  //DDRSS_CTL_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A8 0x03010000  //DDRSS_CTL_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081AC 0x00010000  //DDRSS_CTL_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B0 0x00000000  //DDRSS_CTL_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B4 0x01000000  //DDRSS_CTL_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B8 0x80104002  //DDRSS_CTL_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081BC 0x00040003  //DDRSS_CTL_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C0 0x00040005  //DDRSS_CTL_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C4 0x00030000  //DDRSS_CTL_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C8 0x00050004  //DDRSS_CTL_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081CC 0x00000004  //DDRSS_CTL_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D0 0x00040003  //DDRSS_CTL_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D4 0x00040005  //DDRSS_CTL_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D8 0x00000000  //DDRSS_CTL_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081DC 0x00061800  //DDRSS_CTL_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E0 0x00061800  //DDRSS_CTL_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E4 0x00061800  //DDRSS_CTL_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E8 0x00061800  //DDRSS_CTL_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081EC 0x00061800  //DDRSS_CTL_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F0 0x00000000  //DDRSS_CTL_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F4 0x0000AAA0  //DDRSS_CTL_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F8 0x00061800  //DDRSS_CTL_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081FC 0x00061800  //DDRSS_CTL_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308200 0x00061800  //DDRSS_CTL_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308204 0x00061800  //DDRSS_CTL_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308208 0x00061800  //DDRSS_CTL_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30820C 0x00000000  //DDRSS_CTL_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308210 0x0000AAA0  //DDRSS_CTL_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308214 0x00061800  //DDRSS_CTL_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308218 0x00061800  //DDRSS_CTL_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30821C 0x00061800  //DDRSS_CTL_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308220 0x00061800  //DDRSS_CTL_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308224 0x00061800  //DDRSS_CTL_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308228 0x00000000  //DDRSS_CTL_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30822C 0x0000AAA0  //DDRSS_CTL_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308230 0x00000000  //DDRSS_CTL_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308234 0x00000000  //DDRSS_CTL_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308238 0x00000000  //DDRSS_CTL_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30823C 0x00000000  //DDRSS_CTL_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308240 0x00000000  //DDRSS_CTL_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308244 0x00000000  //DDRSS_CTL_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308248 0x00000000  //DDRSS_CTL_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30824C 0x00000000  //DDRSS_CTL_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308250 0x00000000  //DDRSS_CTL_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308254 0x00000000  //DDRSS_CTL_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308258 0x00000000  //DDRSS_CTL_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30825C 0x00000000  //DDRSS_CTL_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308260 0x00000000  //DDRSS_CTL_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308264 0x00000000  //DDRSS_CTL_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308268 0x00000000  //DDRSS_CTL_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30826C 0x00000000  //DDRSS_CTL_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308270 0x080C0000  //DDRSS_CTL_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308274 0x080C080C  //DDRSS_CTL_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308278 0x00000000  //DDRSS_CTL_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30827C 0x07010A09  //DDRSS_CTL_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308280 0x000E0A09  //DDRSS_CTL_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308284 0x010A0900  //DDRSS_CTL_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308288 0x0E0A0907  //DDRSS_CTL_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30828C 0x0A090000  //DDRSS_CTL_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308290 0x0A090701  //DDRSS_CTL_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308294 0x0000080E  //DDRSS_CTL_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308298 0x00040003  //DDRSS_CTL_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30829C 0x00004007  //DDRSS_CTL_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A0 0x00000000  //DDRSS_CTL_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A4 0x00000000  //DDRSS_CTL_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A8 0x00000000  //DDRSS_CTL_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082AC 0x00000000  //DDRSS_CTL_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B0 0x00000000  //DDRSS_CTL_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B4 0x00000000  //DDRSS_CTL_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B8 0x01000000  //DDRSS_CTL_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082BC 0x00000000  //DDRSS_CTL_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C0 0x00001500  //DDRSS_CTL_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C4 0x0000100E  //DDRSS_CTL_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C8 0x00000000  //DDRSS_CTL_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082CC 0x00000000  //DDRSS_CTL_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D0 0x00000001  //DDRSS_CTL_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D4 0x00000002  //DDRSS_CTL_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D8 0x00000C00  //DDRSS_CTL_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082DC 0x00001000  //DDRSS_CTL_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E0 0x00000C00  //DDRSS_CTL_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E4 0x00001000  //DDRSS_CTL_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E8 0x00000C00  //DDRSS_CTL_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082EC 0x00001000  //DDRSS_CTL_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F0 0x00000000  //DDRSS_CTL_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F4 0x00000000  //DDRSS_CTL_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F8 0x00000000  //DDRSS_CTL_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082FC 0x00000000  //DDRSS_CTL_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308300 0x00000000  //DDRSS_CTL_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308304 0x00000000  //DDRSS_CTL_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308308 0x00000000  //DDRSS_CTL_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30830C 0x00000000  //DDRSS_CTL_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308310 0x00000000  //DDRSS_CTL_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308314 0x00000000  //DDRSS_CTL_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308318 0x00000000  //DDRSS_CTL_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30831C 0x00000000  //DDRSS_CTL_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308320 0x00000000  //DDRSS_CTL_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308324 0x00000000  //DDRSS_CTL_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308328 0x00000000  //DDRSS_CTL_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30832C 0x00000000  //DDRSS_CTL_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308330 0x00041000  //DDRSS_CTL_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308334 0x00000503  //DDRSS_CTL_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308338 0x00000010  //DDRSS_CTL_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30833C 0x00000410  //DDRSS_CTL_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308340 0x00000503  //DDRSS_CTL_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308344 0x00000010  //DDRSS_CTL_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308348 0x00000410  //DDRSS_CTL_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30834C 0x00000503  //DDRSS_CTL_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308350 0x00000010  //DDRSS_CTL_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308354 0x00000410  //DDRSS_CTL_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308358 0x00000503  //DDRSS_CTL_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30835C 0x00000010  //DDRSS_CTL_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308360 0x00000410  //DDRSS_CTL_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308364 0x00000503  //DDRSS_CTL_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308368 0x00000010  //DDRSS_CTL_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30836C 0x00000410  //DDRSS_CTL_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308370 0x00000503  //DDRSS_CTL_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308374 0x00000010  //DDRSS_CTL_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308378 0x00000000  //DDRSS_CTL_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30837C 0x00000000  //DDRSS_CTL_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308380 0x00000000  //DDRSS_CTL_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308384 0x00000000  //DDRSS_CTL_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308388 0x00000000  //DDRSS_CTL_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30838C 0x00000000  //DDRSS_CTL_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308390 0x00000000  //DDRSS_CTL_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308394 0x00000000  //DDRSS_CTL_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308398 0x00000000  //DDRSS_CTL_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30839C 0x00000000  //DDRSS_CTL_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A0 0x00000000  //DDRSS_CTL_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A4 0x00000000  //DDRSS_CTL_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A8 0x00000000  //DDRSS_CTL_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083AC 0x00000000  //DDRSS_CTL_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B0 0x00001401  //DDRSS_CTL_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B4 0x00001401  //DDRSS_CTL_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B8 0x00001401  //DDRSS_CTL_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083BC 0x00001401  //DDRSS_CTL_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C0 0x00001401  //DDRSS_CTL_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C4 0x00001401  //DDRSS_CTL_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C8 0x00000493  //DDRSS_CTL_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083CC 0x00000493  //DDRSS_CTL_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D0 0x00000493  //DDRSS_CTL_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D4 0x00000493  //DDRSS_CTL_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D8 0x00000493  //DDRSS_CTL_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083DC 0x00000493  //DDRSS_CTL_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E0 0x00000000  //DDRSS_CTL_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E4 0x00000000  //DDRSS_CTL_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E8 0x00000000  //DDRSS_CTL_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083EC 0x00000000  //DDRSS_CTL_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F0 0x00000000  //DDRSS_CTL_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F4 0x00000000  //DDRSS_CTL_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F8 0x00000000  //DDRSS_CTL_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083FC 0x00000000  //DDRSS_CTL_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308400 0x00000000  //DDRSS_CTL_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308404 0x00000000  //DDRSS_CTL_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308408 0x00000000  //DDRSS_CTL_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30840C 0x00000000  //DDRSS_CTL_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308410 0x00000000  //DDRSS_CTL_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308414 0x00000000  //DDRSS_CTL_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308418 0x00000000  //DDRSS_CTL_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30841C 0x00000000  //DDRSS_CTL_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308420 0x00000000  //DDRSS_CTL_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308424 0x00000000  //DDRSS_CTL_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308428 0x00000000  //DDRSS_CTL_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30842C 0x00000000  //DDRSS_CTL_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308430 0x00000000  //DDRSS_CTL_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308434 0x00000000  //DDRSS_CTL_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308438 0x00000000  //DDRSS_CTL_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30843C 0x00000000  //DDRSS_CTL_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308440 0x00000000  //DDRSS_CTL_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308444 0x00000000  //DDRSS_CTL_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308448 0x00000000  //DDRSS_CTL_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30844C 0x00000000  //DDRSS_CTL_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308450 0x00000000  //DDRSS_CTL_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308454 0x00010000  //DDRSS_CTL_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308458 0x00000000  //DDRSS_CTL_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30845C 0x00000100  //DDRSS_CTL_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308460 0x00000000  //DDRSS_CTL_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308464 0x00000101  //DDRSS_CTL_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308468 0x00000000  //DDRSS_CTL_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30846C 0x00000000  //DDRSS_CTL_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308470 0x00000000  //DDRSS_CTL_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308474 0x00000000  //DDRSS_CTL_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308478 0x00000000  //DDRSS_CTL_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30847C 0x00000000  //DDRSS_CTL_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308480 0x00000000  //DDRSS_CTL_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308484 0x00000FFF  //DDRSS_CTL_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308488 0x0C181511  //DDRSS_CTL_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30848C 0x00000304  //DDRSS_CTL_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308490 0x00000000  //DDRSS_CTL_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308494 0x00000000  //DDRSS_CTL_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308498 0x00000000  //DDRSS_CTL_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30849C 0x00000000  //DDRSS_CTL_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A0 0x00000000  //DDRSS_CTL_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A4 0x00000000  //DDRSS_CTL_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A8 0x00000000  //DDRSS_CTL_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084AC 0x00000000  //DDRSS_CTL_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B0 0x00000000  //DDRSS_CTL_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B4 0x00000000  //DDRSS_CTL_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B8 0x00000000  //DDRSS_CTL_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084BC 0x00000000  //DDRSS_CTL_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C0 0x00000000  //DDRSS_CTL_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C4 0x00040000  //DDRSS_CTL_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C8 0x00800200  //DDRSS_CTL_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084CC 0x00000000  //DDRSS_CTL_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D0 0x02000400  //DDRSS_CTL_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D4 0x00000080  //DDRSS_CTL_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D8 0x00040000  //DDRSS_CTL_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084DC 0x00800200  //DDRSS_CTL_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E0 0x00000000  //DDRSS_CTL_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E4 0x00000000  //DDRSS_CTL_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E8 0x00000000  //DDRSS_CTL_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084EC 0x00000100  //DDRSS_CTL_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F0 0x01010000  //DDRSS_CTL_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F4 0x00000202  //DDRSS_CTL_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F8 0x0FFF0000  //DDRSS_CTL_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084FC 0x000FFF00  //DDRSS_CTL_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308500 0xFFFFFFFF  //DDRSS_CTL_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308504 0x00FFFF00  //DDRSS_CTL_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308508 0x0A000000  //DDRSS_CTL_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30850C 0x0001FFFF  //DDRSS_CTL_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308510 0x01010101  //DDRSS_CTL_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308514 0x01010101  //DDRSS_CTL_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308518 0x00000118  //DDRSS_CTL_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30851C 0x00000C01  //DDRSS_CTL_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308520 0x00000000  //DDRSS_CTL_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308524 0x00000000  //DDRSS_CTL_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308528 0x00000000  //DDRSS_CTL_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30852C 0x01000000  //DDRSS_CTL_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308530 0x00000100  //DDRSS_CTL_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308534 0x00010000  //DDRSS_CTL_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308538 0x00000000  //DDRSS_CTL_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30853C 0x00000000  //DDRSS_CTL_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308540 0x00000000  //DDRSS_CTL_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308544 0x00000000  //DDRSS_CTL_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308548 0x00000000  //DDRSS_CTL_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30854C 0x00000000  //DDRSS_CTL_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308550 0x00000000  //DDRSS_CTL_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308554 0x00000000  //DDRSS_CTL_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308558 0x00000000  //DDRSS_CTL_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30855C 0x00000000  //DDRSS_CTL_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308560 0x00000000  //DDRSS_CTL_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308564 0x00000000  //DDRSS_CTL_345_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308568 0x00000000  //DDRSS_CTL_346_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30856C 0x00000000  //DDRSS_CTL_347_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308570 0x00000000  //DDRSS_CTL_348_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308574 0x00000000  //DDRSS_CTL_349_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308578 0x00000000  //DDRSS_CTL_350_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30857C 0x00000000  //DDRSS_CTL_351_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308580 0x00000000  //DDRSS_CTL_352_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308584 0x00000000  //DDRSS_CTL_353_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308588 0x00000000  //DDRSS_CTL_354_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30858C 0x00000000  //DDRSS_CTL_355_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308590 0x00000000  //DDRSS_CTL_356_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308594 0x00000000  //DDRSS_CTL_357_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308598 0x00000000  //DDRSS_CTL_358_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30859C 0x00000000  //DDRSS_CTL_359_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A0 0x00000000  //DDRSS_CTL_360_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A4 0x00000000  //DDRSS_CTL_361_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A8 0x00000000  //DDRSS_CTL_362_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085AC 0x00000000  //DDRSS_CTL_363_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B0 0x00000000  //DDRSS_CTL_364_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B4 0x0000FFFF  //DDRSS_CTL_365_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B8 0x0000FFFF  //DDRSS_CTL_366_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085BC 0x0158EFF0  //DDRSS_CTL_367_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C0 0x00000000  //DDRSS_CTL_368_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C4 0x00000000  //DDRSS_CTL_369_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C8 0x0E000000  //DDRSS_CTL_370_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085CC 0x060E0606  //DDRSS_CTL_371_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D0 0x06060E06  //DDRSS_CTL_372_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D4 0x00010101  //DDRSS_CTL_373_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D8 0x02000000  //DDRSS_CTL_374_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085DC 0x00020101  //DDRSS_CTL_375_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E0 0x00000000  //DDRSS_CTL_376_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E4 0x02020200  //DDRSS_CTL_377_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E8 0x02020202  //DDRSS_CTL_378_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085EC 0x02020202  //DDRSS_CTL_379_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F0 0x02020202  //DDRSS_CTL_380_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F4 0x00000000  //DDRSS_CTL_381_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F8 0x00000000  //DDRSS_CTL_382_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085FC 0x04000100  //DDRSS_CTL_383_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308600 0x1E000304  //DDRSS_CTL_384_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308604 0x000030C0  //DDRSS_CTL_385_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308608 0x00000200  //DDRSS_CTL_386_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30860C 0x00000200  //DDRSS_CTL_387_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308610 0x00000200  //DDRSS_CTL_388_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308614 0x00000200  //DDRSS_CTL_389_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308618 0x0000DB60  //DDRSS_CTL_390_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30861C 0x0001E780  //DDRSS_CTL_391_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308620 0x090A0302  //DDRSS_CTL_392_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308624 0x001E0B0C  //DDRSS_CTL_393_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308628 0x000030C0  //DDRSS_CTL_394_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30862C 0x00000200  //DDRSS_CTL_395_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308630 0x00000200  //DDRSS_CTL_396_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308634 0x00000200  //DDRSS_CTL_397_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308638 0x00000200  //DDRSS_CTL_398_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30863C 0x0000DB60  //DDRSS_CTL_399_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308640 0x0001E780  //DDRSS_CTL_400_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308644 0x090A0302  //DDRSS_CTL_401_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308648 0x001E0B0C  //DDRSS_CTL_402_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30864C 0x000030C0  //DDRSS_CTL_403_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308650 0x00000200  //DDRSS_CTL_404_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308654 0x00000200  //DDRSS_CTL_405_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308658 0x00000200  //DDRSS_CTL_406_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30865C 0x00000200  //DDRSS_CTL_407_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308660 0x0000DB60  //DDRSS_CTL_408_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308664 0x0001E780  //DDRSS_CTL_409_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308668 0x090A0302  //DDRSS_CTL_410_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30866C 0x00000B0C  //DDRSS_CTL_411_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308670 0x00000000  //DDRSS_CTL_412_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308674 0x0302000A  //DDRSS_CTL_413_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308678 0x01000500  //DDRSS_CTL_414_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30867C 0x01010001  //DDRSS_CTL_415_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308680 0x00010001  //DDRSS_CTL_416_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308684 0x01010001  //DDRSS_CTL_417_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308688 0x02010000  //DDRSS_CTL_418_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30868C 0x00000200  //DDRSS_CTL_419_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308690 0x02000201  //DDRSS_CTL_420_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308694 0x00000000  //DDRSS_CTL_421_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308698 0x00202020  //DDRSS_CTL_422_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A000 0x00000A01  //DDRSS_PI_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A004 0xAE8D79E2  //DDRSS_PI_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A008 0x0714B570  //DDRSS_PI_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A00C 0x01011387  //DDRSS_PI_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A010 0x00000001  //DDRSS_PI_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A014 0x00010064  //DDRSS_PI_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A018 0x00000000  //DDRSS_PI_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A01C 0x00000000  //DDRSS_PI_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A020 0x00000000  //DDRSS_PI_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A024 0x00000000  //DDRSS_PI_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A028 0x00000000  //DDRSS_PI_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A02C 0x00000000  //DDRSS_PI_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A030 0x00000000  //DDRSS_PI_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A034 0x00010001  //DDRSS_PI_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A038 0x00000000  //DDRSS_PI_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A03C 0x00010001  //DDRSS_PI_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A040 0x00000005  //DDRSS_PI_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A044 0x00010000  //DDRSS_PI_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A048 0x00000000  //DDRSS_PI_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A04C 0x00000000  //DDRSS_PI_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A050 0x00000000  //DDRSS_PI_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A054 0x00000000  //DDRSS_PI_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A058 0x00000000  //DDRSS_PI_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A05C 0x00000000  //DDRSS_PI_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A060 0x280D0001  //DDRSS_PI_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A064 0x00000000  //DDRSS_PI_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A068 0x00010000  //DDRSS_PI_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A06C 0x00003200  //DDRSS_PI_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A070 0x00000000  //DDRSS_PI_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A074 0x00000000  //DDRSS_PI_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A078 0x00060602  //DDRSS_PI_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A07C 0x00000000  //DDRSS_PI_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A080 0x00000000  //DDRSS_PI_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A084 0x00000000  //DDRSS_PI_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A088 0x00000001  //DDRSS_PI_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A08C 0x00000055  //DDRSS_PI_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A090 0x000000AA  //DDRSS_PI_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A094 0x000000AD  //DDRSS_PI_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A098 0x00000052  //DDRSS_PI_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A09C 0x0000006A  //DDRSS_PI_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A0 0x00000095  //DDRSS_PI_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A4 0x00000095  //DDRSS_PI_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A8 0x000000AD  //DDRSS_PI_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0AC 0x00000000  //DDRSS_PI_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B0 0x00000000  //DDRSS_PI_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B4 0x00010100  //DDRSS_PI_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B8 0x00000014  //DDRSS_PI_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0BC 0x000007D0  //DDRSS_PI_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C0 0x00000300  //DDRSS_PI_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C4 0x00000000  //DDRSS_PI_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C8 0x00000000  //DDRSS_PI_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0CC 0x01000000  //DDRSS_PI_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D0 0x00010101  //DDRSS_PI_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D4 0x01000B09  //DDRSS_PI_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D8 0x00000000  //DDRSS_PI_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0DC 0x00010000  //DDRSS_PI_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E0 0x00000000  //DDRSS_PI_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E4 0x00000000  //DDRSS_PI_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E8 0x00000000  //DDRSS_PI_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0EC 0x00000000  //DDRSS_PI_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F0 0x00001400  //DDRSS_PI_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F4 0x00000000  //DDRSS_PI_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F8 0x01000000  //DDRSS_PI_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0FC 0x00000404  //DDRSS_PI_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A100 0x00000001  //DDRSS_PI_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A104 0x0001010E  //DDRSS_PI_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A108 0x02040100  //DDRSS_PI_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A10C 0x00010000  //DDRSS_PI_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A110 0x00000034  //DDRSS_PI_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A114 0x00000000  //DDRSS_PI_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A118 0x00000000  //DDRSS_PI_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A11C 0x00000000  //DDRSS_PI_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A120 0x00000000  //DDRSS_PI_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A124 0x00000000  //DDRSS_PI_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A128 0x00000000  //DDRSS_PI_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A12C 0x00000005  //DDRSS_PI_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A130 0x01000000  //DDRSS_PI_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A134 0x04020100  //DDRSS_PI_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A138 0x00020000  //DDRSS_PI_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A13C 0x00010002  //DDRSS_PI_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A140 0x00000001  //DDRSS_PI_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A144 0x00020001  //DDRSS_PI_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A148 0x00020002  //DDRSS_PI_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A14C 0x29C02000  //DDRSS_PI_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A150 0x00000000  //DDRSS_PI_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A154 0x00000000  //DDRSS_PI_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A158 0x00000000  //DDRSS_PI_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A15C 0x00000000  //DDRSS_PI_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A160 0x00000000  //DDRSS_PI_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A164 0x00000000  //DDRSS_PI_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A168 0x00000000  //DDRSS_PI_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A16C 0x00000300  //DDRSS_PI_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A170 0x0A090B0C  //DDRSS_PI_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A174 0x04060708  //DDRSS_PI_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A178 0x01000005  //DDRSS_PI_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A17C 0x00000800  //DDRSS_PI_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A180 0x00000000  //DDRSS_PI_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A184 0x00010008  //DDRSS_PI_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A188 0x00000000  //DDRSS_PI_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A18C 0x0000AA00  //DDRSS_PI_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A190 0x00000000  //DDRSS_PI_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A194 0x00010000  //DDRSS_PI_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A198 0x00000000  //DDRSS_PI_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A19C 0x00000000  //DDRSS_PI_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A0 0x00000000  //DDRSS_PI_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A4 0x00000000  //DDRSS_PI_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A8 0x00000000  //DDRSS_PI_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1AC 0x00000000  //DDRSS_PI_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B0 0x00000000  //DDRSS_PI_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B4 0x00000000  //DDRSS_PI_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B8 0x00000000  //DDRSS_PI_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1BC 0x00000000  //DDRSS_PI_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C0 0x00000000  //DDRSS_PI_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C4 0x00000000  //DDRSS_PI_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C8 0x00000000  //DDRSS_PI_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1CC 0x00000000  //DDRSS_PI_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D0 0x00000000  //DDRSS_PI_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D4 0x00000000  //DDRSS_PI_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D8 0x00000000  //DDRSS_PI_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1DC 0x00000000  //DDRSS_PI_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E0 0x00000000  //DDRSS_PI_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E4 0x00000000  //DDRSS_PI_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E8 0x00000000  //DDRSS_PI_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1EC 0x00000000  //DDRSS_PI_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F0 0x00000008  //DDRSS_PI_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F4 0x00000000  //DDRSS_PI_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F8 0x00000000  //DDRSS_PI_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1FC 0x00000000  //DDRSS_PI_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A200 0x00000000  //DDRSS_PI_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A204 0x00000000  //DDRSS_PI_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A208 0x00000000  //DDRSS_PI_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A20C 0x00000000  //DDRSS_PI_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A210 0x00000000  //DDRSS_PI_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A214 0x00010100  //DDRSS_PI_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A218 0x00000000  //DDRSS_PI_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A21C 0x00000000  //DDRSS_PI_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A220 0x00027100  //DDRSS_PI_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A224 0x00061A80  //DDRSS_PI_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A228 0x00000100  //DDRSS_PI_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A22C 0x00000000  //DDRSS_PI_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A230 0x00000000  //DDRSS_PI_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A234 0x00000000  //DDRSS_PI_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A238 0x00000000  //DDRSS_PI_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A23C 0x00000000  //DDRSS_PI_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A240 0x01000000  //DDRSS_PI_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A244 0xC1010003  //DDRSS_PI_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A248 0x02000101  //DDRSS_PI_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A24C 0x01030101  //DDRSS_PI_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A250 0x00010400  //DDRSS_PI_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A254 0x06000105  //DDRSS_PI_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A258 0x01070001  //DDRSS_PI_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A25C 0x00000000  //DDRSS_PI_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A260 0x00000000  //DDRSS_PI_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A264 0x00000001  //DDRSS_PI_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A268 0x00010000  //DDRSS_PI_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A26C 0x00000000  //DDRSS_PI_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A270 0x00000000  //DDRSS_PI_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A274 0x00000000  //DDRSS_PI_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A278 0x00000000  //DDRSS_PI_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A27C 0x00010000  //DDRSS_PI_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A280 0x00000004  //DDRSS_PI_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A284 0x00000000  //DDRSS_PI_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A288 0x00000000  //DDRSS_PI_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A28C 0x00000000  //DDRSS_PI_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A290 0x00007800  //DDRSS_PI_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A294 0x00780078  //DDRSS_PI_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A298 0x00141414  //DDRSS_PI_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A29C 0x00000037  //DDRSS_PI_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A0 0x00000037  //DDRSS_PI_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A4 0x00040037  //DDRSS_PI_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A8 0x04000400  //DDRSS_PI_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2AC 0x6804000B  //DDRSS_PI_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B0 0x04000B16  //DDRSS_PI_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B4 0x000B1668  //DDRSS_PI_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B8 0x00166804  //DDRSS_PI_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2BC 0x000000D0  //DDRSS_PI_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C0 0x00001860  //DDRSS_PI_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C4 0x000000D0  //DDRSS_PI_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C8 0x00001860  //DDRSS_PI_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2CC 0x000000D0  //DDRSS_PI_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D0 0x04001860  //DDRSS_PI_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D4 0x01010404  //DDRSS_PI_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D8 0x00001901  //DDRSS_PI_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2DC 0x00190019  //DDRSS_PI_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E0 0x010E010E  //DDRSS_PI_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E4 0x0000010E  //DDRSS_PI_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E8 0x00000000  //DDRSS_PI_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2EC 0x00000000  //DDRSS_PI_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F0 0x01010000  //DDRSS_PI_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F4 0x01010101  //DDRSS_PI_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F8 0x00181818  //DDRSS_PI_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2FC 0x00000000  //DDRSS_PI_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A300 0x00000000  //DDRSS_PI_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A304 0x0A000000  //DDRSS_PI_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A308 0x0C0C0A0A  //DDRSS_PI_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A30C 0x0303030C  //DDRSS_PI_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A310 0x00000000  //DDRSS_PI_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A314 0x00000000  //DDRSS_PI_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A318 0x00000000  //DDRSS_PI_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A31C 0x00000000  //DDRSS_PI_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A320 0x00000000  //DDRSS_PI_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A324 0x00000000  //DDRSS_PI_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A328 0x00000000  //DDRSS_PI_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A32C 0x00000000  //DDRSS_PI_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A330 0x00000000  //DDRSS_PI_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A334 0x00000000  //DDRSS_PI_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A338 0x00000000  //DDRSS_PI_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A33C 0x00000000  //DDRSS_PI_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A340 0x00000000  //DDRSS_PI_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A344 0x0D090000  //DDRSS_PI_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A348 0x0D09000D  //DDRSS_PI_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A34C 0x0D09000D  //DDRSS_PI_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A350 0x0000000D  //DDRSS_PI_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A354 0x00000000  //DDRSS_PI_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A358 0x00000000  //DDRSS_PI_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A35C 0x00000000  //DDRSS_PI_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A360 0x00000000  //DDRSS_PI_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A364 0x16000000  //DDRSS_PI_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A368 0x001600C8  //DDRSS_PI_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A36C 0x001600C8  //DDRSS_PI_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A370 0x010100C8  //DDRSS_PI_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A374 0x00001D01  //DDRSS_PI_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A378 0x1F0F004E  //DDRSS_PI_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A37C 0x02000001  //DDRSS_PI_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A380 0x001D0A0A  //DDRSS_PI_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A384 0x1F0F004E  //DDRSS_PI_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A388 0x02000001  //DDRSS_PI_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A38C 0x001D0A0A  //DDRSS_PI_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A390 0x1F0F004E  //DDRSS_PI_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A394 0x02000001  //DDRSS_PI_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A398 0x00010A0A  //DDRSS_PI_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A39C 0x0C0B0700  //DDRSS_PI_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A0 0x000D0605  //DDRSS_PI_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A4 0x0000C570  //DDRSS_PI_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A8 0x0000001D  //DDRSS_PI_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3AC 0x180A0800  //DDRSS_PI_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B0 0x0B071C1C  //DDRSS_PI_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B4 0x0D06050C  //DDRSS_PI_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B8 0x0000C570  //DDRSS_PI_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3BC 0x0000001D  //DDRSS_PI_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C0 0x180A0800  //DDRSS_PI_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C4 0x0B071C1C  //DDRSS_PI_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C8 0x0D06050C  //DDRSS_PI_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3CC 0x0000C570  //DDRSS_PI_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D0 0x0000001D  //DDRSS_PI_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D4 0x180A0800  //DDRSS_PI_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D8 0x00001C1C  //DDRSS_PI_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3DC 0x000030C0  //DDRSS_PI_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E0 0x0001E780  //DDRSS_PI_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E4 0x000030C0  //DDRSS_PI_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E8 0x0001E780  //DDRSS_PI_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3EC 0x000030C0  //DDRSS_PI_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F0 0x0001E780  //DDRSS_PI_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F4 0x02550255  //DDRSS_PI_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F8 0x03030255  //DDRSS_PI_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3FC 0x00025503  //DDRSS_PI_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A400 0x02550255  //DDRSS_PI_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A404 0x0C080C08  //DDRSS_PI_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A408 0x00000C08  //DDRSS_PI_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A40C 0x00089070  //DDRSS_PI_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A410 0x00000000  //DDRSS_PI_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A414 0x00000000  //DDRSS_PI_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A418 0x00000000  //DDRSS_PI_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A41C 0x000000D8  //DDRSS_PI_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A420 0x00089070  //DDRSS_PI_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A424 0x00000000  //DDRSS_PI_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A428 0x00000000  //DDRSS_PI_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A42C 0x00000000  //DDRSS_PI_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A430 0x000000D8  //DDRSS_PI_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A434 0x00089070  //DDRSS_PI_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A438 0x00000000  //DDRSS_PI_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A43C 0x00000000  //DDRSS_PI_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A440 0x00000000  //DDRSS_PI_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A444 0x020000D8  //DDRSS_PI_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A448 0x00000080  //DDRSS_PI_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A44C 0x00020000  //DDRSS_PI_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A450 0x00000080  //DDRSS_PI_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A454 0x00020000  //DDRSS_PI_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A458 0x00000080  //DDRSS_PI_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A45C 0x00000000  //DDRSS_PI_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A460 0x00000000  //DDRSS_PI_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A464 0x00040404  //DDRSS_PI_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A468 0x00000000  //DDRSS_PI_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A46C 0x02010102  //DDRSS_PI_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A470 0x67676767  //DDRSS_PI_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A474 0x00000202  //DDRSS_PI_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A478 0x00000000  //DDRSS_PI_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A47C 0x00000000  //DDRSS_PI_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A480 0x00000000  //DDRSS_PI_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A484 0x00000000  //DDRSS_PI_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A488 0x00000000  //DDRSS_PI_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A48C 0x0D100F00  //DDRSS_PI_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A490 0x0003020E  //DDRSS_PI_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A494 0x00000001  //DDRSS_PI_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A498 0x01000000  //DDRSS_PI_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A49C 0x00020201  //DDRSS_PI_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A0 0x00000000  //DDRSS_PI_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A4 0x00000410  //DDRSS_PI_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A8 0x00000503  //DDRSS_PI_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4AC 0x00000010  //DDRSS_PI_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B0 0x00000000  //DDRSS_PI_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B4 0x00000000  //DDRSS_PI_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B8 0x00001401  //DDRSS_PI_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4BC 0x00000493  //DDRSS_PI_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C0 0x00000000  //DDRSS_PI_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C4 0x00000410  //DDRSS_PI_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C8 0x00000503  //DDRSS_PI_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4CC 0x00000010  //DDRSS_PI_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D0 0x00000000  //DDRSS_PI_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D4 0x00000000  //DDRSS_PI_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D8 0x00001401  //DDRSS_PI_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4DC 0x00000493  //DDRSS_PI_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E0 0x00000000  //DDRSS_PI_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E4 0x00000410  //DDRSS_PI_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E8 0x00000503  //DDRSS_PI_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4EC 0x00000010  //DDRSS_PI_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F0 0x00000000  //DDRSS_PI_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F4 0x00000000  //DDRSS_PI_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F8 0x00001401  //DDRSS_PI_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4FC 0x00000493  //DDRSS_PI_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A500 0x00000000  //DDRSS_PI_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A504 0x00000410  //DDRSS_PI_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A508 0x00000503  //DDRSS_PI_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A50C 0x00000010  //DDRSS_PI_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A510 0x00000000  //DDRSS_PI_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A514 0x00000000  //DDRSS_PI_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A518 0x00001401  //DDRSS_PI_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A51C 0x00000493  //DDRSS_PI_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A520 0x00000000  //DDRSS_PI_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A524 0x00000410  //DDRSS_PI_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A528 0x00000503  //DDRSS_PI_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A52C 0x00000010  //DDRSS_PI_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A530 0x00000000  //DDRSS_PI_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A534 0x00000000  //DDRSS_PI_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A538 0x00001401  //DDRSS_PI_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A53C 0x00000493  //DDRSS_PI_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A540 0x00000000  //DDRSS_PI_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A544 0x00000410  //DDRSS_PI_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A548 0x00000503  //DDRSS_PI_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A54C 0x00000010  //DDRSS_PI_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A550 0x00000000  //DDRSS_PI_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A554 0x00000000  //DDRSS_PI_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A558 0x00001401  //DDRSS_PI_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A55C 0x00000493  //DDRSS_PI_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A560 0x00000000  //DDRSS_PI_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C000 0x04C00000  //DDRSS_PHY_0_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C004 0x00000000  //DDRSS_PHY_1_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C008 0x00000200  //DDRSS_PHY_2_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C00C 0x00000000  //DDRSS_PHY_3_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C010 0x00000000  //DDRSS_PHY_4_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C014 0x00000000  //DDRSS_PHY_5_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C018 0x00000000  //DDRSS_PHY_6_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C01C 0x00000000  //DDRSS_PHY_7_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C020 0x00000001  //DDRSS_PHY_8_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C024 0x00000000  //DDRSS_PHY_9_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C028 0x0A0C0000  //DDRSS_PHY_10_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C02C 0x010101FF  //DDRSS_PHY_11_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C030 0x00010000  //DDRSS_PHY_12_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C034 0x00C04004  //DDRSS_PHY_13_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C038 0x00CC0008  //DDRSS_PHY_14_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C03C 0x00660201  //DDRSS_PHY_15_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C040 0x00000000  //DDRSS_PHY_16_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C044 0x00000000  //DDRSS_PHY_17_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C048 0x00000000  //DDRSS_PHY_18_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C04C 0x0000AAAA  //DDRSS_PHY_19_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C050 0x00005555  //DDRSS_PHY_20_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C054 0x0000B5B5  //DDRSS_PHY_21_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C058 0x00004A4A  //DDRSS_PHY_22_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C05C 0x00005656  //DDRSS_PHY_23_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C060 0x0000A9A9  //DDRSS_PHY_24_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C064 0x0000B7B7  //DDRSS_PHY_25_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C068 0x00004848  //DDRSS_PHY_26_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C06C 0x00000000  //DDRSS_PHY_27_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C070 0x00000000  //DDRSS_PHY_28_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C074 0x08000000  //DDRSS_PHY_29_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C078 0x0F000008  //DDRSS_PHY_30_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C07C 0x00000F0F  //DDRSS_PHY_31_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C080 0x00E4E400  //DDRSS_PHY_32_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C084 0x00070820  //DDRSS_PHY_33_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C088 0x000C0020  //DDRSS_PHY_34_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C08C 0x00062000  //DDRSS_PHY_35_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C090 0x00000000  //DDRSS_PHY_36_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C094 0x55555555  //DDRSS_PHY_37_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C098 0xAAAAAAAA  //DDRSS_PHY_38_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C09C 0x55555555  //DDRSS_PHY_39_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A0 0xAAAAAAAA  //DDRSS_PHY_40_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A4 0x00005555  //DDRSS_PHY_41_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A8 0x01000100  //DDRSS_PHY_42_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0AC 0x00800180  //DDRSS_PHY_43_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B0 0x00000000  //DDRSS_PHY_44_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B4 0x00100000  //DDRSS_PHY_45_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B8 0x00000000  //DDRSS_PHY_46_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0BC 0x06070010  //DDRSS_PHY_47_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C0 0x0000000C  //DDRSS_PHY_48_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C4 0x00000100  //DDRSS_PHY_49_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C8 0x00300024  //DDRSS_PHY_50_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0CC 0x00000FFF  //DDRSS_PHY_51_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D0 0x00000000  //DDRSS_PHY_52_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D4 0x02B802AC  //DDRSS_PHY_53_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D8 0x00000030  //DDRSS_PHY_54_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0DC 0x0114003C  //DDRSS_PHY_55_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E0 0x00000000  //DDRSS_PHY_56_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E4 0x0C000000  //DDRSS_PHY_57_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E8 0x07FF0000  //DDRSS_PHY_58_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0EC 0x00000000  //DDRSS_PHY_59_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F0 0x00000000  //DDRSS_PHY_60_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F4 0x00000000  //DDRSS_PHY_61_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F8 0x00000000  //DDRSS_PHY_62_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0FC 0x00000000  //DDRSS_PHY_63_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C100 0x00000000  //DDRSS_PHY_64_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C104 0x00000004  //DDRSS_PHY_65_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C108 0x00000000  //DDRSS_PHY_66_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C10C 0x00000000  //DDRSS_PHY_67_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C110 0x00000000  //DDRSS_PHY_68_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C114 0x00000000  //DDRSS_PHY_69_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C118 0x00000000  //DDRSS_PHY_70_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C11C 0x00000000  //DDRSS_PHY_71_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C120 0x041F07FF  //DDRSS_PHY_72_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C124 0x00000000  //DDRSS_PHY_73_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C128 0x01CCB001  //DDRSS_PHY_74_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C12C 0x2000CCB0  //DDRSS_PHY_75_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C130 0x20000140  //DDRSS_PHY_76_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C134 0x07FF0200  //DDRSS_PHY_77_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C138 0x0000DD01  //DDRSS_PHY_78_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C13C 0x10100303  //DDRSS_PHY_79_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C140 0x10101010  //DDRSS_PHY_80_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C144 0x10101010  //DDRSS_PHY_81_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C148 0x00021010  //DDRSS_PHY_82_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C14C 0x00100010  //DDRSS_PHY_83_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C150 0x00100010  //DDRSS_PHY_84_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C154 0x00100010  //DDRSS_PHY_85_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C158 0x00100010  //DDRSS_PHY_86_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C15C 0x02020010  //DDRSS_PHY_87_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C160 0x51515041  //DDRSS_PHY_88_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C164 0x31804000  //DDRSS_PHY_89_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C168 0x04C00340  //DDRSS_PHY_90_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C16C 0x01008080  //DDRSS_PHY_91_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C170 0x04050001  //DDRSS_PHY_92_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C174 0x00000504  //DDRSS_PHY_93_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C178 0x42100010  //DDRSS_PHY_94_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C17C 0x010C053E  //DDRSS_PHY_95_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C180 0x000F0C14  //DDRSS_PHY_96_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C184 0x01000140  //DDRSS_PHY_97_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C188 0x007A0120  //DDRSS_PHY_98_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C18C 0x00000C00  //DDRSS_PHY_99_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C190 0x000001CC  //DDRSS_PHY_100_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C194 0x20100200  //DDRSS_PHY_101_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C198 0x00000005  //DDRSS_PHY_102_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C19C 0x76543210  //DDRSS_PHY_103_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A0 0x00000008  //DDRSS_PHY_104_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A4 0x02800280  //DDRSS_PHY_105_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A8 0x02800280  //DDRSS_PHY_106_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1AC 0x02800280  //DDRSS_PHY_107_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B0 0x02800280  //DDRSS_PHY_108_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B4 0x002A0280  //DDRSS_PHY_109_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B8 0x0000A800  //DDRSS_PHY_110_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1BC 0x00A800AE  //DDRSS_PHY_111_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C0 0x00A800AE  //DDRSS_PHY_112_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C4 0x00B400AE  //DDRSS_PHY_113_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C8 0x00B400B4  //DDRSS_PHY_114_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1CC 0x00A800B4  //DDRSS_PHY_115_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D0 0x00A800AE  //DDRSS_PHY_116_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D4 0x00A800AE  //DDRSS_PHY_117_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D8 0x00A800AE  //DDRSS_PHY_118_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1DC 0x01B200AE  //DDRSS_PHY_119_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E0 0x01000000  //DDRSS_PHY_120_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E4 0x00000000  //DDRSS_PHY_121_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E8 0x00000000  //DDRSS_PHY_122_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1EC 0x00080200  //DDRSS_PHY_123_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F0 0x00000000  //DDRSS_PHY_124_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F4 0x00000000  //DDRSS_PHY_125_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C400 0x04C00000  //DDRSS_PHY_256_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C404 0x00000000  //DDRSS_PHY_257_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C408 0x00000200  //DDRSS_PHY_258_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C40C 0x00000000  //DDRSS_PHY_259_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C410 0x00000000  //DDRSS_PHY_260_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C414 0x00000000  //DDRSS_PHY_261_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C418 0x00000000  //DDRSS_PHY_262_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C41C 0x00000000  //DDRSS_PHY_263_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C420 0x00000001  //DDRSS_PHY_264_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C424 0x00000000  //DDRSS_PHY_265_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C428 0x0A0C0000  //DDRSS_PHY_266_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C42C 0x010101FF  //DDRSS_PHY_267_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C430 0x00010000  //DDRSS_PHY_268_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C434 0x00C04004  //DDRSS_PHY_269_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C438 0x00CC0008  //DDRSS_PHY_270_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C43C 0x00660201  //DDRSS_PHY_271_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C440 0x00000000  //DDRSS_PHY_272_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C444 0x00000000  //DDRSS_PHY_273_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C448 0x00000000  //DDRSS_PHY_274_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C44C 0x0000AAAA  //DDRSS_PHY_275_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C450 0x00005555  //DDRSS_PHY_276_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C454 0x0000B5B5  //DDRSS_PHY_277_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C458 0x00004A4A  //DDRSS_PHY_278_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C45C 0x00005656  //DDRSS_PHY_279_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C460 0x0000A9A9  //DDRSS_PHY_280_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C464 0x0000B7B7  //DDRSS_PHY_281_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C468 0x00004848  //DDRSS_PHY_282_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C46C 0x00000000  //DDRSS_PHY_283_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C470 0x00000000  //DDRSS_PHY_284_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C474 0x08000000  //DDRSS_PHY_285_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C478 0x0F000008  //DDRSS_PHY_286_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C47C 0x00000F0F  //DDRSS_PHY_287_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C480 0x00E4E400  //DDRSS_PHY_288_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C484 0x00070820  //DDRSS_PHY_289_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C488 0x000C0020  //DDRSS_PHY_290_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C48C 0x00062000  //DDRSS_PHY_291_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C490 0x00000000  //DDRSS_PHY_292_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C494 0x55555555  //DDRSS_PHY_293_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C498 0xAAAAAAAA  //DDRSS_PHY_294_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C49C 0x55555555  //DDRSS_PHY_295_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A0 0xAAAAAAAA  //DDRSS_PHY_296_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A4 0x00005555  //DDRSS_PHY_297_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A8 0x01000100  //DDRSS_PHY_298_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4AC 0x00800180  //DDRSS_PHY_299_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B0 0x00000000  //DDRSS_PHY_300_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B4 0x00100000  //DDRSS_PHY_301_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B8 0x00000000  //DDRSS_PHY_302_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4BC 0x14070010  //DDRSS_PHY_303_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C0 0x00000014  //DDRSS_PHY_304_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C4 0x00010600  //DDRSS_PHY_305_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C8 0x0048003C  //DDRSS_PHY_306_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4CC 0x00000FFF  //DDRSS_PHY_307_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D0 0x00000000  //DDRSS_PHY_308_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D4 0x02AC02A0  //DDRSS_PHY_309_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D8 0x00000030  //DDRSS_PHY_310_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4DC 0x01200048  //DDRSS_PHY_311_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E0 0x00000000  //DDRSS_PHY_312_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E4 0x0C000000  //DDRSS_PHY_313_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E8 0x07FF0000  //DDRSS_PHY_314_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4EC 0x00000000  //DDRSS_PHY_315_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F0 0x00000000  //DDRSS_PHY_316_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F4 0x00000000  //DDRSS_PHY_317_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F8 0x00000000  //DDRSS_PHY_318_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4FC 0x00000000  //DDRSS_PHY_319_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C500 0x00000000  //DDRSS_PHY_320_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C504 0x00000004  //DDRSS_PHY_321_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C508 0x00000000  //DDRSS_PHY_322_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C50C 0x00000000  //DDRSS_PHY_323_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C510 0x00000000  //DDRSS_PHY_324_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C514 0x00000000  //DDRSS_PHY_325_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C518 0x00000000  //DDRSS_PHY_326_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C51C 0x00000000  //DDRSS_PHY_327_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C520 0x041F07FF  //DDRSS_PHY_328_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C524 0x00000000  //DDRSS_PHY_329_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C528 0x01CCB001  //DDRSS_PHY_330_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C52C 0x2000CCB0  //DDRSS_PHY_331_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C530 0x20000140  //DDRSS_PHY_332_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C534 0x07FF0200  //DDRSS_PHY_333_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C538 0x0000DD01  //DDRSS_PHY_334_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C53C 0x10100303  //DDRSS_PHY_335_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C540 0x10101010  //DDRSS_PHY_336_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C544 0x10101010  //DDRSS_PHY_337_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C548 0x00021010  //DDRSS_PHY_338_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C54C 0x00100010  //DDRSS_PHY_339_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C550 0x00100010  //DDRSS_PHY_340_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C554 0x00100010  //DDRSS_PHY_341_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C558 0x00100010  //DDRSS_PHY_342_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C55C 0x02020010  //DDRSS_PHY_343_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C560 0x51515041  //DDRSS_PHY_344_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C564 0x31804000  //DDRSS_PHY_345_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C568 0x04C00340  //DDRSS_PHY_346_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C56C 0x01008080  //DDRSS_PHY_347_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C570 0x04050001  //DDRSS_PHY_348_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C574 0x00000504  //DDRSS_PHY_349_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C578 0x42100010  //DDRSS_PHY_350_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C57C 0x010C053E  //DDRSS_PHY_351_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C580 0x000F0C14  //DDRSS_PHY_352_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C584 0x01000140  //DDRSS_PHY_353_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C588 0x007A0120  //DDRSS_PHY_354_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C58C 0x00000C00  //DDRSS_PHY_355_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C590 0x000001CC  //DDRSS_PHY_356_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C594 0x20100200  //DDRSS_PHY_357_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C598 0x00000005  //DDRSS_PHY_358_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C59C 0x76543210  //DDRSS_PHY_359_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A0 0x00000008  //DDRSS_PHY_360_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A4 0x02800280  //DDRSS_PHY_361_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A8 0x02800280  //DDRSS_PHY_362_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5AC 0x02800280  //DDRSS_PHY_363_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B0 0x02800280  //DDRSS_PHY_364_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B4 0x00420280  //DDRSS_PHY_365_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B8 0x0000B400  //DDRSS_PHY_366_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5BC 0x00A800B4  //DDRSS_PHY_367_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C0 0x00A800A8  //DDRSS_PHY_368_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C4 0x00B400A8  //DDRSS_PHY_369_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C8 0x00B400B4  //DDRSS_PHY_370_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5CC 0x00B400B4  //DDRSS_PHY_371_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D0 0x00B400B4  //DDRSS_PHY_372_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D4 0x00AE00B4  //DDRSS_PHY_373_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D8 0x00B400AE  //DDRSS_PHY_374_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5DC 0x01A600B4  //DDRSS_PHY_375_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E0 0x01000000  //DDRSS_PHY_376_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E4 0x00000000  //DDRSS_PHY_377_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E8 0x00000000  //DDRSS_PHY_378_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5EC 0x00080200  //DDRSS_PHY_379_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F0 0x00000000  //DDRSS_PHY_380_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F4 0x00000000  //DDRSS_PHY_381_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C800 0x00000100  //DDRSS_PHY_512_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C804 0x00001000  //DDRSS_PHY_513_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C808 0x00070000  //DDRSS_PHY_514_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C80C 0x00000000  //DDRSS_PHY_515_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C810 0x00000000  //DDRSS_PHY_516_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C814 0x00000100  //DDRSS_PHY_517_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C818 0x00000000  //DDRSS_PHY_518_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C81C 0x00000000  //DDRSS_PHY_519_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C820 0x00000000  //DDRSS_PHY_520_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C824 0x00000000  //DDRSS_PHY_521_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C828 0x00000000  //DDRSS_PHY_522_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C82C 0x00000000  //DDRSS_PHY_523_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C830 0x00000000  //DDRSS_PHY_524_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C834 0x00DCBA98  //DDRSS_PHY_525_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C838 0x00000000  //DDRSS_PHY_526_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C83C 0x00000000  //DDRSS_PHY_527_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C840 0x00000000  //DDRSS_PHY_528_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C844 0x00000000  //DDRSS_PHY_529_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C848 0x00000000  //DDRSS_PHY_530_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C84C 0x00000100  //DDRSS_PHY_531_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C850 0x00000000  //DDRSS_PHY_532_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C854 0x00000000  //DDRSS_PHY_533_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C858 0x00000000  //DDRSS_PHY_534_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C85C 0x00000000  //DDRSS_PHY_535_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C860 0x00000000  //DDRSS_PHY_536_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C864 0x00000000  //DDRSS_PHY_537_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C868 0x00000000  //DDRSS_PHY_538_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C86C 0x00000000  //DDRSS_PHY_539_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C870 0x0A418820  //DDRSS_PHY_540_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C874 0x103F0000  //DDRSS_PHY_541_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C878 0x000F0100  //DDRSS_PHY_542_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C87C 0x0000000F  //DDRSS_PHY_543_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C880 0x020002FF  //DDRSS_PHY_544_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C884 0x00030000  //DDRSS_PHY_545_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C888 0x00000300  //DDRSS_PHY_546_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C88C 0x00000300  //DDRSS_PHY_547_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C890 0x00000300  //DDRSS_PHY_548_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C894 0x00000300  //DDRSS_PHY_549_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C898 0x00000300  //DDRSS_PHY_550_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C89C 0x42080010  //DDRSS_PHY_551_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A0 0x0000003E  //DDRSS_PHY_552_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A4 0x00000000  //DDRSS_PHY_553_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A8 0x00000000  //DDRSS_PHY_554_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC00 0x00000100  //DDRSS_PHY_768_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC04 0x00001000  //DDRSS_PHY_769_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC08 0x00070000  //DDRSS_PHY_770_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC0C 0x00000000  //DDRSS_PHY_771_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC10 0x00000000  //DDRSS_PHY_772_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC14 0x00000100  //DDRSS_PHY_773_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC18 0x00000000  //DDRSS_PHY_774_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC1C 0x00000000  //DDRSS_PHY_775_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC20 0x00000000  //DDRSS_PHY_776_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC24 0x00000000  //DDRSS_PHY_777_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC28 0x00000000  //DDRSS_PHY_778_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC2C 0x00000000  //DDRSS_PHY_779_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC30 0x00000000  //DDRSS_PHY_780_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC34 0x00DCBA98  //DDRSS_PHY_781_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC38 0x00000000  //DDRSS_PHY_782_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC3C 0x00000000  //DDRSS_PHY_783_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC40 0x00000000  //DDRSS_PHY_784_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC44 0x00000000  //DDRSS_PHY_785_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC48 0x00000000  //DDRSS_PHY_786_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC4C 0x00000100  //DDRSS_PHY_787_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC50 0x00000000  //DDRSS_PHY_788_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC54 0x00000000  //DDRSS_PHY_789_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC58 0x00000000  //DDRSS_PHY_790_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC5C 0x00000000  //DDRSS_PHY_791_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC60 0x00000000  //DDRSS_PHY_792_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC64 0x00000000  //DDRSS_PHY_793_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC68 0x00000000  //DDRSS_PHY_794_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC6C 0x00000000  //DDRSS_PHY_795_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC70 0x16A4A0E6  //DDRSS_PHY_796_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC74 0x103F0000  //DDRSS_PHY_797_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC78 0x000F0000  //DDRSS_PHY_798_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC7C 0x0000000F  //DDRSS_PHY_799_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC80 0x020002FF  //DDRSS_PHY_800_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC84 0x00030000  //DDRSS_PHY_801_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC88 0x00000300  //DDRSS_PHY_802_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC8C 0x00000300  //DDRSS_PHY_803_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC90 0x00000300  //DDRSS_PHY_804_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC94 0x00000300  //DDRSS_PHY_805_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC98 0x00000300  //DDRSS_PHY_806_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC9C 0x42080010  //DDRSS_PHY_807_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA0 0x0000003E  //DDRSS_PHY_808_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA4 0x00000000  //DDRSS_PHY_809_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA8 0x00000000  //DDRSS_PHY_810_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D000 0x00000100  //DDRSS_PHY_1024_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D004 0x00001000  //DDRSS_PHY_1025_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D008 0x00070000  //DDRSS_PHY_1026_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D00C 0x00000000  //DDRSS_PHY_1027_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D010 0x00000000  //DDRSS_PHY_1028_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D014 0x00000100  //DDRSS_PHY_1029_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D018 0x00000000  //DDRSS_PHY_1030_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D01C 0x00000000  //DDRSS_PHY_1031_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D020 0x00000000  //DDRSS_PHY_1032_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D024 0x00000000  //DDRSS_PHY_1033_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D028 0x00000000  //DDRSS_PHY_1034_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D02C 0x00000000  //DDRSS_PHY_1035_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D030 0x00000000  //DDRSS_PHY_1036_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D034 0x00DCBA98  //DDRSS_PHY_1037_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D038 0x00000000  //DDRSS_PHY_1038_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D03C 0x00000000  //DDRSS_PHY_1039_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D040 0x00000000  //DDRSS_PHY_1040_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D044 0x00000000  //DDRSS_PHY_1041_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D048 0x00000000  //DDRSS_PHY_1042_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D04C 0x00000100  //DDRSS_PHY_1043_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D050 0x00000000  //DDRSS_PHY_1044_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D054 0x00000000  //DDRSS_PHY_1045_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D058 0x00000000  //DDRSS_PHY_1046_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D05C 0x00000000  //DDRSS_PHY_1047_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D060 0x00000000  //DDRSS_PHY_1048_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D064 0x00000000  //DDRSS_PHY_1049_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D068 0x00000000  //DDRSS_PHY_1050_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D06C 0x00000000  //DDRSS_PHY_1051_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D070 0x2307B9AC  //DDRSS_PHY_1052_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D074 0x10030000  //DDRSS_PHY_1053_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D078 0x000F0000  //DDRSS_PHY_1054_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D07C 0x0000000F  //DDRSS_PHY_1055_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D080 0x020002FF  //DDRSS_PHY_1056_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D084 0x00030000  //DDRSS_PHY_1057_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D088 0x00000300  //DDRSS_PHY_1058_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D08C 0x00000300  //DDRSS_PHY_1059_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D090 0x00000300  //DDRSS_PHY_1060_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D094 0x00000300  //DDRSS_PHY_1061_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D098 0x00000300  //DDRSS_PHY_1062_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D09C 0x42080010  //DDRSS_PHY_1063_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A0 0x0000003E  //DDRSS_PHY_1064_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A4 0x00000000  //DDRSS_PHY_1065_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A8 0x00000000  //DDRSS_PHY_1066_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D400 0x00000000  //DDRSS_PHY_1280_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D404 0x00000000  //DDRSS_PHY_1281_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D408 0x00000000  //DDRSS_PHY_1282_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D40C 0x00000000  //DDRSS_PHY_1283_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D410 0x00000000  //DDRSS_PHY_1284_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D414 0x00000000  //DDRSS_PHY_1285_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D418 0x00050000  //DDRSS_PHY_1286_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D41C 0x04000100  //DDRSS_PHY_1287_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D420 0x00000055  //DDRSS_PHY_1288_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D424 0x00000000  //DDRSS_PHY_1289_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D428 0x06800000  //DDRSS_PHY_1290_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D42C 0x00000000  //DDRSS_PHY_1291_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D430 0x00000000  //DDRSS_PHY_1292_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D434 0x01002000  //DDRSS_PHY_1293_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D438 0x00004001  //DDRSS_PHY_1294_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D43C 0x00020028  //DDRSS_PHY_1295_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D440 0x00010100  //DDRSS_PHY_1296_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D444 0x00000001  //DDRSS_PHY_1297_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D448 0x00000000  //DDRSS_PHY_1298_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D44C 0x0F0F0E06  //DDRSS_PHY_1299_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D450 0x00010101  //DDRSS_PHY_1300_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D454 0x010F0004  //DDRSS_PHY_1301_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D458 0x00000000  //DDRSS_PHY_1302_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D45C 0x20125770  //DDRSS_PHY_1303_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D460 0x00000064  //DDRSS_PHY_1304_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D464 0x00000000  //DDRSS_PHY_1305_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D468 0x00000000  //DDRSS_PHY_1306_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D46C 0x01020103  //DDRSS_PHY_1307_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D470 0x03020102  //DDRSS_PHY_1308_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D474 0x03030303  //DDRSS_PHY_1309_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D478 0x03030303  //DDRSS_PHY_1310_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D47C 0x00040000  //DDRSS_PHY_1311_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D480 0x00005201  //DDRSS_PHY_1312_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D484 0x00000003  //DDRSS_PHY_1313_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D488 0x00010000  //DDRSS_PHY_1314_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D48C 0x00000000  //DDRSS_PHY_1315_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D490 0x00000003  //DDRSS_PHY_1316_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D494 0x00010000  //DDRSS_PHY_1317_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D498 0x00000000  //DDRSS_PHY_1318_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D49C 0x07070001  //DDRSS_PHY_1319_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A0 0x00005400  //DDRSS_PHY_1320_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A4 0x000040A2  //DDRSS_PHY_1321_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A8 0x00034890  //DDRSS_PHY_1322_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4AC 0x00014890  //DDRSS_PHY_1323_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B0 0x00014890  //DDRSS_PHY_1324_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B4 0x00014890  //DDRSS_PHY_1325_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B8 0x0001488F  //DDRSS_PHY_1326_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4BC 0x00014890  //DDRSS_PHY_1327_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C0 0x0001491E  //DDRSS_PHY_1328_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C4 0x0001491E  //DDRSS_PHY_1329_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C8 0x00014890  //DDRSS_PHY_1330_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4CC 0x00014890  //DDRSS_PHY_1331_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D0 0x00000000  //DDRSS_PHY_1332_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D4 0x00000046  //DDRSS_PHY_1333_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D8 0x00000400  //DDRSS_PHY_1334_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4DC 0x00000008  //DDRSS_PHY_1335_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E0 0x00814890  //DDRSS_PHY_1336_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E4 0x0081491E  //DDRSS_PHY_1337_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E8 0x00148900  //DDRSS_PHY_1338_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4EC 0x001491E8  //DDRSS_PHY_1339_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F0 0x00F4890F  //DDRSS_PHY_1340_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F4 0x03F491EF  //DDRSS_PHY_1341_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F8 0x00000000  //DDRSS_PHY_1342_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4FC 0x00000000  //DDRSS_PHY_1343_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D500 0xB3000000  //DDRSS_PHY_1344_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D504 0x04102006  //DDRSS_PHY_1345_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D508 0x00041020  //DDRSS_PHY_1346_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D50C 0x01C98C98  //DDRSS_PHY_1347_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D510 0x3F400000  //DDRSS_PHY_1348_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D514 0x3F3F1F3F  //DDRSS_PHY_1349_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D518 0x0000001F  //DDRSS_PHY_1350_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D51C 0x00000000  //DDRSS_PHY_1351_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D520 0x00000000  //DDRSS_PHY_1352_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D524 0x00000000  //DDRSS_PHY_1353_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D528 0x00000001  //DDRSS_PHY_1354_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D52C 0x00000000  //DDRSS_PHY_1355_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D530 0x00000000  //DDRSS_PHY_1356_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D534 0x00000000  //DDRSS_PHY_1357_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D538 0x00000000  //DDRSS_PHY_1358_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D53C 0x76543210  //DDRSS_PHY_1359_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D540 0x00000098  //DDRSS_PHY_1360_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D544 0x00000000  //DDRSS_PHY_1361_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D548 0x00000000  //DDRSS_PHY_1362_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D54C 0x00000000  //DDRSS_PHY_1363_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D550 0x00040700  //DDRSS_PHY_1364_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D554 0x00000000  //DDRSS_PHY_1365_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D558 0x00000000  //DDRSS_PHY_1366_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D55C 0x00000000  //DDRSS_PHY_1367_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D560 0x030F7102  //DDRSS_PHY_1368_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D564 0x00000100  //DDRSS_PHY_1369_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D568 0x00000000  //DDRSS_PHY_1370_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D56C 0x0001F7C2  //DDRSS_PHY_1371_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D570 0x00020002  //DDRSS_PHY_1372_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D574 0x00000000  //DDRSS_PHY_1373_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D578 0x00001142  //DDRSS_PHY_1374_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D57C 0x03020400  //DDRSS_PHY_1375_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D580 0x00000080  //DDRSS_PHY_1376_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D584 0x03900390  //DDRSS_PHY_1377_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D588 0x03900390  //DDRSS_PHY_1378_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D58C 0x03900390  //DDRSS_PHY_1379_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D590 0x03900390  //DDRSS_PHY_1380_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D594 0x03900390  //DDRSS_PHY_1381_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D598 0x03900390  //DDRSS_PHY_1382_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D59C 0x00000300  //DDRSS_PHY_1383_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A0 0x00000300  //DDRSS_PHY_1384_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A4 0x00000300  //DDRSS_PHY_1385_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A8 0x00000300  //DDRSS_PHY_1386_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5AC 0x31823FF7  //DDRSS_PHY_1387_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B0 0x00000000  //DDRSS_PHY_1388_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B4 0x0C000D3F  //DDRSS_PHY_1389_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B8 0x30000D3F  //DDRSS_PHY_1390_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5BC 0x300D3F11  //DDRSS_PHY_1391_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C0 0x01FF0000  //DDRSS_PHY_1392_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C4 0x000D3FFF  //DDRSS_PHY_1393_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C8 0x00000C11  //DDRSS_PHY_1394_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5CC 0x300D3F11  //DDRSS_PHY_1395_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D0 0x01FF0000  //DDRSS_PHY_1396_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D4 0x300C3F11  //DDRSS_PHY_1397_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D8 0x01FF0000  //DDRSS_PHY_1398_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5DC 0x300C3F11  //DDRSS_PHY_1399_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E0 0x01FF0000  //DDRSS_PHY_1400_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E4 0x300D3F11  //DDRSS_PHY_1401_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E8 0x01FF0000  //DDRSS_PHY_1402_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5EC 0x300D3F11  //DDRSS_PHY_1403_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F0 0x01FF0000  //DDRSS_PHY_1404_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F4 0x20040004  //DDRSS_PHY_1405_DATA_F0

And here is the register dump when DDR test program already run several cycles of write and read:

MAIN_Cortex_R5_0_0: GEL Output: 0x0F308000 0x10460A01  //DDRSS_CTL_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308004 0x5D1AF3C3  //DDRSS_CTL_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308008 0x0171A610  //DDRSS_CTL_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30800C 0x40020A11  //DDRSS_CTL_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308010 0x00052006  //DDRSS_CTL_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308014 0x02050020  //DDRSS_CTL_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308018 0x03070101  //DDRSS_CTL_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30801C 0x00089070  //DDRSS_CTL_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308020 0x00000000  //DDRSS_CTL_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308024 0x00000000  //DDRSS_CTL_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308028 0x00000000  //DDRSS_CTL_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30802C 0x00089070  //DDRSS_CTL_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308030 0x00000000  //DDRSS_CTL_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308034 0x00000000  //DDRSS_CTL_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308038 0x00000000  //DDRSS_CTL_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30803C 0x00089070  //DDRSS_CTL_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308040 0x00000000  //DDRSS_CTL_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308044 0x00000000  //DDRSS_CTL_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308048 0x00000000  //DDRSS_CTL_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30804C 0x01010100  //DDRSS_CTL_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308050 0x01000101  //DDRSS_CTL_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308054 0x01000110  //DDRSS_CTL_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308058 0x02010002  //DDRSS_CTL_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30805C 0x00027100  //DDRSS_CTL_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308060 0x00061A80  //DDRSS_CTL_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308064 0x02550255  //DDRSS_CTL_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308068 0x00000255  //DDRSS_CTL_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30806C 0x00000000  //DDRSS_CTL_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308070 0x00000000  //DDRSS_CTL_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308074 0x00000000  //DDRSS_CTL_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308078 0x00000000  //DDRSS_CTL_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30807C 0x00000000  //DDRSS_CTL_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308080 0x00000000  //DDRSS_CTL_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308084 0x00000000  //DDRSS_CTL_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308088 0x00000000  //DDRSS_CTL_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30808C 0x00000000  //DDRSS_CTL_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308090 0x00000000  //DDRSS_CTL_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308094 0x00000000  //DDRSS_CTL_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308098 0x04000B16  //DDRSS_CTL_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30809C 0x1C1C1C1C  //DDRSS_CTL_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A0 0x04000B16  //DDRSS_CTL_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A4 0x1C1C1C1C  //DDRSS_CTL_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A8 0x04000B16  //DDRSS_CTL_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080AC 0x1C1C1C1C  //DDRSS_CTL_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B0 0x05050404  //DDRSS_CTL_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B4 0x00002706  //DDRSS_CTL_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B8 0x0602001D  //DDRSS_CTL_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080BC 0x05001D0B  //DDRSS_CTL_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C0 0x00270605  //DDRSS_CTL_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C4 0x0602001D  //DDRSS_CTL_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C8 0x05001D0B  //DDRSS_CTL_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080CC 0x00270605  //DDRSS_CTL_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D0 0x0602001D  //DDRSS_CTL_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D4 0x07001D0B  //DDRSS_CTL_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D8 0x00180807  //DDRSS_CTL_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080DC 0x0400DB60  //DDRSS_CTL_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E0 0x07070009  //DDRSS_CTL_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E4 0x00001808  //DDRSS_CTL_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E8 0x0400DB60  //DDRSS_CTL_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080EC 0x07070009  //DDRSS_CTL_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F0 0x00001808  //DDRSS_CTL_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F4 0x0400DB60  //DDRSS_CTL_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F8 0x03000009  //DDRSS_CTL_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080FC 0x0D0C0002  //DDRSS_CTL_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308100 0x0D0C0D0C  //DDRSS_CTL_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308104 0x01010000  //DDRSS_CTL_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308108 0x03191919  //DDRSS_CTL_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30810C 0x0B0B0B0B  //DDRSS_CTL_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308110 0x00000B0B  //DDRSS_CTL_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308114 0x00000101  //DDRSS_CTL_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308118 0x00000000  //DDRSS_CTL_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30811C 0x01000000  //DDRSS_CTL_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308120 0x00D00803  //DDRSS_CTL_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308124 0x00001860  //DDRSS_CTL_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308128 0x000000D0  //DDRSS_CTL_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30812C 0x00001860  //DDRSS_CTL_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308130 0x000000D0  //DDRSS_CTL_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308134 0x00001860  //DDRSS_CTL_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308138 0x00000005  //DDRSS_CTL_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30813C 0x00000000  //DDRSS_CTL_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308140 0x00000000  //DDRSS_CTL_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308144 0x00000000  //DDRSS_CTL_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308148 0x00000000  //DDRSS_CTL_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30814C 0x00000000  //DDRSS_CTL_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308150 0x00000000  //DDRSS_CTL_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308154 0x00000000  //DDRSS_CTL_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308158 0x00000000  //DDRSS_CTL_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30815C 0x00090009  //DDRSS_CTL_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308160 0x00000009  //DDRSS_CTL_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308164 0x00000000  //DDRSS_CTL_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308168 0x00000000  //DDRSS_CTL_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30816C 0x00000000  //DDRSS_CTL_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308170 0x00000000  //DDRSS_CTL_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308174 0x00000000  //DDRSS_CTL_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308178 0x00010001  //DDRSS_CTL_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30817C 0x00025501  //DDRSS_CTL_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308180 0x025500D8  //DDRSS_CTL_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308184 0x025500D8  //DDRSS_CTL_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308188 0x00D800D8  //DDRSS_CTL_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30818C 0x00D800D8  //DDRSS_CTL_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308190 0x00000000  //DDRSS_CTL_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308194 0x00000000  //DDRSS_CTL_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308198 0x00000000  //DDRSS_CTL_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30819C 0x00000000  //DDRSS_CTL_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A0 0x00000000  //DDRSS_CTL_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A4 0x00000000  //DDRSS_CTL_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A8 0x03010000  //DDRSS_CTL_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081AC 0x00010000  //DDRSS_CTL_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B0 0x00000000  //DDRSS_CTL_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B4 0x01000000  //DDRSS_CTL_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B8 0x80104002  //DDRSS_CTL_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081BC 0x00040003  //DDRSS_CTL_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C0 0x00040005  //DDRSS_CTL_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C4 0x00030000  //DDRSS_CTL_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C8 0x00050004  //DDRSS_CTL_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081CC 0x00000004  //DDRSS_CTL_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D0 0x00040003  //DDRSS_CTL_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D4 0x00040005  //DDRSS_CTL_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D8 0x00000000  //DDRSS_CTL_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081DC 0x00061800  //DDRSS_CTL_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E0 0x00061800  //DDRSS_CTL_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E4 0x00061800  //DDRSS_CTL_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E8 0x00061800  //DDRSS_CTL_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081EC 0x00061800  //DDRSS_CTL_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F0 0x00000000  //DDRSS_CTL_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F4 0x0000AAA0  //DDRSS_CTL_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F8 0x00061800  //DDRSS_CTL_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081FC 0x00061800  //DDRSS_CTL_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308200 0x00061800  //DDRSS_CTL_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308204 0x00061800  //DDRSS_CTL_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308208 0x00061800  //DDRSS_CTL_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30820C 0x00000000  //DDRSS_CTL_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308210 0x0000AAA0  //DDRSS_CTL_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308214 0x00061800  //DDRSS_CTL_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308218 0x00061800  //DDRSS_CTL_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30821C 0x00061800  //DDRSS_CTL_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308220 0x00061800  //DDRSS_CTL_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308224 0x00061800  //DDRSS_CTL_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308228 0x00000000  //DDRSS_CTL_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30822C 0x0000AAA0  //DDRSS_CTL_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308230 0x00000000  //DDRSS_CTL_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308234 0x00000000  //DDRSS_CTL_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308238 0x00000000  //DDRSS_CTL_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30823C 0x00000000  //DDRSS_CTL_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308240 0x00000000  //DDRSS_CTL_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308244 0x00000000  //DDRSS_CTL_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308248 0x00000000  //DDRSS_CTL_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30824C 0x00000000  //DDRSS_CTL_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308250 0x00000000  //DDRSS_CTL_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308254 0x00000000  //DDRSS_CTL_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308258 0x00000000  //DDRSS_CTL_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30825C 0x00000000  //DDRSS_CTL_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308260 0x00000000  //DDRSS_CTL_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308264 0x00000000  //DDRSS_CTL_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308268 0x00000000  //DDRSS_CTL_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30826C 0x00000000  //DDRSS_CTL_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308270 0x080C0000  //DDRSS_CTL_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308274 0x080C080C  //DDRSS_CTL_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308278 0x00000000  //DDRSS_CTL_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30827C 0x07010A09  //DDRSS_CTL_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308280 0x000E0A09  //DDRSS_CTL_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308284 0x010A0900  //DDRSS_CTL_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308288 0x0E0A0907  //DDRSS_CTL_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30828C 0x0A090000  //DDRSS_CTL_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308290 0x0A090701  //DDRSS_CTL_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308294 0x0000080E  //DDRSS_CTL_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308298 0x00040003  //DDRSS_CTL_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30829C 0x00004007  //DDRSS_CTL_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A0 0x00000000  //DDRSS_CTL_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A4 0x00000000  //DDRSS_CTL_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A8 0x00000000  //DDRSS_CTL_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082AC 0x00000000  //DDRSS_CTL_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B0 0x00000000  //DDRSS_CTL_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B4 0x00000000  //DDRSS_CTL_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B8 0x01000000  //DDRSS_CTL_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082BC 0x00000000  //DDRSS_CTL_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C0 0x00001500  //DDRSS_CTL_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C4 0x0000100E  //DDRSS_CTL_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C8 0x00000000  //DDRSS_CTL_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082CC 0x00000000  //DDRSS_CTL_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D0 0x00000001  //DDRSS_CTL_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D4 0x00000002  //DDRSS_CTL_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D8 0x00000C00  //DDRSS_CTL_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082DC 0x00001000  //DDRSS_CTL_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E0 0x00000C00  //DDRSS_CTL_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E4 0x00001000  //DDRSS_CTL_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E8 0x00000C00  //DDRSS_CTL_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082EC 0x00001000  //DDRSS_CTL_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F0 0x00000000  //DDRSS_CTL_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F4 0x00000000  //DDRSS_CTL_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F8 0x00000000  //DDRSS_CTL_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082FC 0x00000000  //DDRSS_CTL_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308300 0x00000000  //DDRSS_CTL_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308304 0x00000000  //DDRSS_CTL_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308308 0x00000000  //DDRSS_CTL_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30830C 0x00000000  //DDRSS_CTL_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308310 0x00000000  //DDRSS_CTL_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308314 0x00000000  //DDRSS_CTL_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308318 0x00000000  //DDRSS_CTL_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30831C 0x00000000  //DDRSS_CTL_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308320 0x00000000  //DDRSS_CTL_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308324 0x00000000  //DDRSS_CTL_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308328 0x00000000  //DDRSS_CTL_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30832C 0x00000000  //DDRSS_CTL_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308330 0x00041000  //DDRSS_CTL_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308334 0x00000503  //DDRSS_CTL_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308338 0x00000010  //DDRSS_CTL_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30833C 0x00000410  //DDRSS_CTL_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308340 0x00000503  //DDRSS_CTL_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308344 0x00000010  //DDRSS_CTL_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308348 0x00000410  //DDRSS_CTL_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30834C 0x00000503  //DDRSS_CTL_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308350 0x00000010  //DDRSS_CTL_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308354 0x00000410  //DDRSS_CTL_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308358 0x00000503  //DDRSS_CTL_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30835C 0x00000010  //DDRSS_CTL_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308360 0x00000410  //DDRSS_CTL_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308364 0x00000503  //DDRSS_CTL_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308368 0x00000010  //DDRSS_CTL_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30836C 0x00000410  //DDRSS_CTL_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308370 0x00000503  //DDRSS_CTL_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308374 0x00000010  //DDRSS_CTL_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308378 0x00000000  //DDRSS_CTL_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30837C 0x00000000  //DDRSS_CTL_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308380 0x00000000  //DDRSS_CTL_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308384 0x00000000  //DDRSS_CTL_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308388 0x00000000  //DDRSS_CTL_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30838C 0x00000000  //DDRSS_CTL_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308390 0x00000000  //DDRSS_CTL_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308394 0x00000000  //DDRSS_CTL_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308398 0x00000000  //DDRSS_CTL_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30839C 0x00000000  //DDRSS_CTL_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A0 0x00000000  //DDRSS_CTL_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A4 0x00000000  //DDRSS_CTL_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A8 0x00000000  //DDRSS_CTL_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083AC 0x00000000  //DDRSS_CTL_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B0 0x00001401  //DDRSS_CTL_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B4 0x00001401  //DDRSS_CTL_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B8 0x00001401  //DDRSS_CTL_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083BC 0x00001401  //DDRSS_CTL_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C0 0x00001401  //DDRSS_CTL_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C4 0x00001401  //DDRSS_CTL_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C8 0x00000493  //DDRSS_CTL_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083CC 0x00000493  //DDRSS_CTL_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D0 0x00000493  //DDRSS_CTL_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D4 0x00000493  //DDRSS_CTL_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D8 0x00000493  //DDRSS_CTL_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083DC 0x00000493  //DDRSS_CTL_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E0 0x00000000  //DDRSS_CTL_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E4 0x00000000  //DDRSS_CTL_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E8 0x00000000  //DDRSS_CTL_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083EC 0x00000000  //DDRSS_CTL_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F0 0x00000000  //DDRSS_CTL_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F4 0x00000000  //DDRSS_CTL_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F8 0x00000000  //DDRSS_CTL_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083FC 0x00000000  //DDRSS_CTL_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308400 0x00000000  //DDRSS_CTL_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308404 0x00000000  //DDRSS_CTL_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308408 0x00000000  //DDRSS_CTL_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30840C 0x00000000  //DDRSS_CTL_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308410 0x00000000  //DDRSS_CTL_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308414 0x00000000  //DDRSS_CTL_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308418 0x00000000  //DDRSS_CTL_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30841C 0x00000000  //DDRSS_CTL_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308420 0x00000000  //DDRSS_CTL_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308424 0x00000000  //DDRSS_CTL_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308428 0x00000000  //DDRSS_CTL_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30842C 0x00000000  //DDRSS_CTL_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308430 0x00000000  //DDRSS_CTL_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308434 0x00000000  //DDRSS_CTL_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308438 0x00000000  //DDRSS_CTL_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30843C 0x00000000  //DDRSS_CTL_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308440 0x00000000  //DDRSS_CTL_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308444 0x00000000  //DDRSS_CTL_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308448 0x00000000  //DDRSS_CTL_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30844C 0x00000000  //DDRSS_CTL_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308450 0x00000000  //DDRSS_CTL_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308454 0x00010000  //DDRSS_CTL_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308458 0x00000000  //DDRSS_CTL_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30845C 0x00000100  //DDRSS_CTL_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308460 0x00000000  //DDRSS_CTL_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308464 0x00000101  //DDRSS_CTL_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308468 0x00000000  //DDRSS_CTL_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30846C 0x00000000  //DDRSS_CTL_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308470 0x00000000  //DDRSS_CTL_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308474 0x00000000  //DDRSS_CTL_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308478 0x00000000  //DDRSS_CTL_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30847C 0x00000000  //DDRSS_CTL_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308480 0x00000000  //DDRSS_CTL_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308484 0x00000FFF  //DDRSS_CTL_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308488 0x0C181511  //DDRSS_CTL_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30848C 0x00000304  //DDRSS_CTL_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308490 0x00000000  //DDRSS_CTL_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308494 0x00000000  //DDRSS_CTL_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308498 0x00000000  //DDRSS_CTL_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30849C 0x00000000  //DDRSS_CTL_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A0 0x00000000  //DDRSS_CTL_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A4 0x00000000  //DDRSS_CTL_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A8 0x00000000  //DDRSS_CTL_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084AC 0x00000000  //DDRSS_CTL_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B0 0x00000000  //DDRSS_CTL_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B4 0x00000000  //DDRSS_CTL_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B8 0x00000000  //DDRSS_CTL_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084BC 0x00000000  //DDRSS_CTL_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C0 0x00000000  //DDRSS_CTL_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C4 0x00040000  //DDRSS_CTL_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C8 0x00800200  //DDRSS_CTL_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084CC 0x00000000  //DDRSS_CTL_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D0 0x02000400  //DDRSS_CTL_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D4 0x00000080  //DDRSS_CTL_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D8 0x00040000  //DDRSS_CTL_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084DC 0x00800200  //DDRSS_CTL_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E0 0x00000000  //DDRSS_CTL_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E4 0x00000000  //DDRSS_CTL_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E8 0x00000000  //DDRSS_CTL_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084EC 0x00000100  //DDRSS_CTL_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F0 0x01010000  //DDRSS_CTL_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F4 0x00000202  //DDRSS_CTL_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F8 0x0FFF0000  //DDRSS_CTL_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084FC 0x000FFF00  //DDRSS_CTL_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308500 0xFFFFFFFF  //DDRSS_CTL_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308504 0x00FFFF00  //DDRSS_CTL_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308508 0x0A000000  //DDRSS_CTL_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30850C 0x0001FFFF  //DDRSS_CTL_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308510 0x01010101  //DDRSS_CTL_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308514 0x01010101  //DDRSS_CTL_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308518 0x00000118  //DDRSS_CTL_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30851C 0x00000C01  //DDRSS_CTL_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308520 0x00000000  //DDRSS_CTL_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308524 0x00000000  //DDRSS_CTL_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308528 0x00000000  //DDRSS_CTL_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30852C 0x01000000  //DDRSS_CTL_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308530 0x00000100  //DDRSS_CTL_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308534 0x00010000  //DDRSS_CTL_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308538 0x00000000  //DDRSS_CTL_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30853C 0x00000000  //DDRSS_CTL_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308540 0x00000000  //DDRSS_CTL_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308544 0x00000000  //DDRSS_CTL_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308548 0x00000000  //DDRSS_CTL_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30854C 0x00000000  //DDRSS_CTL_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308550 0x00000000  //DDRSS_CTL_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308554 0x00000000  //DDRSS_CTL_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308558 0x00000000  //DDRSS_CTL_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30855C 0x00000000  //DDRSS_CTL_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308560 0x00000000  //DDRSS_CTL_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308564 0x00000000  //DDRSS_CTL_345_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308568 0x00000000  //DDRSS_CTL_346_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30856C 0x00000000  //DDRSS_CTL_347_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308570 0x00000000  //DDRSS_CTL_348_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308574 0x00000000  //DDRSS_CTL_349_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308578 0x00000000  //DDRSS_CTL_350_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30857C 0x00000000  //DDRSS_CTL_351_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308580 0x00000000  //DDRSS_CTL_352_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308584 0x00000000  //DDRSS_CTL_353_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308588 0x00000000  //DDRSS_CTL_354_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30858C 0x00000000  //DDRSS_CTL_355_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308590 0x00000000  //DDRSS_CTL_356_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308594 0x00000000  //DDRSS_CTL_357_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308598 0x00000000  //DDRSS_CTL_358_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30859C 0x00000000  //DDRSS_CTL_359_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A0 0x00000000  //DDRSS_CTL_360_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A4 0x00000000  //DDRSS_CTL_361_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A8 0x00000000  //DDRSS_CTL_362_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085AC 0x00000000  //DDRSS_CTL_363_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B0 0x00000000  //DDRSS_CTL_364_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B4 0x00000003  //DDRSS_CTL_365_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B8 0x00000003  //DDRSS_CTL_366_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085BC 0x0000AB50  //DDRSS_CTL_367_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C0 0x00000000  //DDRSS_CTL_368_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C4 0x00000000  //DDRSS_CTL_369_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C8 0x0E000000  //DDRSS_CTL_370_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085CC 0x060E0606  //DDRSS_CTL_371_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D0 0x06060E06  //DDRSS_CTL_372_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D4 0x00010101  //DDRSS_CTL_373_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D8 0x02000000  //DDRSS_CTL_374_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085DC 0x00020101  //DDRSS_CTL_375_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E0 0x00000000  //DDRSS_CTL_376_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E4 0x02020200  //DDRSS_CTL_377_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E8 0x02020202  //DDRSS_CTL_378_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085EC 0x02020202  //DDRSS_CTL_379_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F0 0x02020202  //DDRSS_CTL_380_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F4 0x00000000  //DDRSS_CTL_381_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F8 0x00000000  //DDRSS_CTL_382_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085FC 0x04000100  //DDRSS_CTL_383_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308600 0x1E000304  //DDRSS_CTL_384_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308604 0x000030C0  //DDRSS_CTL_385_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308608 0x00000200  //DDRSS_CTL_386_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30860C 0x00000200  //DDRSS_CTL_387_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308610 0x00000200  //DDRSS_CTL_388_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308614 0x00000200  //DDRSS_CTL_389_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308618 0x0000DB60  //DDRSS_CTL_390_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30861C 0x0001E780  //DDRSS_CTL_391_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308620 0x090A0302  //DDRSS_CTL_392_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308624 0x001E0B0C  //DDRSS_CTL_393_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308628 0x000030C0  //DDRSS_CTL_394_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30862C 0x00000200  //DDRSS_CTL_395_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308630 0x00000200  //DDRSS_CTL_396_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308634 0x00000200  //DDRSS_CTL_397_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308638 0x00000200  //DDRSS_CTL_398_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30863C 0x0000DB60  //DDRSS_CTL_399_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308640 0x0001E780  //DDRSS_CTL_400_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308644 0x090A0302  //DDRSS_CTL_401_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308648 0x001E0B0C  //DDRSS_CTL_402_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30864C 0x000030C0  //DDRSS_CTL_403_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308650 0x00000200  //DDRSS_CTL_404_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308654 0x00000200  //DDRSS_CTL_405_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308658 0x00000200  //DDRSS_CTL_406_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30865C 0x00000200  //DDRSS_CTL_407_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308660 0x0000DB60  //DDRSS_CTL_408_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308664 0x0001E780  //DDRSS_CTL_409_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308668 0x090A0302  //DDRSS_CTL_410_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30866C 0x00000B0C  //DDRSS_CTL_411_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308670 0x00000000  //DDRSS_CTL_412_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308674 0x0302000A  //DDRSS_CTL_413_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308678 0x01000500  //DDRSS_CTL_414_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30867C 0x01010001  //DDRSS_CTL_415_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308680 0x00010001  //DDRSS_CTL_416_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308684 0x01010001  //DDRSS_CTL_417_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308688 0x02010000  //DDRSS_CTL_418_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30868C 0x00000200  //DDRSS_CTL_419_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308690 0x02000201  //DDRSS_CTL_420_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308694 0x00000000  //DDRSS_CTL_421_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308698 0x00202020  //DDRSS_CTL_422_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A000 0x00000A01  //DDRSS_PI_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A004 0xAE8D79E2  //DDRSS_PI_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A008 0x0714B570  //DDRSS_PI_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A00C 0x01011387  //DDRSS_PI_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A010 0x00000001  //DDRSS_PI_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A014 0x00010064  //DDRSS_PI_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A018 0x00000000  //DDRSS_PI_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A01C 0x00000000  //DDRSS_PI_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A020 0x00000000  //DDRSS_PI_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A024 0x00000000  //DDRSS_PI_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A028 0x00000000  //DDRSS_PI_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A02C 0x00000000  //DDRSS_PI_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A030 0x00000000  //DDRSS_PI_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A034 0x00010001  //DDRSS_PI_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A038 0x00000000  //DDRSS_PI_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A03C 0x00010001  //DDRSS_PI_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A040 0x00000005  //DDRSS_PI_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A044 0x00010000  //DDRSS_PI_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A048 0x00000000  //DDRSS_PI_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A04C 0x00000000  //DDRSS_PI_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A050 0x00000000  //DDRSS_PI_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A054 0x00000000  //DDRSS_PI_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A058 0x00000000  //DDRSS_PI_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A05C 0x00000000  //DDRSS_PI_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A060 0x280D0001  //DDRSS_PI_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A064 0x00000000  //DDRSS_PI_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A068 0x00010000  //DDRSS_PI_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A06C 0x00003200  //DDRSS_PI_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A070 0x00000000  //DDRSS_PI_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A074 0x00000000  //DDRSS_PI_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A078 0x00060602  //DDRSS_PI_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A07C 0x00000000  //DDRSS_PI_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A080 0x00000000  //DDRSS_PI_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A084 0x00000000  //DDRSS_PI_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A088 0x00000001  //DDRSS_PI_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A08C 0x00000055  //DDRSS_PI_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A090 0x000000AA  //DDRSS_PI_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A094 0x000000AD  //DDRSS_PI_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A098 0x00000052  //DDRSS_PI_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A09C 0x0000006A  //DDRSS_PI_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A0 0x00000095  //DDRSS_PI_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A4 0x00000095  //DDRSS_PI_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A8 0x000000AD  //DDRSS_PI_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0AC 0x00000000  //DDRSS_PI_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B0 0x00000000  //DDRSS_PI_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B4 0x00010100  //DDRSS_PI_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B8 0x00000014  //DDRSS_PI_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0BC 0x000007D0  //DDRSS_PI_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C0 0x00000300  //DDRSS_PI_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C4 0x00000000  //DDRSS_PI_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C8 0x00000000  //DDRSS_PI_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0CC 0x01000000  //DDRSS_PI_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D0 0x00010101  //DDRSS_PI_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D4 0x01000B09  //DDRSS_PI_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D8 0x00000000  //DDRSS_PI_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0DC 0x00010000  //DDRSS_PI_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E0 0x00000000  //DDRSS_PI_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E4 0x00000000  //DDRSS_PI_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E8 0x00000000  //DDRSS_PI_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0EC 0x00000000  //DDRSS_PI_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F0 0x00001400  //DDRSS_PI_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F4 0x00000000  //DDRSS_PI_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F8 0x01000000  //DDRSS_PI_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0FC 0x00000404  //DDRSS_PI_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A100 0x00000001  //DDRSS_PI_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A104 0x0001010E  //DDRSS_PI_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A108 0x02040100  //DDRSS_PI_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A10C 0x00010000  //DDRSS_PI_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A110 0x00000034  //DDRSS_PI_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A114 0x00000000  //DDRSS_PI_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A118 0x00000000  //DDRSS_PI_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A11C 0x00000000  //DDRSS_PI_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A120 0x00000000  //DDRSS_PI_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A124 0x00000000  //DDRSS_PI_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A128 0x00000000  //DDRSS_PI_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A12C 0x00000005  //DDRSS_PI_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A130 0x01000000  //DDRSS_PI_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A134 0x04020100  //DDRSS_PI_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A138 0x00020000  //DDRSS_PI_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A13C 0x00010002  //DDRSS_PI_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A140 0x00000001  //DDRSS_PI_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A144 0x00020001  //DDRSS_PI_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A148 0x00020002  //DDRSS_PI_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A14C 0x29C02000  //DDRSS_PI_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A150 0x00000000  //DDRSS_PI_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A154 0x00000000  //DDRSS_PI_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A158 0x00000000  //DDRSS_PI_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A15C 0x00000000  //DDRSS_PI_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A160 0x00000000  //DDRSS_PI_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A164 0x00000000  //DDRSS_PI_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A168 0x00000000  //DDRSS_PI_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A16C 0x00000300  //DDRSS_PI_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A170 0x0A090B0C  //DDRSS_PI_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A174 0x04060708  //DDRSS_PI_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A178 0x01000005  //DDRSS_PI_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A17C 0x00000800  //DDRSS_PI_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A180 0x00000000  //DDRSS_PI_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A184 0x00010008  //DDRSS_PI_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A188 0x00000000  //DDRSS_PI_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A18C 0x0000AA00  //DDRSS_PI_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A190 0x00000000  //DDRSS_PI_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A194 0x00010000  //DDRSS_PI_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A198 0x00000000  //DDRSS_PI_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A19C 0x00000000  //DDRSS_PI_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A0 0x00000000  //DDRSS_PI_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A4 0x00000000  //DDRSS_PI_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A8 0x00000000  //DDRSS_PI_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1AC 0x00000000  //DDRSS_PI_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B0 0x00000000  //DDRSS_PI_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B4 0x00000000  //DDRSS_PI_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B8 0x00000000  //DDRSS_PI_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1BC 0x00000000  //DDRSS_PI_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C0 0x00000000  //DDRSS_PI_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C4 0x00000000  //DDRSS_PI_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C8 0x00000000  //DDRSS_PI_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1CC 0x00000000  //DDRSS_PI_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D0 0x00000000  //DDRSS_PI_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D4 0x00000000  //DDRSS_PI_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D8 0x00000000  //DDRSS_PI_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1DC 0x00000000  //DDRSS_PI_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E0 0x00000000  //DDRSS_PI_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E4 0x00000000  //DDRSS_PI_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E8 0x00000000  //DDRSS_PI_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1EC 0x00000000  //DDRSS_PI_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F0 0x00000008  //DDRSS_PI_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F4 0x00000000  //DDRSS_PI_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F8 0x00000000  //DDRSS_PI_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1FC 0x00000000  //DDRSS_PI_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A200 0x00000000  //DDRSS_PI_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A204 0x00000000  //DDRSS_PI_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A208 0x00000000  //DDRSS_PI_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A20C 0x00000000  //DDRSS_PI_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A210 0x00000000  //DDRSS_PI_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A214 0x00010100  //DDRSS_PI_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A218 0x00000000  //DDRSS_PI_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A21C 0x00000000  //DDRSS_PI_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A220 0x00027100  //DDRSS_PI_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A224 0x00061A80  //DDRSS_PI_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A228 0x00000100  //DDRSS_PI_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A22C 0x00000000  //DDRSS_PI_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A230 0x00000000  //DDRSS_PI_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A234 0x00000000  //DDRSS_PI_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A238 0x00000000  //DDRSS_PI_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A23C 0x00000000  //DDRSS_PI_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A240 0x01000000  //DDRSS_PI_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A244 0xC1010003  //DDRSS_PI_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A248 0x02000101  //DDRSS_PI_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A24C 0x01030101  //DDRSS_PI_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A250 0x00010400  //DDRSS_PI_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A254 0x06000105  //DDRSS_PI_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A258 0x01070001  //DDRSS_PI_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A25C 0x00000000  //DDRSS_PI_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A260 0x00000000  //DDRSS_PI_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A264 0x00000001  //DDRSS_PI_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A268 0x00010000  //DDRSS_PI_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A26C 0x00000000  //DDRSS_PI_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A270 0x00000000  //DDRSS_PI_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A274 0x00000000  //DDRSS_PI_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A278 0x00000000  //DDRSS_PI_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A27C 0x00010000  //DDRSS_PI_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A280 0x00000004  //DDRSS_PI_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A284 0x00000000  //DDRSS_PI_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A288 0x00000000  //DDRSS_PI_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A28C 0x00000000  //DDRSS_PI_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A290 0x00007800  //DDRSS_PI_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A294 0x00780078  //DDRSS_PI_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A298 0x00141414  //DDRSS_PI_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A29C 0x00000037  //DDRSS_PI_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A0 0x00000037  //DDRSS_PI_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A4 0x00040037  //DDRSS_PI_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A8 0x04000400  //DDRSS_PI_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2AC 0x6804000B  //DDRSS_PI_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B0 0x04000B16  //DDRSS_PI_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B4 0x000B1668  //DDRSS_PI_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B8 0x00166804  //DDRSS_PI_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2BC 0x000000D0  //DDRSS_PI_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C0 0x00001860  //DDRSS_PI_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C4 0x000000D0  //DDRSS_PI_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C8 0x00001860  //DDRSS_PI_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2CC 0x000000D0  //DDRSS_PI_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D0 0x04001860  //DDRSS_PI_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D4 0x01010404  //DDRSS_PI_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D8 0x00001901  //DDRSS_PI_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2DC 0x00190019  //DDRSS_PI_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E0 0x010E010E  //DDRSS_PI_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E4 0x0000010E  //DDRSS_PI_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E8 0x00000000  //DDRSS_PI_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2EC 0x00000000  //DDRSS_PI_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F0 0x01010000  //DDRSS_PI_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F4 0x01010101  //DDRSS_PI_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F8 0x00181818  //DDRSS_PI_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2FC 0x00000000  //DDRSS_PI_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A300 0x00000000  //DDRSS_PI_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A304 0x0A000000  //DDRSS_PI_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A308 0x0C0C0A0A  //DDRSS_PI_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A30C 0x0303030C  //DDRSS_PI_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A310 0x00000000  //DDRSS_PI_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A314 0x00000000  //DDRSS_PI_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A318 0x00000000  //DDRSS_PI_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A31C 0x00000000  //DDRSS_PI_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A320 0x00000000  //DDRSS_PI_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A324 0x00000000  //DDRSS_PI_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A328 0x00000000  //DDRSS_PI_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A32C 0x00000000  //DDRSS_PI_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A330 0x00000000  //DDRSS_PI_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A334 0x00000000  //DDRSS_PI_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A338 0x00000000  //DDRSS_PI_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A33C 0x00000000  //DDRSS_PI_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A340 0x00000000  //DDRSS_PI_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A344 0x0D090000  //DDRSS_PI_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A348 0x0D09000D  //DDRSS_PI_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A34C 0x0D09000D  //DDRSS_PI_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A350 0x0000000D  //DDRSS_PI_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A354 0x00000000  //DDRSS_PI_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A358 0x00000000  //DDRSS_PI_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A35C 0x00000000  //DDRSS_PI_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A360 0x00000000  //DDRSS_PI_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A364 0x16000000  //DDRSS_PI_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A368 0x001600C8  //DDRSS_PI_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A36C 0x001600C8  //DDRSS_PI_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A370 0x010100C8  //DDRSS_PI_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A374 0x00001D01  //DDRSS_PI_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A378 0x1F0F004E  //DDRSS_PI_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A37C 0x02000001  //DDRSS_PI_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A380 0x001D0A0A  //DDRSS_PI_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A384 0x1F0F004E  //DDRSS_PI_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A388 0x02000001  //DDRSS_PI_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A38C 0x001D0A0A  //DDRSS_PI_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A390 0x1F0F004E  //DDRSS_PI_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A394 0x02000001  //DDRSS_PI_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A398 0x00010A0A  //DDRSS_PI_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A39C 0x0C0B0700  //DDRSS_PI_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A0 0x000D0605  //DDRSS_PI_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A4 0x0000C570  //DDRSS_PI_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A8 0x0000001D  //DDRSS_PI_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3AC 0x180A0800  //DDRSS_PI_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B0 0x0B071C1C  //DDRSS_PI_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B4 0x0D06050C  //DDRSS_PI_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B8 0x0000C570  //DDRSS_PI_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3BC 0x0000001D  //DDRSS_PI_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C0 0x180A0800  //DDRSS_PI_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C4 0x0B071C1C  //DDRSS_PI_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C8 0x0D06050C  //DDRSS_PI_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3CC 0x0000C570  //DDRSS_PI_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D0 0x0000001D  //DDRSS_PI_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D4 0x180A0800  //DDRSS_PI_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D8 0x00001C1C  //DDRSS_PI_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3DC 0x000030C0  //DDRSS_PI_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E0 0x0001E780  //DDRSS_PI_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E4 0x000030C0  //DDRSS_PI_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E8 0x0001E780  //DDRSS_PI_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3EC 0x000030C0  //DDRSS_PI_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F0 0x0001E780  //DDRSS_PI_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F4 0x02550255  //DDRSS_PI_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F8 0x03030255  //DDRSS_PI_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3FC 0x00025503  //DDRSS_PI_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A400 0x02550255  //DDRSS_PI_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A404 0x0C080C08  //DDRSS_PI_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A408 0x00000C08  //DDRSS_PI_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A40C 0x00089070  //DDRSS_PI_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A410 0x00000000  //DDRSS_PI_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A414 0x00000000  //DDRSS_PI_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A418 0x00000000  //DDRSS_PI_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A41C 0x000000D8  //DDRSS_PI_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A420 0x00089070  //DDRSS_PI_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A424 0x00000000  //DDRSS_PI_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A428 0x00000000  //DDRSS_PI_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A42C 0x00000000  //DDRSS_PI_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A430 0x000000D8  //DDRSS_PI_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A434 0x00089070  //DDRSS_PI_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A438 0x00000000  //DDRSS_PI_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A43C 0x00000000  //DDRSS_PI_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A440 0x00000000  //DDRSS_PI_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A444 0x020000D8  //DDRSS_PI_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A448 0x00000080  //DDRSS_PI_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A44C 0x00020000  //DDRSS_PI_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A450 0x00000080  //DDRSS_PI_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A454 0x00020000  //DDRSS_PI_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A458 0x00000080  //DDRSS_PI_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A45C 0x00000000  //DDRSS_PI_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A460 0x00000000  //DDRSS_PI_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A464 0x00040404  //DDRSS_PI_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A468 0x00000000  //DDRSS_PI_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A46C 0x02010102  //DDRSS_PI_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A470 0x67676767  //DDRSS_PI_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A474 0x00000202  //DDRSS_PI_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A478 0x00000000  //DDRSS_PI_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A47C 0x00000000  //DDRSS_PI_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A480 0x00000000  //DDRSS_PI_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A484 0x00000000  //DDRSS_PI_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A488 0x00000000  //DDRSS_PI_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A48C 0x0D100F00  //DDRSS_PI_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A490 0x0003020E  //DDRSS_PI_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A494 0x00000001  //DDRSS_PI_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A498 0x01000000  //DDRSS_PI_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A49C 0x00020201  //DDRSS_PI_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A0 0x00000000  //DDRSS_PI_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A4 0x00000410  //DDRSS_PI_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A8 0x00000503  //DDRSS_PI_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4AC 0x00000010  //DDRSS_PI_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B0 0x00000000  //DDRSS_PI_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B4 0x00000000  //DDRSS_PI_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B8 0x00001401  //DDRSS_PI_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4BC 0x00000493  //DDRSS_PI_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C0 0x00000000  //DDRSS_PI_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C4 0x00000410  //DDRSS_PI_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C8 0x00000503  //DDRSS_PI_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4CC 0x00000010  //DDRSS_PI_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D0 0x00000000  //DDRSS_PI_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D4 0x00000000  //DDRSS_PI_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D8 0x00001401  //DDRSS_PI_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4DC 0x00000493  //DDRSS_PI_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E0 0x00000000  //DDRSS_PI_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E4 0x00000410  //DDRSS_PI_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E8 0x00000503  //DDRSS_PI_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4EC 0x00000010  //DDRSS_PI_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F0 0x00000000  //DDRSS_PI_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F4 0x00000000  //DDRSS_PI_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F8 0x00001401  //DDRSS_PI_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4FC 0x00000493  //DDRSS_PI_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A500 0x00000000  //DDRSS_PI_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A504 0x00000410  //DDRSS_PI_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A508 0x00000503  //DDRSS_PI_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A50C 0x00000010  //DDRSS_PI_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A510 0x00000000  //DDRSS_PI_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A514 0x00000000  //DDRSS_PI_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A518 0x00001401  //DDRSS_PI_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A51C 0x00000493  //DDRSS_PI_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A520 0x00000000  //DDRSS_PI_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A524 0x00000410  //DDRSS_PI_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A528 0x00000503  //DDRSS_PI_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A52C 0x00000010  //DDRSS_PI_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A530 0x00000000  //DDRSS_PI_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A534 0x00000000  //DDRSS_PI_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A538 0x00001401  //DDRSS_PI_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A53C 0x00000493  //DDRSS_PI_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A540 0x00000000  //DDRSS_PI_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A544 0x00000410  //DDRSS_PI_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A548 0x00000503  //DDRSS_PI_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A54C 0x00000010  //DDRSS_PI_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A550 0x00000000  //DDRSS_PI_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A554 0x00000000  //DDRSS_PI_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A558 0x00001401  //DDRSS_PI_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A55C 0x00000493  //DDRSS_PI_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A560 0x00000000  //DDRSS_PI_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C000 0x04C00000  //DDRSS_PHY_0_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C004 0x00000000  //DDRSS_PHY_1_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C008 0x00000200  //DDRSS_PHY_2_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C00C 0x00000000  //DDRSS_PHY_3_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C010 0x00000000  //DDRSS_PHY_4_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C014 0x00000000  //DDRSS_PHY_5_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C018 0x00000000  //DDRSS_PHY_6_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C01C 0x00000000  //DDRSS_PHY_7_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C020 0x00000001  //DDRSS_PHY_8_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C024 0x00000000  //DDRSS_PHY_9_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C028 0x0A0C0000  //DDRSS_PHY_10_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C02C 0x010101FF  //DDRSS_PHY_11_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C030 0x00010000  //DDRSS_PHY_12_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C034 0x00C04004  //DDRSS_PHY_13_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C038 0x00CC0008  //DDRSS_PHY_14_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C03C 0x00660201  //DDRSS_PHY_15_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C040 0x00000000  //DDRSS_PHY_16_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C044 0x00000000  //DDRSS_PHY_17_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C048 0x00000000  //DDRSS_PHY_18_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C04C 0x0000AAAA  //DDRSS_PHY_19_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C050 0x00005555  //DDRSS_PHY_20_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C054 0x0000B5B5  //DDRSS_PHY_21_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C058 0x00004A4A  //DDRSS_PHY_22_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C05C 0x00005656  //DDRSS_PHY_23_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C060 0x0000A9A9  //DDRSS_PHY_24_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C064 0x0000B7B7  //DDRSS_PHY_25_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C068 0x00004848  //DDRSS_PHY_26_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C06C 0x00000000  //DDRSS_PHY_27_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C070 0x00000000  //DDRSS_PHY_28_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C074 0x08000000  //DDRSS_PHY_29_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C078 0x0F000008  //DDRSS_PHY_30_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C07C 0x00000F0F  //DDRSS_PHY_31_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C080 0x00E4E400  //DDRSS_PHY_32_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C084 0x00070820  //DDRSS_PHY_33_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C088 0x000C0020  //DDRSS_PHY_34_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C08C 0x00062000  //DDRSS_PHY_35_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C090 0x00000000  //DDRSS_PHY_36_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C094 0x55555555  //DDRSS_PHY_37_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C098 0xAAAAAAAA  //DDRSS_PHY_38_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C09C 0x55555555  //DDRSS_PHY_39_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A0 0xAAAAAAAA  //DDRSS_PHY_40_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A4 0x00005555  //DDRSS_PHY_41_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A8 0x01000100  //DDRSS_PHY_42_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0AC 0x00800180  //DDRSS_PHY_43_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B0 0x00000000  //DDRSS_PHY_44_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B4 0x00100000  //DDRSS_PHY_45_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B8 0x00000000  //DDRSS_PHY_46_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0BC 0x05070010  //DDRSS_PHY_47_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C0 0x0000000C  //DDRSS_PHY_48_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C4 0x00000000  //DDRSS_PHY_49_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C8 0x00300024  //DDRSS_PHY_50_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0CC 0x00000FFF  //DDRSS_PHY_51_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D0 0x00000000  //DDRSS_PHY_52_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D4 0x02B802AC  //DDRSS_PHY_53_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D8 0x00000030  //DDRSS_PHY_54_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0DC 0x0114003C  //DDRSS_PHY_55_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E0 0x00000000  //DDRSS_PHY_56_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E4 0x0C000000  //DDRSS_PHY_57_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E8 0x07FF0000  //DDRSS_PHY_58_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0EC 0x00000000  //DDRSS_PHY_59_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F0 0x00000000  //DDRSS_PHY_60_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F4 0x00000000  //DDRSS_PHY_61_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F8 0x00000000  //DDRSS_PHY_62_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0FC 0x00000000  //DDRSS_PHY_63_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C100 0x00000000  //DDRSS_PHY_64_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C104 0x00000004  //DDRSS_PHY_65_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C108 0x00000000  //DDRSS_PHY_66_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C10C 0x00000000  //DDRSS_PHY_67_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C110 0x00000000  //DDRSS_PHY_68_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C114 0x00000000  //DDRSS_PHY_69_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C118 0x00000000  //DDRSS_PHY_70_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C11C 0x00000000  //DDRSS_PHY_71_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C120 0x041F07FF  //DDRSS_PHY_72_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C124 0x00000000  //DDRSS_PHY_73_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C128 0x01CCB001  //DDRSS_PHY_74_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C12C 0x2000CCB0  //DDRSS_PHY_75_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C130 0x20000140  //DDRSS_PHY_76_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C134 0x07FF0200  //DDRSS_PHY_77_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C138 0x0000DD01  //DDRSS_PHY_78_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C13C 0x10100303  //DDRSS_PHY_79_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C140 0x10101010  //DDRSS_PHY_80_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C144 0x10101010  //DDRSS_PHY_81_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C148 0x00021010  //DDRSS_PHY_82_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C14C 0x00100010  //DDRSS_PHY_83_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C150 0x00100010  //DDRSS_PHY_84_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C154 0x00100010  //DDRSS_PHY_85_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C158 0x00100010  //DDRSS_PHY_86_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C15C 0x02020010  //DDRSS_PHY_87_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C160 0x51515041  //DDRSS_PHY_88_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C164 0x31804000  //DDRSS_PHY_89_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C168 0x04C00340  //DDRSS_PHY_90_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C16C 0x01008080  //DDRSS_PHY_91_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C170 0x04050001  //DDRSS_PHY_92_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C174 0x00000504  //DDRSS_PHY_93_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C178 0x42100010  //DDRSS_PHY_94_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C17C 0x010C053E  //DDRSS_PHY_95_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C180 0x000F0C14  //DDRSS_PHY_96_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C184 0x01000140  //DDRSS_PHY_97_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C188 0x007A0120  //DDRSS_PHY_98_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C18C 0x00000C00  //DDRSS_PHY_99_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C190 0x000001CC  //DDRSS_PHY_100_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C194 0x20100200  //DDRSS_PHY_101_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C198 0x00000005  //DDRSS_PHY_102_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C19C 0x76543210  //DDRSS_PHY_103_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A0 0x00000008  //DDRSS_PHY_104_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A4 0x02800280  //DDRSS_PHY_105_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A8 0x02800280  //DDRSS_PHY_106_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1AC 0x02800280  //DDRSS_PHY_107_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B0 0x02800280  //DDRSS_PHY_108_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B4 0x002A0280  //DDRSS_PHY_109_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B8 0x0000A800  //DDRSS_PHY_110_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1BC 0x00A800AE  //DDRSS_PHY_111_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C0 0x00A800AE  //DDRSS_PHY_112_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C4 0x00B400AE  //DDRSS_PHY_113_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C8 0x00B400B4  //DDRSS_PHY_114_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1CC 0x00A800B4  //DDRSS_PHY_115_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D0 0x00A800AE  //DDRSS_PHY_116_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D4 0x00A800AE  //DDRSS_PHY_117_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D8 0x00A800AE  //DDRSS_PHY_118_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1DC 0x01B200AE  //DDRSS_PHY_119_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E0 0x01000000  //DDRSS_PHY_120_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E4 0x00000000  //DDRSS_PHY_121_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E8 0x00000000  //DDRSS_PHY_122_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1EC 0x00080200  //DDRSS_PHY_123_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F0 0x00000000  //DDRSS_PHY_124_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F4 0x00000000  //DDRSS_PHY_125_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C400 0x04C00000  //DDRSS_PHY_256_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C404 0x00000000  //DDRSS_PHY_257_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C408 0x00000200  //DDRSS_PHY_258_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C40C 0x00000000  //DDRSS_PHY_259_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C410 0x00000000  //DDRSS_PHY_260_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C414 0x00000000  //DDRSS_PHY_261_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C418 0x00000000  //DDRSS_PHY_262_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C41C 0x00000000  //DDRSS_PHY_263_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C420 0x00000001  //DDRSS_PHY_264_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C424 0x00000000  //DDRSS_PHY_265_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C428 0x0A0C0000  //DDRSS_PHY_266_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C42C 0x010101FF  //DDRSS_PHY_267_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C430 0x00010000  //DDRSS_PHY_268_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C434 0x00C04004  //DDRSS_PHY_269_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C438 0x00CC0008  //DDRSS_PHY_270_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C43C 0x00660201  //DDRSS_PHY_271_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C440 0x00000000  //DDRSS_PHY_272_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C444 0x00000000  //DDRSS_PHY_273_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C448 0x00000000  //DDRSS_PHY_274_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C44C 0x0000AAAA  //DDRSS_PHY_275_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C450 0x00005555  //DDRSS_PHY_276_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C454 0x0000B5B5  //DDRSS_PHY_277_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C458 0x00004A4A  //DDRSS_PHY_278_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C45C 0x00005656  //DDRSS_PHY_279_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C460 0x0000A9A9  //DDRSS_PHY_280_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C464 0x0000B7B7  //DDRSS_PHY_281_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C468 0x00004848  //DDRSS_PHY_282_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C46C 0x00000000  //DDRSS_PHY_283_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C470 0x00000000  //DDRSS_PHY_284_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C474 0x08000000  //DDRSS_PHY_285_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C478 0x0F000008  //DDRSS_PHY_286_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C47C 0x00000F0F  //DDRSS_PHY_287_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C480 0x00E4E400  //DDRSS_PHY_288_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C484 0x00070820  //DDRSS_PHY_289_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C488 0x000C0020  //DDRSS_PHY_290_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C48C 0x00062000  //DDRSS_PHY_291_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C490 0x00000000  //DDRSS_PHY_292_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C494 0x55555555  //DDRSS_PHY_293_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C498 0xAAAAAAAA  //DDRSS_PHY_294_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C49C 0x55555555  //DDRSS_PHY_295_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A0 0xAAAAAAAA  //DDRSS_PHY_296_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A4 0x00005555  //DDRSS_PHY_297_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A8 0x01000100  //DDRSS_PHY_298_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4AC 0x00800180  //DDRSS_PHY_299_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B0 0x00000000  //DDRSS_PHY_300_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B4 0x00100000  //DDRSS_PHY_301_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B8 0x00000000  //DDRSS_PHY_302_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4BC 0x13070010  //DDRSS_PHY_303_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C0 0x00000013  //DDRSS_PHY_304_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C4 0x00010500  //DDRSS_PHY_305_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C8 0x0048003C  //DDRSS_PHY_306_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4CC 0x00000FFF  //DDRSS_PHY_307_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D0 0x00000000  //DDRSS_PHY_308_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D4 0x02AC02A0  //DDRSS_PHY_309_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D8 0x00000030  //DDRSS_PHY_310_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4DC 0x01200048  //DDRSS_PHY_311_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E0 0x00000000  //DDRSS_PHY_312_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E4 0x0C000000  //DDRSS_PHY_313_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E8 0x07FF0000  //DDRSS_PHY_314_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4EC 0x00000000  //DDRSS_PHY_315_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F0 0x00000000  //DDRSS_PHY_316_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F4 0x00000000  //DDRSS_PHY_317_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F8 0x00000000  //DDRSS_PHY_318_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4FC 0x00000000  //DDRSS_PHY_319_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C500 0x00000000  //DDRSS_PHY_320_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C504 0x00000004  //DDRSS_PHY_321_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C508 0x00000000  //DDRSS_PHY_322_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C50C 0x00000000  //DDRSS_PHY_323_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C510 0x00000000  //DDRSS_PHY_324_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C514 0x00000000  //DDRSS_PHY_325_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C518 0x00000000  //DDRSS_PHY_326_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C51C 0x00000000  //DDRSS_PHY_327_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C520 0x041F07FF  //DDRSS_PHY_328_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C524 0x00000000  //DDRSS_PHY_329_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C528 0x01CCB001  //DDRSS_PHY_330_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C52C 0x2000CCB0  //DDRSS_PHY_331_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C530 0x20000140  //DDRSS_PHY_332_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C534 0x07FF0200  //DDRSS_PHY_333_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C538 0x0000DD01  //DDRSS_PHY_334_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C53C 0x10100303  //DDRSS_PHY_335_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C540 0x10101010  //DDRSS_PHY_336_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C544 0x10101010  //DDRSS_PHY_337_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C548 0x00021010  //DDRSS_PHY_338_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C54C 0x00100010  //DDRSS_PHY_339_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C550 0x00100010  //DDRSS_PHY_340_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C554 0x00100010  //DDRSS_PHY_341_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C558 0x00100010  //DDRSS_PHY_342_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C55C 0x02020010  //DDRSS_PHY_343_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C560 0x51515041  //DDRSS_PHY_344_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C564 0x31804000  //DDRSS_PHY_345_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C568 0x04C00340  //DDRSS_PHY_346_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C56C 0x01008080  //DDRSS_PHY_347_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C570 0x04050001  //DDRSS_PHY_348_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C574 0x00000504  //DDRSS_PHY_349_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C578 0x42100010  //DDRSS_PHY_350_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C57C 0x010C053E  //DDRSS_PHY_351_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C580 0x000F0C14  //DDRSS_PHY_352_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C584 0x01000140  //DDRSS_PHY_353_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C588 0x007A0120  //DDRSS_PHY_354_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C58C 0x00000C00  //DDRSS_PHY_355_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C590 0x000001CC  //DDRSS_PHY_356_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C594 0x20100200  //DDRSS_PHY_357_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C598 0x00000005  //DDRSS_PHY_358_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C59C 0x76543210  //DDRSS_PHY_359_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A0 0x00000008  //DDRSS_PHY_360_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A4 0x02800280  //DDRSS_PHY_361_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A8 0x02800280  //DDRSS_PHY_362_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5AC 0x02800280  //DDRSS_PHY_363_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B0 0x02800280  //DDRSS_PHY_364_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B4 0x00420280  //DDRSS_PHY_365_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B8 0x0000B400  //DDRSS_PHY_366_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5BC 0x00A800B4  //DDRSS_PHY_367_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C0 0x00A800A8  //DDRSS_PHY_368_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C4 0x00B400A8  //DDRSS_PHY_369_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C8 0x00B400B4  //DDRSS_PHY_370_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5CC 0x00B400B4  //DDRSS_PHY_371_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D0 0x00B400B4  //DDRSS_PHY_372_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D4 0x00AE00B4  //DDRSS_PHY_373_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D8 0x00B400AE  //DDRSS_PHY_374_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5DC 0x01A600B4  //DDRSS_PHY_375_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E0 0x01000000  //DDRSS_PHY_376_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E4 0x00000000  //DDRSS_PHY_377_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E8 0x00000000  //DDRSS_PHY_378_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5EC 0x00080200  //DDRSS_PHY_379_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F0 0x00000000  //DDRSS_PHY_380_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F4 0x00000000  //DDRSS_PHY_381_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C800 0x00000100  //DDRSS_PHY_512_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C804 0x00001000  //DDRSS_PHY_513_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C808 0x00070000  //DDRSS_PHY_514_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C80C 0x00000000  //DDRSS_PHY_515_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C810 0x00000000  //DDRSS_PHY_516_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C814 0x00000100  //DDRSS_PHY_517_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C818 0x00000000  //DDRSS_PHY_518_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C81C 0x00000000  //DDRSS_PHY_519_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C820 0x00000000  //DDRSS_PHY_520_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C824 0x00000000  //DDRSS_PHY_521_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C828 0x00000000  //DDRSS_PHY_522_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C82C 0x00000000  //DDRSS_PHY_523_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C830 0x00000000  //DDRSS_PHY_524_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C834 0x00DCBA98  //DDRSS_PHY_525_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C838 0x00000000  //DDRSS_PHY_526_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C83C 0x00000000  //DDRSS_PHY_527_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C840 0x00000000  //DDRSS_PHY_528_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C844 0x00000000  //DDRSS_PHY_529_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C848 0x00000000  //DDRSS_PHY_530_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C84C 0x00000100  //DDRSS_PHY_531_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C850 0x00000000  //DDRSS_PHY_532_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C854 0x00000000  //DDRSS_PHY_533_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C858 0x00000000  //DDRSS_PHY_534_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C85C 0x00000000  //DDRSS_PHY_535_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C860 0x00000000  //DDRSS_PHY_536_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C864 0x00000000  //DDRSS_PHY_537_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C868 0x00000000  //DDRSS_PHY_538_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C86C 0x00000000  //DDRSS_PHY_539_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C870 0x0A418820  //DDRSS_PHY_540_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C874 0x103F0000  //DDRSS_PHY_541_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C878 0x000F0100  //DDRSS_PHY_542_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C87C 0x0000000F  //DDRSS_PHY_543_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C880 0x020002FF  //DDRSS_PHY_544_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C884 0x00030000  //DDRSS_PHY_545_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C888 0x00000300  //DDRSS_PHY_546_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C88C 0x00000300  //DDRSS_PHY_547_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C890 0x00000300  //DDRSS_PHY_548_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C894 0x00000300  //DDRSS_PHY_549_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C898 0x00000300  //DDRSS_PHY_550_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C89C 0x42080010  //DDRSS_PHY_551_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A0 0x0000003E  //DDRSS_PHY_552_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A4 0x00000000  //DDRSS_PHY_553_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A8 0x00000000  //DDRSS_PHY_554_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC00 0x00000100  //DDRSS_PHY_768_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC04 0x00001000  //DDRSS_PHY_769_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC08 0x00070000  //DDRSS_PHY_770_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC0C 0x00000000  //DDRSS_PHY_771_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC10 0x00000000  //DDRSS_PHY_772_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC14 0x00000100  //DDRSS_PHY_773_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC18 0x00000000  //DDRSS_PHY_774_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC1C 0x00000000  //DDRSS_PHY_775_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC20 0x00000000  //DDRSS_PHY_776_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC24 0x00000000  //DDRSS_PHY_777_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC28 0x00000000  //DDRSS_PHY_778_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC2C 0x00000000  //DDRSS_PHY_779_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC30 0x00000000  //DDRSS_PHY_780_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC34 0x00DCBA98  //DDRSS_PHY_781_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC38 0x00000000  //DDRSS_PHY_782_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC3C 0x00000000  //DDRSS_PHY_783_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC40 0x00000000  //DDRSS_PHY_784_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC44 0x00000000  //DDRSS_PHY_785_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC48 0x00000000  //DDRSS_PHY_786_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC4C 0x00000100  //DDRSS_PHY_787_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC50 0x00000000  //DDRSS_PHY_788_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC54 0x00000000  //DDRSS_PHY_789_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC58 0x00000000  //DDRSS_PHY_790_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC5C 0x00000000  //DDRSS_PHY_791_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC60 0x00000000  //DDRSS_PHY_792_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC64 0x00000000  //DDRSS_PHY_793_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC68 0x00000000  //DDRSS_PHY_794_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC6C 0x00000000  //DDRSS_PHY_795_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC70 0x16A4A0E6  //DDRSS_PHY_796_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC74 0x103F0000  //DDRSS_PHY_797_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC78 0x000F0000  //DDRSS_PHY_798_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC7C 0x0000000F  //DDRSS_PHY_799_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC80 0x020002FF  //DDRSS_PHY_800_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC84 0x00030000  //DDRSS_PHY_801_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC88 0x00000300  //DDRSS_PHY_802_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC8C 0x00000300  //DDRSS_PHY_803_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC90 0x00000300  //DDRSS_PHY_804_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC94 0x00000300  //DDRSS_PHY_805_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC98 0x00000300  //DDRSS_PHY_806_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC9C 0x42080010  //DDRSS_PHY_807_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA0 0x0000003E  //DDRSS_PHY_808_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA4 0x00000000  //DDRSS_PHY_809_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA8 0x00000000  //DDRSS_PHY_810_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D000 0x00000100  //DDRSS_PHY_1024_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D004 0x00001000  //DDRSS_PHY_1025_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D008 0x00070000  //DDRSS_PHY_1026_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D00C 0x00000000  //DDRSS_PHY_1027_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D010 0x00000000  //DDRSS_PHY_1028_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D014 0x00000100  //DDRSS_PHY_1029_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D018 0x00000000  //DDRSS_PHY_1030_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D01C 0x00000000  //DDRSS_PHY_1031_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D020 0x00000000  //DDRSS_PHY_1032_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D024 0x00000000  //DDRSS_PHY_1033_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D028 0x00000000  //DDRSS_PHY_1034_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D02C 0x00000000  //DDRSS_PHY_1035_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D030 0x00000000  //DDRSS_PHY_1036_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D034 0x00DCBA98  //DDRSS_PHY_1037_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D038 0x00000000  //DDRSS_PHY_1038_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D03C 0x00000000  //DDRSS_PHY_1039_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D040 0x00000000  //DDRSS_PHY_1040_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D044 0x00000000  //DDRSS_PHY_1041_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D048 0x00000000  //DDRSS_PHY_1042_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D04C 0x00000100  //DDRSS_PHY_1043_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D050 0x00000000  //DDRSS_PHY_1044_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D054 0x00000000  //DDRSS_PHY_1045_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D058 0x00000000  //DDRSS_PHY_1046_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D05C 0x00000000  //DDRSS_PHY_1047_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D060 0x00000000  //DDRSS_PHY_1048_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D064 0x00000000  //DDRSS_PHY_1049_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D068 0x00000000  //DDRSS_PHY_1050_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D06C 0x00000000  //DDRSS_PHY_1051_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D070 0x2307B9AC  //DDRSS_PHY_1052_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D074 0x10030000  //DDRSS_PHY_1053_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D078 0x000F0000  //DDRSS_PHY_1054_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D07C 0x0000000F  //DDRSS_PHY_1055_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D080 0x020002FF  //DDRSS_PHY_1056_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D084 0x00030000  //DDRSS_PHY_1057_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D088 0x00000300  //DDRSS_PHY_1058_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D08C 0x00000300  //DDRSS_PHY_1059_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D090 0x00000300  //DDRSS_PHY_1060_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D094 0x00000300  //DDRSS_PHY_1061_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D098 0x00000300  //DDRSS_PHY_1062_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D09C 0x42080010  //DDRSS_PHY_1063_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A0 0x0000003E  //DDRSS_PHY_1064_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A4 0x00000000  //DDRSS_PHY_1065_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A8 0x00000000  //DDRSS_PHY_1066_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D400 0x00000000  //DDRSS_PHY_1280_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D404 0x00000000  //DDRSS_PHY_1281_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D408 0x00000000  //DDRSS_PHY_1282_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D40C 0x00000000  //DDRSS_PHY_1283_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D410 0x00000000  //DDRSS_PHY_1284_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D414 0x00000000  //DDRSS_PHY_1285_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D418 0x00050000  //DDRSS_PHY_1286_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D41C 0x04000100  //DDRSS_PHY_1287_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D420 0x00000055  //DDRSS_PHY_1288_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D424 0x00000000  //DDRSS_PHY_1289_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D428 0x06800000  //DDRSS_PHY_1290_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D42C 0x00000000  //DDRSS_PHY_1291_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D430 0x00000000  //DDRSS_PHY_1292_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D434 0x01002000  //DDRSS_PHY_1293_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D438 0x00004001  //DDRSS_PHY_1294_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D43C 0x00020028  //DDRSS_PHY_1295_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D440 0x00010100  //DDRSS_PHY_1296_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D444 0x00000001  //DDRSS_PHY_1297_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D448 0x00000000  //DDRSS_PHY_1298_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D44C 0x0F0F0E06  //DDRSS_PHY_1299_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D450 0x00010101  //DDRSS_PHY_1300_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D454 0x010F0004  //DDRSS_PHY_1301_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D458 0x00000000  //DDRSS_PHY_1302_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D45C 0x20125770  //DDRSS_PHY_1303_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D460 0x00000064  //DDRSS_PHY_1304_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D464 0x00000000  //DDRSS_PHY_1305_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D468 0x00000000  //DDRSS_PHY_1306_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D46C 0x01020103  //DDRSS_PHY_1307_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D470 0x03020102  //DDRSS_PHY_1308_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D474 0x03030303  //DDRSS_PHY_1309_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D478 0x03030303  //DDRSS_PHY_1310_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D47C 0x00040000  //DDRSS_PHY_1311_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D480 0x00005201  //DDRSS_PHY_1312_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D484 0x00000003  //DDRSS_PHY_1313_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D488 0x00010000  //DDRSS_PHY_1314_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D48C 0x00000000  //DDRSS_PHY_1315_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D490 0x00000003  //DDRSS_PHY_1316_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D494 0x00010000  //DDRSS_PHY_1317_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D498 0x00000000  //DDRSS_PHY_1318_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D49C 0x07070001  //DDRSS_PHY_1319_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A0 0x00005400  //DDRSS_PHY_1320_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A4 0x000040A2  //DDRSS_PHY_1321_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A8 0x0003488F  //DDRSS_PHY_1322_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4AC 0x0001488F  //DDRSS_PHY_1323_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B0 0x0001488F  //DDRSS_PHY_1324_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B4 0x0001488F  //DDRSS_PHY_1325_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B8 0x0001488F  //DDRSS_PHY_1326_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4BC 0x0001488F  //DDRSS_PHY_1327_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C0 0x0001491E  //DDRSS_PHY_1328_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C4 0x0001491E  //DDRSS_PHY_1329_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C8 0x0001488F  //DDRSS_PHY_1330_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4CC 0x0001488F  //DDRSS_PHY_1331_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D0 0x00000000  //DDRSS_PHY_1332_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D4 0x00000046  //DDRSS_PHY_1333_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D8 0x00000400  //DDRSS_PHY_1334_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4DC 0x00000008  //DDRSS_PHY_1335_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E0 0x0081488F  //DDRSS_PHY_1336_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E4 0x0081491E  //DDRSS_PHY_1337_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E8 0x001488F0  //DDRSS_PHY_1338_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4EC 0x001491E8  //DDRSS_PHY_1339_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F0 0x00F488FF  //DDRSS_PHY_1340_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F4 0x03F491EF  //DDRSS_PHY_1341_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F8 0x00000000  //DDRSS_PHY_1342_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4FC 0x00000000  //DDRSS_PHY_1343_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D500 0xB3000000  //DDRSS_PHY_1344_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D504 0x04102006  //DDRSS_PHY_1345_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D508 0x00041020  //DDRSS_PHY_1346_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D50C 0x01C98C98  //DDRSS_PHY_1347_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D510 0x3F400000  //DDRSS_PHY_1348_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D514 0x3F3F1F3F  //DDRSS_PHY_1349_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D518 0x0000001F  //DDRSS_PHY_1350_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D51C 0x00000000  //DDRSS_PHY_1351_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D520 0x00000000  //DDRSS_PHY_1352_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D524 0x00000000  //DDRSS_PHY_1353_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D528 0x00000001  //DDRSS_PHY_1354_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D52C 0x00000000  //DDRSS_PHY_1355_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D530 0x00000000  //DDRSS_PHY_1356_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D534 0x00000000  //DDRSS_PHY_1357_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D538 0x00000000  //DDRSS_PHY_1358_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D53C 0x76543210  //DDRSS_PHY_1359_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D540 0x00000098  //DDRSS_PHY_1360_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D544 0x00000000  //DDRSS_PHY_1361_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D548 0x00000000  //DDRSS_PHY_1362_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D54C 0x00000000  //DDRSS_PHY_1363_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D550 0x00040700  //DDRSS_PHY_1364_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D554 0x00000000  //DDRSS_PHY_1365_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D558 0x00000000  //DDRSS_PHY_1366_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D55C 0x00000000  //DDRSS_PHY_1367_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D560 0x030F7102  //DDRSS_PHY_1368_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D564 0x00000100  //DDRSS_PHY_1369_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D568 0x00000000  //DDRSS_PHY_1370_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D56C 0x0001F7C2  //DDRSS_PHY_1371_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D570 0x00020002  //DDRSS_PHY_1372_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D574 0x00000000  //DDRSS_PHY_1373_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D578 0x00001142  //DDRSS_PHY_1374_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D57C 0x03020400  //DDRSS_PHY_1375_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D580 0x00000080  //DDRSS_PHY_1376_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D584 0x03900390  //DDRSS_PHY_1377_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D588 0x03900390  //DDRSS_PHY_1378_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D58C 0x03900390  //DDRSS_PHY_1379_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D590 0x03900390  //DDRSS_PHY_1380_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D594 0x03900390  //DDRSS_PHY_1381_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D598 0x03900390  //DDRSS_PHY_1382_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D59C 0x00000300  //DDRSS_PHY_1383_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A0 0x00000300  //DDRSS_PHY_1384_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A4 0x00000300  //DDRSS_PHY_1385_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A8 0x00000300  //DDRSS_PHY_1386_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5AC 0x31823FF7  //DDRSS_PHY_1387_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B0 0x00000000  //DDRSS_PHY_1388_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B4 0x0C000D3F  //DDRSS_PHY_1389_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B8 0x30000D3F  //DDRSS_PHY_1390_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5BC 0x300D3F11  //DDRSS_PHY_1391_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C0 0x01FF0000  //DDRSS_PHY_1392_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C4 0x000D3FFF  //DDRSS_PHY_1393_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C8 0x00000C11  //DDRSS_PHY_1394_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5CC 0x300D3F11  //DDRSS_PHY_1395_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D0 0x01FF0000  //DDRSS_PHY_1396_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D4 0x300C3F11  //DDRSS_PHY_1397_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D8 0x01FF0000  //DDRSS_PHY_1398_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5DC 0x300C3F11  //DDRSS_PHY_1399_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E0 0x01FF0000  //DDRSS_PHY_1400_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E4 0x300D3F11  //DDRSS_PHY_1401_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E8 0x01FF0000  //DDRSS_PHY_1402_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5EC 0x300D3F11  //DDRSS_PHY_1403_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F0 0x01FF0000  //DDRSS_PHY_1404_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F4 0x20040004  //DDRSS_PHY_1405_DATA_F0

We also tried with Read Preamble set to 2T (other configuration same as the previous case).

Here is the register dump when the program runs to just before DDR write&read start:

MAIN_Cortex_R5_0_0: GEL Output: 0x0F308000 0x10460A01  //DDRSS_CTL_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308004 0x5D1AF3C3  //DDRSS_CTL_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308008 0x0171A610  //DDRSS_CTL_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30800C 0x40020A11  //DDRSS_CTL_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308010 0x00052006  //DDRSS_CTL_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308014 0x02050020  //DDRSS_CTL_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308018 0x03070101  //DDRSS_CTL_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30801C 0x00089070  //DDRSS_CTL_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308020 0x00000000  //DDRSS_CTL_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308024 0x00000000  //DDRSS_CTL_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308028 0x00000000  //DDRSS_CTL_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30802C 0x00089070  //DDRSS_CTL_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308030 0x00000000  //DDRSS_CTL_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308034 0x00000000  //DDRSS_CTL_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308038 0x00000000  //DDRSS_CTL_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30803C 0x00089070  //DDRSS_CTL_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308040 0x00000000  //DDRSS_CTL_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308044 0x00000000  //DDRSS_CTL_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308048 0x00000000  //DDRSS_CTL_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30804C 0x01010100  //DDRSS_CTL_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308050 0x01000101  //DDRSS_CTL_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308054 0x01000110  //DDRSS_CTL_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308058 0x02010002  //DDRSS_CTL_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30805C 0x00027100  //DDRSS_CTL_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308060 0x00061A80  //DDRSS_CTL_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308064 0x02550255  //DDRSS_CTL_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308068 0x00000255  //DDRSS_CTL_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30806C 0x00000000  //DDRSS_CTL_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308070 0x00000000  //DDRSS_CTL_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308074 0x00000000  //DDRSS_CTL_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308078 0x00000000  //DDRSS_CTL_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30807C 0x00000000  //DDRSS_CTL_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308080 0x00000000  //DDRSS_CTL_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308084 0x00000000  //DDRSS_CTL_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308088 0x00000000  //DDRSS_CTL_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30808C 0x00000000  //DDRSS_CTL_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308090 0x00000000  //DDRSS_CTL_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308094 0x00000000  //DDRSS_CTL_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308098 0x04000B16  //DDRSS_CTL_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30809C 0x1C1C1C1C  //DDRSS_CTL_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A0 0x04000B16  //DDRSS_CTL_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A4 0x1C1C1C1C  //DDRSS_CTL_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A8 0x04000B16  //DDRSS_CTL_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080AC 0x1C1C1C1C  //DDRSS_CTL_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B0 0x05050404  //DDRSS_CTL_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B4 0x00002706  //DDRSS_CTL_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B8 0x0602001D  //DDRSS_CTL_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080BC 0x05001D0B  //DDRSS_CTL_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C0 0x00270605  //DDRSS_CTL_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C4 0x0602001D  //DDRSS_CTL_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C8 0x05001D0B  //DDRSS_CTL_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080CC 0x00270605  //DDRSS_CTL_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D0 0x0602001D  //DDRSS_CTL_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D4 0x07001D0B  //DDRSS_CTL_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D8 0x00180807  //DDRSS_CTL_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080DC 0x0400DB60  //DDRSS_CTL_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E0 0x07070009  //DDRSS_CTL_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E4 0x00001808  //DDRSS_CTL_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E8 0x0400DB60  //DDRSS_CTL_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080EC 0x07070009  //DDRSS_CTL_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F0 0x00001808  //DDRSS_CTL_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F4 0x0400DB60  //DDRSS_CTL_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F8 0x03000009  //DDRSS_CTL_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080FC 0x0D0C0002  //DDRSS_CTL_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308100 0x0D0C0D0C  //DDRSS_CTL_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308104 0x01010000  //DDRSS_CTL_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308108 0x03191919  //DDRSS_CTL_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30810C 0x0B0B0B0B  //DDRSS_CTL_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308110 0x00000B0B  //DDRSS_CTL_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308114 0x00000101  //DDRSS_CTL_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308118 0x00000000  //DDRSS_CTL_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30811C 0x01000000  //DDRSS_CTL_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308120 0x00D00803  //DDRSS_CTL_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308124 0x00001860  //DDRSS_CTL_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308128 0x000000D0  //DDRSS_CTL_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30812C 0x00001860  //DDRSS_CTL_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308130 0x000000D0  //DDRSS_CTL_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308134 0x00001860  //DDRSS_CTL_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308138 0x00000005  //DDRSS_CTL_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30813C 0x00000000  //DDRSS_CTL_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308140 0x00000000  //DDRSS_CTL_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308144 0x00000000  //DDRSS_CTL_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308148 0x00000000  //DDRSS_CTL_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30814C 0x00000000  //DDRSS_CTL_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308150 0x00000000  //DDRSS_CTL_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308154 0x00000000  //DDRSS_CTL_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308158 0x00000000  //DDRSS_CTL_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30815C 0x00090009  //DDRSS_CTL_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308160 0x00000009  //DDRSS_CTL_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308164 0x00000000  //DDRSS_CTL_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308168 0x00000000  //DDRSS_CTL_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30816C 0x00000000  //DDRSS_CTL_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308170 0x00000000  //DDRSS_CTL_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308174 0x00000000  //DDRSS_CTL_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308178 0x00010001  //DDRSS_CTL_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30817C 0x00025501  //DDRSS_CTL_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308180 0x025500D8  //DDRSS_CTL_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308184 0x025500D8  //DDRSS_CTL_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308188 0x00D800D8  //DDRSS_CTL_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30818C 0x00D800D8  //DDRSS_CTL_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308190 0x00000000  //DDRSS_CTL_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308194 0x00000000  //DDRSS_CTL_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308198 0x00000000  //DDRSS_CTL_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30819C 0x00000000  //DDRSS_CTL_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A0 0x00000000  //DDRSS_CTL_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A4 0x00000000  //DDRSS_CTL_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A8 0x03010000  //DDRSS_CTL_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081AC 0x00010000  //DDRSS_CTL_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B0 0x00000000  //DDRSS_CTL_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B4 0x01000000  //DDRSS_CTL_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B8 0x80104002  //DDRSS_CTL_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081BC 0x00040003  //DDRSS_CTL_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C0 0x00040005  //DDRSS_CTL_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C4 0x00030000  //DDRSS_CTL_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C8 0x00050004  //DDRSS_CTL_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081CC 0x00000004  //DDRSS_CTL_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D0 0x00040003  //DDRSS_CTL_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D4 0x00040005  //DDRSS_CTL_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D8 0x00000000  //DDRSS_CTL_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081DC 0x00061800  //DDRSS_CTL_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E0 0x00061800  //DDRSS_CTL_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E4 0x00061800  //DDRSS_CTL_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E8 0x00061800  //DDRSS_CTL_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081EC 0x00061800  //DDRSS_CTL_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F0 0x00000000  //DDRSS_CTL_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F4 0x0000AAA0  //DDRSS_CTL_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F8 0x00061800  //DDRSS_CTL_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081FC 0x00061800  //DDRSS_CTL_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308200 0x00061800  //DDRSS_CTL_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308204 0x00061800  //DDRSS_CTL_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308208 0x00061800  //DDRSS_CTL_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30820C 0x00000000  //DDRSS_CTL_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308210 0x0000AAA0  //DDRSS_CTL_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308214 0x00061800  //DDRSS_CTL_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308218 0x00061800  //DDRSS_CTL_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30821C 0x00061800  //DDRSS_CTL_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308220 0x00061800  //DDRSS_CTL_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308224 0x00061800  //DDRSS_CTL_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308228 0x00000000  //DDRSS_CTL_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30822C 0x0000AAA0  //DDRSS_CTL_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308230 0x00000000  //DDRSS_CTL_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308234 0x00000000  //DDRSS_CTL_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308238 0x00000000  //DDRSS_CTL_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30823C 0x00000000  //DDRSS_CTL_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308240 0x00000000  //DDRSS_CTL_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308244 0x00000000  //DDRSS_CTL_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308248 0x00000000  //DDRSS_CTL_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30824C 0x00000000  //DDRSS_CTL_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308250 0x00000000  //DDRSS_CTL_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308254 0x00000000  //DDRSS_CTL_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308258 0x00000000  //DDRSS_CTL_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30825C 0x00000000  //DDRSS_CTL_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308260 0x00000000  //DDRSS_CTL_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308264 0x00000000  //DDRSS_CTL_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308268 0x00000000  //DDRSS_CTL_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30826C 0x00000000  //DDRSS_CTL_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308270 0x080C0000  //DDRSS_CTL_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308274 0x080C080C  //DDRSS_CTL_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308278 0x00000000  //DDRSS_CTL_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30827C 0x07010A09  //DDRSS_CTL_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308280 0x000E0A09  //DDRSS_CTL_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308284 0x010A0900  //DDRSS_CTL_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308288 0x0E0A0907  //DDRSS_CTL_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30828C 0x0A090000  //DDRSS_CTL_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308290 0x0A090701  //DDRSS_CTL_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308294 0x0000080E  //DDRSS_CTL_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308298 0x00040003  //DDRSS_CTL_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30829C 0x00004007  //DDRSS_CTL_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A0 0x00000000  //DDRSS_CTL_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A4 0x00000000  //DDRSS_CTL_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A8 0x00000000  //DDRSS_CTL_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082AC 0x00000000  //DDRSS_CTL_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B0 0x00000000  //DDRSS_CTL_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B4 0x00000000  //DDRSS_CTL_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B8 0x01000000  //DDRSS_CTL_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082BC 0x00000000  //DDRSS_CTL_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C0 0x00001500  //DDRSS_CTL_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C4 0x0000100E  //DDRSS_CTL_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C8 0x00000000  //DDRSS_CTL_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082CC 0x00000000  //DDRSS_CTL_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D0 0x00000001  //DDRSS_CTL_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D4 0x00000002  //DDRSS_CTL_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D8 0x00000C00  //DDRSS_CTL_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082DC 0x00001000  //DDRSS_CTL_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E0 0x00000C00  //DDRSS_CTL_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E4 0x00001000  //DDRSS_CTL_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E8 0x00000C00  //DDRSS_CTL_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082EC 0x00001000  //DDRSS_CTL_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F0 0x00000000  //DDRSS_CTL_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F4 0x00000000  //DDRSS_CTL_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F8 0x00000000  //DDRSS_CTL_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082FC 0x00000000  //DDRSS_CTL_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308300 0x00000000  //DDRSS_CTL_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308304 0x00000000  //DDRSS_CTL_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308308 0x00000000  //DDRSS_CTL_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30830C 0x00000000  //DDRSS_CTL_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308310 0x00000000  //DDRSS_CTL_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308314 0x00000000  //DDRSS_CTL_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308318 0x00000000  //DDRSS_CTL_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30831C 0x00000000  //DDRSS_CTL_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308320 0x00000000  //DDRSS_CTL_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308324 0x00000000  //DDRSS_CTL_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308328 0x00000000  //DDRSS_CTL_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30832C 0x00000000  //DDRSS_CTL_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308330 0x00041000  //DDRSS_CTL_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308334 0x00000503  //DDRSS_CTL_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308338 0x00000010  //DDRSS_CTL_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30833C 0x00000410  //DDRSS_CTL_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308340 0x00000503  //DDRSS_CTL_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308344 0x00000010  //DDRSS_CTL_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308348 0x00000410  //DDRSS_CTL_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30834C 0x00000503  //DDRSS_CTL_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308350 0x00000010  //DDRSS_CTL_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308354 0x00000410  //DDRSS_CTL_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308358 0x00000503  //DDRSS_CTL_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30835C 0x00000010  //DDRSS_CTL_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308360 0x00000410  //DDRSS_CTL_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308364 0x00000503  //DDRSS_CTL_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308368 0x00000010  //DDRSS_CTL_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30836C 0x00000410  //DDRSS_CTL_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308370 0x00000503  //DDRSS_CTL_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308374 0x00000010  //DDRSS_CTL_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308378 0x00000000  //DDRSS_CTL_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30837C 0x00000000  //DDRSS_CTL_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308380 0x00000000  //DDRSS_CTL_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308384 0x00000000  //DDRSS_CTL_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308388 0x00000000  //DDRSS_CTL_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30838C 0x00000000  //DDRSS_CTL_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308390 0x00000000  //DDRSS_CTL_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308394 0x00000000  //DDRSS_CTL_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308398 0x00000000  //DDRSS_CTL_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30839C 0x00000000  //DDRSS_CTL_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A0 0x00000000  //DDRSS_CTL_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A4 0x00000000  //DDRSS_CTL_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A8 0x00000000  //DDRSS_CTL_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083AC 0x00000000  //DDRSS_CTL_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B0 0x00001401  //DDRSS_CTL_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B4 0x00001401  //DDRSS_CTL_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B8 0x00001401  //DDRSS_CTL_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083BC 0x00001401  //DDRSS_CTL_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C0 0x00001401  //DDRSS_CTL_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C4 0x00001401  //DDRSS_CTL_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C8 0x00000493  //DDRSS_CTL_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083CC 0x00000493  //DDRSS_CTL_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D0 0x00000493  //DDRSS_CTL_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D4 0x00000493  //DDRSS_CTL_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D8 0x00000493  //DDRSS_CTL_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083DC 0x00000493  //DDRSS_CTL_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E0 0x00000000  //DDRSS_CTL_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E4 0x00000000  //DDRSS_CTL_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E8 0x00000000  //DDRSS_CTL_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083EC 0x00000000  //DDRSS_CTL_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F0 0x00000000  //DDRSS_CTL_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F4 0x00000000  //DDRSS_CTL_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F8 0x00000000  //DDRSS_CTL_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083FC 0x00000000  //DDRSS_CTL_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308400 0x00000000  //DDRSS_CTL_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308404 0x00000000  //DDRSS_CTL_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308408 0x00000000  //DDRSS_CTL_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30840C 0x00000000  //DDRSS_CTL_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308410 0x00000000  //DDRSS_CTL_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308414 0x00000000  //DDRSS_CTL_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308418 0x00000000  //DDRSS_CTL_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30841C 0x00000000  //DDRSS_CTL_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308420 0x00000000  //DDRSS_CTL_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308424 0x00000000  //DDRSS_CTL_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308428 0x00000000  //DDRSS_CTL_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30842C 0x00000000  //DDRSS_CTL_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308430 0x00000000  //DDRSS_CTL_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308434 0x00000000  //DDRSS_CTL_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308438 0x00000000  //DDRSS_CTL_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30843C 0x00000000  //DDRSS_CTL_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308440 0x00000000  //DDRSS_CTL_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308444 0x00000000  //DDRSS_CTL_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308448 0x00000000  //DDRSS_CTL_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30844C 0x00000000  //DDRSS_CTL_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308450 0x00000000  //DDRSS_CTL_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308454 0x00010000  //DDRSS_CTL_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308458 0x00000000  //DDRSS_CTL_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30845C 0x00000100  //DDRSS_CTL_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308460 0x00000000  //DDRSS_CTL_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308464 0x00000101  //DDRSS_CTL_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308468 0x00000000  //DDRSS_CTL_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30846C 0x00000000  //DDRSS_CTL_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308470 0x00000000  //DDRSS_CTL_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308474 0x00000000  //DDRSS_CTL_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308478 0x00000000  //DDRSS_CTL_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30847C 0x00000000  //DDRSS_CTL_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308480 0x00000000  //DDRSS_CTL_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308484 0x00000FFF  //DDRSS_CTL_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308488 0x0C181511  //DDRSS_CTL_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30848C 0x00000304  //DDRSS_CTL_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308490 0x00000000  //DDRSS_CTL_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308494 0x00000000  //DDRSS_CTL_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308498 0x00000000  //DDRSS_CTL_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30849C 0x00000000  //DDRSS_CTL_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A0 0x00000000  //DDRSS_CTL_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A4 0x00000000  //DDRSS_CTL_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A8 0x00000000  //DDRSS_CTL_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084AC 0x00000000  //DDRSS_CTL_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B0 0x00000000  //DDRSS_CTL_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B4 0x00000000  //DDRSS_CTL_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B8 0x00000000  //DDRSS_CTL_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084BC 0x00000000  //DDRSS_CTL_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C0 0x00000000  //DDRSS_CTL_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C4 0x00040000  //DDRSS_CTL_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C8 0x00800200  //DDRSS_CTL_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084CC 0x00000000  //DDRSS_CTL_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D0 0x02000400  //DDRSS_CTL_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D4 0x00000080  //DDRSS_CTL_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D8 0x00040000  //DDRSS_CTL_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084DC 0x00800200  //DDRSS_CTL_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E0 0x00000000  //DDRSS_CTL_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E4 0x00000000  //DDRSS_CTL_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E8 0x00000000  //DDRSS_CTL_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084EC 0x00000100  //DDRSS_CTL_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F0 0x01010000  //DDRSS_CTL_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F4 0x00000202  //DDRSS_CTL_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F8 0x0FFF0000  //DDRSS_CTL_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084FC 0x000FFF00  //DDRSS_CTL_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308500 0xFFFFFFFF  //DDRSS_CTL_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308504 0x00FFFF00  //DDRSS_CTL_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308508 0x0A000000  //DDRSS_CTL_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30850C 0x0001FFFF  //DDRSS_CTL_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308510 0x01010101  //DDRSS_CTL_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308514 0x01010101  //DDRSS_CTL_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308518 0x00000118  //DDRSS_CTL_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30851C 0x00000C01  //DDRSS_CTL_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308520 0x00000000  //DDRSS_CTL_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308524 0x00000000  //DDRSS_CTL_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308528 0x00000000  //DDRSS_CTL_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30852C 0x01000000  //DDRSS_CTL_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308530 0x00000100  //DDRSS_CTL_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308534 0x00010000  //DDRSS_CTL_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308538 0x00000000  //DDRSS_CTL_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30853C 0x00000000  //DDRSS_CTL_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308540 0x00000000  //DDRSS_CTL_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308544 0x00000000  //DDRSS_CTL_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308548 0x00000000  //DDRSS_CTL_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30854C 0x00000000  //DDRSS_CTL_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308550 0x00000000  //DDRSS_CTL_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308554 0x00000000  //DDRSS_CTL_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308558 0x00000000  //DDRSS_CTL_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30855C 0x00000000  //DDRSS_CTL_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308560 0x00000000  //DDRSS_CTL_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308564 0x00000000  //DDRSS_CTL_345_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308568 0x00000000  //DDRSS_CTL_346_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30856C 0x00000000  //DDRSS_CTL_347_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308570 0x00000000  //DDRSS_CTL_348_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308574 0x00000000  //DDRSS_CTL_349_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308578 0x00000000  //DDRSS_CTL_350_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30857C 0x00000000  //DDRSS_CTL_351_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308580 0x00000000  //DDRSS_CTL_352_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308584 0x00000000  //DDRSS_CTL_353_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308588 0x00000000  //DDRSS_CTL_354_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30858C 0x00000000  //DDRSS_CTL_355_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308590 0x00000000  //DDRSS_CTL_356_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308594 0x00000000  //DDRSS_CTL_357_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308598 0x00000000  //DDRSS_CTL_358_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30859C 0x00000000  //DDRSS_CTL_359_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A0 0x00000000  //DDRSS_CTL_360_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A4 0x00000000  //DDRSS_CTL_361_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A8 0x00000000  //DDRSS_CTL_362_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085AC 0x00000000  //DDRSS_CTL_363_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B0 0x00000000  //DDRSS_CTL_364_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B4 0x0000FFFF  //DDRSS_CTL_365_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B8 0x0000FFFF  //DDRSS_CTL_366_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085BC 0x0196EFF0  //DDRSS_CTL_367_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C0 0x00000000  //DDRSS_CTL_368_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C4 0x00000000  //DDRSS_CTL_369_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C8 0x0E000000  //DDRSS_CTL_370_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085CC 0x060E0606  //DDRSS_CTL_371_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D0 0x06060E06  //DDRSS_CTL_372_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D4 0x00010101  //DDRSS_CTL_373_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D8 0x02000000  //DDRSS_CTL_374_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085DC 0x00020101  //DDRSS_CTL_375_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E0 0x00000000  //DDRSS_CTL_376_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E4 0x02020200  //DDRSS_CTL_377_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E8 0x02020202  //DDRSS_CTL_378_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085EC 0x02020202  //DDRSS_CTL_379_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F0 0x02020202  //DDRSS_CTL_380_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F4 0x00000000  //DDRSS_CTL_381_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F8 0x00000000  //DDRSS_CTL_382_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085FC 0x04000100  //DDRSS_CTL_383_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308600 0x1E000304  //DDRSS_CTL_384_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308604 0x000030C0  //DDRSS_CTL_385_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308608 0x00000200  //DDRSS_CTL_386_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30860C 0x00000200  //DDRSS_CTL_387_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308610 0x00000200  //DDRSS_CTL_388_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308614 0x00000200  //DDRSS_CTL_389_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308618 0x0000DB60  //DDRSS_CTL_390_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30861C 0x0001E780  //DDRSS_CTL_391_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308620 0x090A0302  //DDRSS_CTL_392_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308624 0x001E0B0C  //DDRSS_CTL_393_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308628 0x000030C0  //DDRSS_CTL_394_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30862C 0x00000200  //DDRSS_CTL_395_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308630 0x00000200  //DDRSS_CTL_396_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308634 0x00000200  //DDRSS_CTL_397_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308638 0x00000200  //DDRSS_CTL_398_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30863C 0x0000DB60  //DDRSS_CTL_399_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308640 0x0001E780  //DDRSS_CTL_400_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308644 0x090A0302  //DDRSS_CTL_401_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308648 0x001E0B0C  //DDRSS_CTL_402_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30864C 0x000030C0  //DDRSS_CTL_403_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308650 0x00000200  //DDRSS_CTL_404_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308654 0x00000200  //DDRSS_CTL_405_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308658 0x00000200  //DDRSS_CTL_406_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30865C 0x00000200  //DDRSS_CTL_407_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308660 0x0000DB60  //DDRSS_CTL_408_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308664 0x0001E780  //DDRSS_CTL_409_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308668 0x090A0302  //DDRSS_CTL_410_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30866C 0x00000B0C  //DDRSS_CTL_411_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308670 0x00000000  //DDRSS_CTL_412_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308674 0x0302000A  //DDRSS_CTL_413_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308678 0x01000500  //DDRSS_CTL_414_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30867C 0x01010001  //DDRSS_CTL_415_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308680 0x00010001  //DDRSS_CTL_416_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308684 0x01010001  //DDRSS_CTL_417_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308688 0x02010000  //DDRSS_CTL_418_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30868C 0x00000200  //DDRSS_CTL_419_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308690 0x02000201  //DDRSS_CTL_420_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308694 0x00000000  //DDRSS_CTL_421_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308698 0x00202020  //DDRSS_CTL_422_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A000 0x00000A01  //DDRSS_PI_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A004 0xAE8D79E2  //DDRSS_PI_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A008 0x0714B570  //DDRSS_PI_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A00C 0x01011387  //DDRSS_PI_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A010 0x00000001  //DDRSS_PI_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A014 0x00010064  //DDRSS_PI_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A018 0x00000000  //DDRSS_PI_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A01C 0x00000000  //DDRSS_PI_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A020 0x00000000  //DDRSS_PI_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A024 0x00000003  //DDRSS_PI_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A028 0x0000000F  //DDRSS_PI_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A02C 0x00000000  //DDRSS_PI_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A030 0x00000000  //DDRSS_PI_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A034 0x00010001  //DDRSS_PI_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A038 0x00000000  //DDRSS_PI_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A03C 0x00010001  //DDRSS_PI_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A040 0x00000005  //DDRSS_PI_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A044 0x00010000  //DDRSS_PI_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A048 0x00000000  //DDRSS_PI_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A04C 0x00000000  //DDRSS_PI_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A050 0x00000000  //DDRSS_PI_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A054 0x00000000  //DDRSS_PI_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A058 0x00000000  //DDRSS_PI_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A05C 0x00000000  //DDRSS_PI_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A060 0x280D0001  //DDRSS_PI_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A064 0x00000000  //DDRSS_PI_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A068 0x00010000  //DDRSS_PI_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A06C 0x00003200  //DDRSS_PI_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A070 0x00000000  //DDRSS_PI_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A074 0x00000000  //DDRSS_PI_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A078 0x00060602  //DDRSS_PI_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A07C 0x00000000  //DDRSS_PI_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A080 0x00000000  //DDRSS_PI_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A084 0x00000000  //DDRSS_PI_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A088 0x00000001  //DDRSS_PI_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A08C 0x00000055  //DDRSS_PI_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A090 0x000000AA  //DDRSS_PI_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A094 0x000000AD  //DDRSS_PI_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A098 0x00000052  //DDRSS_PI_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A09C 0x0000006A  //DDRSS_PI_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A0 0x00000095  //DDRSS_PI_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A4 0x00000095  //DDRSS_PI_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A8 0x000000AD  //DDRSS_PI_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0AC 0x00000000  //DDRSS_PI_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B0 0x00000000  //DDRSS_PI_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B4 0x00010100  //DDRSS_PI_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B8 0x00000014  //DDRSS_PI_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0BC 0x000007D0  //DDRSS_PI_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C0 0x00000300  //DDRSS_PI_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C4 0x00000000  //DDRSS_PI_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C8 0x00000000  //DDRSS_PI_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0CC 0x01000000  //DDRSS_PI_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D0 0x00010101  //DDRSS_PI_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D4 0x01000B09  //DDRSS_PI_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D8 0x00000000  //DDRSS_PI_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0DC 0x00010000  //DDRSS_PI_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E0 0x00000000  //DDRSS_PI_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E4 0x00000000  //DDRSS_PI_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E8 0x00000000  //DDRSS_PI_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0EC 0x00000000  //DDRSS_PI_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F0 0x00001400  //DDRSS_PI_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F4 0x00000000  //DDRSS_PI_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F8 0x01000000  //DDRSS_PI_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0FC 0x00000404  //DDRSS_PI_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A100 0x00000001  //DDRSS_PI_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A104 0x0001010E  //DDRSS_PI_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A108 0x02040100  //DDRSS_PI_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A10C 0x00010000  //DDRSS_PI_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A110 0x00000034  //DDRSS_PI_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A114 0x00000000  //DDRSS_PI_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A118 0x00000000  //DDRSS_PI_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A11C 0x00000000  //DDRSS_PI_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A120 0x00000000  //DDRSS_PI_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A124 0x00000000  //DDRSS_PI_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A128 0x00000000  //DDRSS_PI_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A12C 0x00000005  //DDRSS_PI_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A130 0x01000000  //DDRSS_PI_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A134 0x04020100  //DDRSS_PI_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A138 0x00020000  //DDRSS_PI_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A13C 0x00010002  //DDRSS_PI_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A140 0x00000001  //DDRSS_PI_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A144 0x00020001  //DDRSS_PI_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A148 0x00020002  //DDRSS_PI_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A14C 0x29C02000  //DDRSS_PI_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A150 0x00000000  //DDRSS_PI_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A154 0x00000000  //DDRSS_PI_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A158 0x00000000  //DDRSS_PI_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A15C 0x00000000  //DDRSS_PI_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A160 0x00000000  //DDRSS_PI_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A164 0x00000000  //DDRSS_PI_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A168 0x00000000  //DDRSS_PI_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A16C 0x00000300  //DDRSS_PI_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A170 0x0A090B0C  //DDRSS_PI_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A174 0x04060708  //DDRSS_PI_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A178 0x01000005  //DDRSS_PI_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A17C 0x00000800  //DDRSS_PI_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A180 0x00000000  //DDRSS_PI_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A184 0x00010008  //DDRSS_PI_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A188 0x00000000  //DDRSS_PI_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A18C 0x0000AA00  //DDRSS_PI_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A190 0x00000000  //DDRSS_PI_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A194 0x00010000  //DDRSS_PI_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A198 0x00000000  //DDRSS_PI_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A19C 0x00000000  //DDRSS_PI_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A0 0x00000000  //DDRSS_PI_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A4 0x00000000  //DDRSS_PI_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A8 0x00000000  //DDRSS_PI_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1AC 0x00000000  //DDRSS_PI_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B0 0x00000000  //DDRSS_PI_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B4 0x00000000  //DDRSS_PI_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B8 0x00000000  //DDRSS_PI_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1BC 0x00000000  //DDRSS_PI_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C0 0x00000000  //DDRSS_PI_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C4 0x00000000  //DDRSS_PI_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C8 0x00000000  //DDRSS_PI_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1CC 0x00000000  //DDRSS_PI_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D0 0x00000000  //DDRSS_PI_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D4 0x00000000  //DDRSS_PI_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D8 0x00000000  //DDRSS_PI_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1DC 0x00000000  //DDRSS_PI_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E0 0x00000000  //DDRSS_PI_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E4 0x00000000  //DDRSS_PI_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E8 0x00000000  //DDRSS_PI_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1EC 0x00000000  //DDRSS_PI_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F0 0x00000008  //DDRSS_PI_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F4 0x00000000  //DDRSS_PI_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F8 0x00000000  //DDRSS_PI_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1FC 0x00000000  //DDRSS_PI_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A200 0x00000000  //DDRSS_PI_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A204 0x00000000  //DDRSS_PI_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A208 0x00000000  //DDRSS_PI_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A20C 0x00000000  //DDRSS_PI_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A210 0x00000000  //DDRSS_PI_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A214 0x00010100  //DDRSS_PI_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A218 0x00000000  //DDRSS_PI_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A21C 0x00000000  //DDRSS_PI_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A220 0x00027100  //DDRSS_PI_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A224 0x00061A80  //DDRSS_PI_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A228 0x00000100  //DDRSS_PI_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A22C 0x00000000  //DDRSS_PI_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A230 0x00000000  //DDRSS_PI_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A234 0x00000000  //DDRSS_PI_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A238 0x00000000  //DDRSS_PI_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A23C 0x00000000  //DDRSS_PI_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A240 0x01000000  //DDRSS_PI_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A244 0xC1010003  //DDRSS_PI_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A248 0x02000101  //DDRSS_PI_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A24C 0x01030101  //DDRSS_PI_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A250 0x00010400  //DDRSS_PI_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A254 0x06000105  //DDRSS_PI_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A258 0x01070001  //DDRSS_PI_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A25C 0x00000000  //DDRSS_PI_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A260 0x00000000  //DDRSS_PI_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A264 0x00000001  //DDRSS_PI_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A268 0x00010000  //DDRSS_PI_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A26C 0x00000000  //DDRSS_PI_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A270 0x00000000  //DDRSS_PI_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A274 0x00000000  //DDRSS_PI_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A278 0x00000000  //DDRSS_PI_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A27C 0x00010000  //DDRSS_PI_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A280 0x00000004  //DDRSS_PI_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A284 0x00000000  //DDRSS_PI_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A288 0x00000000  //DDRSS_PI_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A28C 0x00000000  //DDRSS_PI_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A290 0x00007800  //DDRSS_PI_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A294 0x00780078  //DDRSS_PI_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A298 0x00141414  //DDRSS_PI_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A29C 0x00000037  //DDRSS_PI_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A0 0x00000037  //DDRSS_PI_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A4 0x00040037  //DDRSS_PI_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A8 0x04000400  //DDRSS_PI_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2AC 0x6804000B  //DDRSS_PI_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B0 0x04000B16  //DDRSS_PI_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B4 0x000B1668  //DDRSS_PI_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B8 0x00166804  //DDRSS_PI_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2BC 0x000000D0  //DDRSS_PI_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C0 0x00001860  //DDRSS_PI_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C4 0x000000D0  //DDRSS_PI_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C8 0x00001860  //DDRSS_PI_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2CC 0x000000D0  //DDRSS_PI_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D0 0x04001860  //DDRSS_PI_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D4 0x01010404  //DDRSS_PI_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D8 0x00001901  //DDRSS_PI_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2DC 0x00190019  //DDRSS_PI_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E0 0x010E010E  //DDRSS_PI_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E4 0x0000010E  //DDRSS_PI_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E8 0x00000000  //DDRSS_PI_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2EC 0x00000000  //DDRSS_PI_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F0 0x01010000  //DDRSS_PI_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F4 0x01010101  //DDRSS_PI_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F8 0x00181818  //DDRSS_PI_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2FC 0x00000000  //DDRSS_PI_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A300 0x00000000  //DDRSS_PI_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A304 0x0A000000  //DDRSS_PI_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A308 0x0C0C0A0A  //DDRSS_PI_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A30C 0x0303030C  //DDRSS_PI_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A310 0x00000000  //DDRSS_PI_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A314 0x00000000  //DDRSS_PI_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A318 0x00000000  //DDRSS_PI_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A31C 0x00000000  //DDRSS_PI_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A320 0x00000000  //DDRSS_PI_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A324 0x00000000  //DDRSS_PI_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A328 0x00000000  //DDRSS_PI_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A32C 0x00000000  //DDRSS_PI_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A330 0x00000000  //DDRSS_PI_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A334 0x00000000  //DDRSS_PI_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A338 0x00000000  //DDRSS_PI_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A33C 0x00000000  //DDRSS_PI_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A340 0x00000000  //DDRSS_PI_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A344 0x0D090000  //DDRSS_PI_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A348 0x0D09000D  //DDRSS_PI_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A34C 0x0D09000D  //DDRSS_PI_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A350 0x0000000D  //DDRSS_PI_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A354 0x00000000  //DDRSS_PI_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A358 0x00000000  //DDRSS_PI_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A35C 0x00000000  //DDRSS_PI_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A360 0x00000000  //DDRSS_PI_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A364 0x16000000  //DDRSS_PI_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A368 0x001600C8  //DDRSS_PI_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A36C 0x001600C8  //DDRSS_PI_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A370 0x010100C8  //DDRSS_PI_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A374 0x00001D01  //DDRSS_PI_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A378 0x1F0F004E  //DDRSS_PI_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A37C 0x02000001  //DDRSS_PI_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A380 0x001D0A0A  //DDRSS_PI_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A384 0x1F0F004E  //DDRSS_PI_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A388 0x02000001  //DDRSS_PI_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A38C 0x001D0A0A  //DDRSS_PI_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A390 0x1F0F004E  //DDRSS_PI_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A394 0x02000001  //DDRSS_PI_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A398 0x00010A0A  //DDRSS_PI_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A39C 0x0C0B0700  //DDRSS_PI_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A0 0x000D0605  //DDRSS_PI_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A4 0x0000C570  //DDRSS_PI_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A8 0x0000001D  //DDRSS_PI_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3AC 0x180A0800  //DDRSS_PI_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B0 0x0B071C1C  //DDRSS_PI_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B4 0x0D06050C  //DDRSS_PI_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B8 0x0000C570  //DDRSS_PI_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3BC 0x0000001D  //DDRSS_PI_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C0 0x180A0800  //DDRSS_PI_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C4 0x0B071C1C  //DDRSS_PI_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C8 0x0D06050C  //DDRSS_PI_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3CC 0x0000C570  //DDRSS_PI_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D0 0x0000001D  //DDRSS_PI_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D4 0x180A0800  //DDRSS_PI_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D8 0x00001C1C  //DDRSS_PI_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3DC 0x000030C0  //DDRSS_PI_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E0 0x0001E780  //DDRSS_PI_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E4 0x000030C0  //DDRSS_PI_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E8 0x0001E780  //DDRSS_PI_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3EC 0x000030C0  //DDRSS_PI_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F0 0x0001E780  //DDRSS_PI_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F4 0x02550255  //DDRSS_PI_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F8 0x03030255  //DDRSS_PI_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3FC 0x00025503  //DDRSS_PI_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A400 0x02550255  //DDRSS_PI_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A404 0x0C080C08  //DDRSS_PI_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A408 0x00000C08  //DDRSS_PI_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A40C 0x00089070  //DDRSS_PI_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A410 0x00000000  //DDRSS_PI_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A414 0x00000000  //DDRSS_PI_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A418 0x00000000  //DDRSS_PI_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A41C 0x000000D8  //DDRSS_PI_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A420 0x00089070  //DDRSS_PI_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A424 0x00000000  //DDRSS_PI_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A428 0x00000000  //DDRSS_PI_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A42C 0x00000000  //DDRSS_PI_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A430 0x000000D8  //DDRSS_PI_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A434 0x00089070  //DDRSS_PI_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A438 0x00000000  //DDRSS_PI_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A43C 0x00000000  //DDRSS_PI_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A440 0x00000000  //DDRSS_PI_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A444 0x020000D8  //DDRSS_PI_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A448 0x00000080  //DDRSS_PI_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A44C 0x00020000  //DDRSS_PI_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A450 0x00000080  //DDRSS_PI_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A454 0x00020000  //DDRSS_PI_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A458 0x00000080  //DDRSS_PI_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A45C 0x00000000  //DDRSS_PI_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A460 0x00000000  //DDRSS_PI_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A464 0x00040404  //DDRSS_PI_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A468 0x00000000  //DDRSS_PI_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A46C 0x02010102  //DDRSS_PI_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A470 0x67676767  //DDRSS_PI_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A474 0x00000202  //DDRSS_PI_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A478 0x00000000  //DDRSS_PI_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A47C 0x00000000  //DDRSS_PI_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A480 0x00000000  //DDRSS_PI_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A484 0x00000000  //DDRSS_PI_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A488 0x00000000  //DDRSS_PI_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A48C 0x0D100F00  //DDRSS_PI_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A490 0x0003020E  //DDRSS_PI_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A494 0x00000001  //DDRSS_PI_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A498 0x01000000  //DDRSS_PI_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A49C 0x00020201  //DDRSS_PI_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A0 0x00000000  //DDRSS_PI_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A4 0x00000410  //DDRSS_PI_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A8 0x00000503  //DDRSS_PI_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4AC 0x00000010  //DDRSS_PI_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B0 0x00000000  //DDRSS_PI_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B4 0x00000000  //DDRSS_PI_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B8 0x00001401  //DDRSS_PI_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4BC 0x00000493  //DDRSS_PI_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C0 0x00000000  //DDRSS_PI_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C4 0x00000410  //DDRSS_PI_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C8 0x00000503  //DDRSS_PI_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4CC 0x00000010  //DDRSS_PI_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D0 0x00000000  //DDRSS_PI_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D4 0x00000000  //DDRSS_PI_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D8 0x00001401  //DDRSS_PI_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4DC 0x00000493  //DDRSS_PI_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E0 0x00000000  //DDRSS_PI_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E4 0x00000410  //DDRSS_PI_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E8 0x00000503  //DDRSS_PI_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4EC 0x00000010  //DDRSS_PI_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F0 0x00000000  //DDRSS_PI_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F4 0x00000000  //DDRSS_PI_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F8 0x00001401  //DDRSS_PI_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4FC 0x00000493  //DDRSS_PI_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A500 0x00000000  //DDRSS_PI_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A504 0x00000410  //DDRSS_PI_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A508 0x00000503  //DDRSS_PI_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A50C 0x00000010  //DDRSS_PI_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A510 0x00000000  //DDRSS_PI_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A514 0x00000000  //DDRSS_PI_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A518 0x00001401  //DDRSS_PI_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A51C 0x00000493  //DDRSS_PI_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A520 0x00000000  //DDRSS_PI_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A524 0x00000410  //DDRSS_PI_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A528 0x00000503  //DDRSS_PI_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A52C 0x00000010  //DDRSS_PI_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A530 0x00000000  //DDRSS_PI_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A534 0x00000000  //DDRSS_PI_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A538 0x00001401  //DDRSS_PI_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A53C 0x00000493  //DDRSS_PI_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A540 0x00000000  //DDRSS_PI_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A544 0x00000410  //DDRSS_PI_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A548 0x00000503  //DDRSS_PI_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A54C 0x00000010  //DDRSS_PI_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A550 0x00000000  //DDRSS_PI_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A554 0x00000000  //DDRSS_PI_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A558 0x00001401  //DDRSS_PI_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A55C 0x00000493  //DDRSS_PI_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A560 0x00000000  //DDRSS_PI_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C000 0x04C00000  //DDRSS_PHY_0_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C004 0x00000000  //DDRSS_PHY_1_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C008 0x00000200  //DDRSS_PHY_2_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C00C 0x00000000  //DDRSS_PHY_3_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C010 0x00000000  //DDRSS_PHY_4_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C014 0x00000000  //DDRSS_PHY_5_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C018 0x00000000  //DDRSS_PHY_6_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C01C 0x00000000  //DDRSS_PHY_7_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C020 0x00000001  //DDRSS_PHY_8_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C024 0x00000000  //DDRSS_PHY_9_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C028 0x0A0C0000  //DDRSS_PHY_10_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C02C 0x010101FF  //DDRSS_PHY_11_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C030 0x00010000  //DDRSS_PHY_12_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C034 0x00C04004  //DDRSS_PHY_13_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C038 0x00CC0008  //DDRSS_PHY_14_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C03C 0x00660201  //DDRSS_PHY_15_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C040 0x00000000  //DDRSS_PHY_16_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C044 0x00000000  //DDRSS_PHY_17_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C048 0x00000000  //DDRSS_PHY_18_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C04C 0x0000AAAA  //DDRSS_PHY_19_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C050 0x00005555  //DDRSS_PHY_20_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C054 0x0000B5B5  //DDRSS_PHY_21_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C058 0x00004A4A  //DDRSS_PHY_22_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C05C 0x00005656  //DDRSS_PHY_23_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C060 0x0000A9A9  //DDRSS_PHY_24_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C064 0x0000B7B7  //DDRSS_PHY_25_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C068 0x00004848  //DDRSS_PHY_26_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C06C 0x00000000  //DDRSS_PHY_27_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C070 0x00000000  //DDRSS_PHY_28_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C074 0x08000000  //DDRSS_PHY_29_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C078 0x0F000008  //DDRSS_PHY_30_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C07C 0x00000F0F  //DDRSS_PHY_31_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C080 0x00E4E400  //DDRSS_PHY_32_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C084 0x00070820  //DDRSS_PHY_33_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C088 0x000C0020  //DDRSS_PHY_34_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C08C 0x00062000  //DDRSS_PHY_35_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C090 0x00000000  //DDRSS_PHY_36_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C094 0x55555555  //DDRSS_PHY_37_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C098 0xAAAAAAAA  //DDRSS_PHY_38_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C09C 0x55555555  //DDRSS_PHY_39_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A0 0xAAAAAAAA  //DDRSS_PHY_40_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A4 0x00005555  //DDRSS_PHY_41_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A8 0x01000100  //DDRSS_PHY_42_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0AC 0x00800180  //DDRSS_PHY_43_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B0 0x00000000  //DDRSS_PHY_44_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B4 0x00100000  //DDRSS_PHY_45_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B8 0x00000000  //DDRSS_PHY_46_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0BC 0x06070010  //DDRSS_PHY_47_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C0 0x0000000C  //DDRSS_PHY_48_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C4 0x00000100  //DDRSS_PHY_49_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C8 0x00300024  //DDRSS_PHY_50_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0CC 0x00000FFF  //DDRSS_PHY_51_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D0 0x00000000  //DDRSS_PHY_52_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D4 0x02B802AC  //DDRSS_PHY_53_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D8 0x00000030  //DDRSS_PHY_54_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0DC 0x0114003C  //DDRSS_PHY_55_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E0 0x00000000  //DDRSS_PHY_56_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E4 0x0C000000  //DDRSS_PHY_57_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E8 0x07FF0000  //DDRSS_PHY_58_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0EC 0x00000000  //DDRSS_PHY_59_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F0 0x00000000  //DDRSS_PHY_60_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F4 0x00000000  //DDRSS_PHY_61_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F8 0x00000000  //DDRSS_PHY_62_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0FC 0x00000000  //DDRSS_PHY_63_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C100 0x00000000  //DDRSS_PHY_64_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C104 0x00000004  //DDRSS_PHY_65_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C108 0x00000000  //DDRSS_PHY_66_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C10C 0x00000000  //DDRSS_PHY_67_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C110 0x00000000  //DDRSS_PHY_68_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C114 0x00000000  //DDRSS_PHY_69_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C118 0x00000000  //DDRSS_PHY_70_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C11C 0x00000000  //DDRSS_PHY_71_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C120 0x041F07FF  //DDRSS_PHY_72_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C124 0x00000000  //DDRSS_PHY_73_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C128 0x01CCB001  //DDRSS_PHY_74_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C12C 0x2000CCB0  //DDRSS_PHY_75_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C130 0x20000140  //DDRSS_PHY_76_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C134 0x07FF0200  //DDRSS_PHY_77_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C138 0x0000DD01  //DDRSS_PHY_78_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C13C 0x10100303  //DDRSS_PHY_79_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C140 0x10101010  //DDRSS_PHY_80_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C144 0x10101010  //DDRSS_PHY_81_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C148 0x00021010  //DDRSS_PHY_82_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C14C 0x00100010  //DDRSS_PHY_83_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C150 0x00100010  //DDRSS_PHY_84_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C154 0x00100010  //DDRSS_PHY_85_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C158 0x00100010  //DDRSS_PHY_86_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C15C 0x02020010  //DDRSS_PHY_87_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C160 0x51515041  //DDRSS_PHY_88_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C164 0x31804000  //DDRSS_PHY_89_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C168 0x04C00340  //DDRSS_PHY_90_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C16C 0x01008080  //DDRSS_PHY_91_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C170 0x04050001  //DDRSS_PHY_92_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C174 0x00000504  //DDRSS_PHY_93_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C178 0x42100010  //DDRSS_PHY_94_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C17C 0x010C053E  //DDRSS_PHY_95_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C180 0x000F0C14  //DDRSS_PHY_96_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C184 0x01000140  //DDRSS_PHY_97_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C188 0x007A0120  //DDRSS_PHY_98_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C18C 0x00000C00  //DDRSS_PHY_99_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C190 0x000001CC  //DDRSS_PHY_100_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C194 0x20100200  //DDRSS_PHY_101_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C198 0x00000005  //DDRSS_PHY_102_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C19C 0x76543210  //DDRSS_PHY_103_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A0 0x00000008  //DDRSS_PHY_104_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A4 0x02800280  //DDRSS_PHY_105_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A8 0x02800280  //DDRSS_PHY_106_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1AC 0x02800280  //DDRSS_PHY_107_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B0 0x02800280  //DDRSS_PHY_108_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B4 0x002A0280  //DDRSS_PHY_109_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B8 0x0000A800  //DDRSS_PHY_110_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1BC 0x00A800AE  //DDRSS_PHY_111_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C0 0x00A800B4  //DDRSS_PHY_112_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C4 0x00B400AE  //DDRSS_PHY_113_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C8 0x00B400BA  //DDRSS_PHY_114_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1CC 0x00A800B4  //DDRSS_PHY_115_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D0 0x00A800AE  //DDRSS_PHY_116_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D4 0x00A800AE  //DDRSS_PHY_117_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D8 0x00A800AE  //DDRSS_PHY_118_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1DC 0x01B200AE  //DDRSS_PHY_119_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E0 0x01000000  //DDRSS_PHY_120_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E4 0x00000000  //DDRSS_PHY_121_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E8 0x00000000  //DDRSS_PHY_122_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1EC 0x00080200  //DDRSS_PHY_123_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F0 0x00000000  //DDRSS_PHY_124_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F4 0x00000000  //DDRSS_PHY_125_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C400 0x04C00000  //DDRSS_PHY_256_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C404 0x00000000  //DDRSS_PHY_257_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C408 0x00000200  //DDRSS_PHY_258_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C40C 0x00000000  //DDRSS_PHY_259_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C410 0x00000000  //DDRSS_PHY_260_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C414 0x00000000  //DDRSS_PHY_261_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C418 0x00000000  //DDRSS_PHY_262_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C41C 0x00000000  //DDRSS_PHY_263_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C420 0x00000001  //DDRSS_PHY_264_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C424 0x00000000  //DDRSS_PHY_265_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C428 0x0A0C0000  //DDRSS_PHY_266_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C42C 0x010101FF  //DDRSS_PHY_267_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C430 0x00010000  //DDRSS_PHY_268_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C434 0x00C03C04  //DDRSS_PHY_269_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C438 0x00CC0008  //DDRSS_PHY_270_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C43C 0x00660201  //DDRSS_PHY_271_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C440 0x00000000  //DDRSS_PHY_272_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C444 0x00000000  //DDRSS_PHY_273_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C448 0x00000000  //DDRSS_PHY_274_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C44C 0x0000AAAA  //DDRSS_PHY_275_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C450 0x00005555  //DDRSS_PHY_276_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C454 0x0000B5B5  //DDRSS_PHY_277_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C458 0x00004A4A  //DDRSS_PHY_278_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C45C 0x00005656  //DDRSS_PHY_279_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C460 0x0000A9A9  //DDRSS_PHY_280_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C464 0x0000B7B7  //DDRSS_PHY_281_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C468 0x00004848  //DDRSS_PHY_282_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C46C 0x00000000  //DDRSS_PHY_283_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C470 0x00000000  //DDRSS_PHY_284_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C474 0x08000000  //DDRSS_PHY_285_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C478 0x0F000008  //DDRSS_PHY_286_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C47C 0x00000F0F  //DDRSS_PHY_287_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C480 0x00E4E400  //DDRSS_PHY_288_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C484 0x00070820  //DDRSS_PHY_289_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C488 0x000C0020  //DDRSS_PHY_290_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C48C 0x00062000  //DDRSS_PHY_291_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C490 0x00000000  //DDRSS_PHY_292_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C494 0x55555555  //DDRSS_PHY_293_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C498 0xAAAAAAAA  //DDRSS_PHY_294_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C49C 0x55555555  //DDRSS_PHY_295_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A0 0xAAAAAAAA  //DDRSS_PHY_296_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A4 0x00005555  //DDRSS_PHY_297_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A8 0x01000100  //DDRSS_PHY_298_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4AC 0x00800180  //DDRSS_PHY_299_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B0 0x00000000  //DDRSS_PHY_300_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B4 0x00100000  //DDRSS_PHY_301_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B8 0x00000000  //DDRSS_PHY_302_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4BC 0x14070010  //DDRSS_PHY_303_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C0 0x00000014  //DDRSS_PHY_304_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C4 0x00010600  //DDRSS_PHY_305_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C8 0x0048003C  //DDRSS_PHY_306_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4CC 0x00000FFF  //DDRSS_PHY_307_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D0 0x00000000  //DDRSS_PHY_308_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D4 0x02A00294  //DDRSS_PHY_309_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D8 0x00000030  //DDRSS_PHY_310_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4DC 0x01200048  //DDRSS_PHY_311_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E0 0x00000000  //DDRSS_PHY_312_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E4 0x0C000000  //DDRSS_PHY_313_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E8 0x07FF0000  //DDRSS_PHY_314_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4EC 0x00000000  //DDRSS_PHY_315_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F0 0x00000000  //DDRSS_PHY_316_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F4 0x00000000  //DDRSS_PHY_317_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F8 0x00000000  //DDRSS_PHY_318_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4FC 0x00000000  //DDRSS_PHY_319_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C500 0x00000000  //DDRSS_PHY_320_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C504 0x00000004  //DDRSS_PHY_321_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C508 0x00000000  //DDRSS_PHY_322_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C50C 0x00000000  //DDRSS_PHY_323_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C510 0x00000000  //DDRSS_PHY_324_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C514 0x00000000  //DDRSS_PHY_325_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C518 0x00000000  //DDRSS_PHY_326_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C51C 0x00000000  //DDRSS_PHY_327_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C520 0x041F07FF  //DDRSS_PHY_328_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C524 0x00000000  //DDRSS_PHY_329_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C528 0x01CCB001  //DDRSS_PHY_330_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C52C 0x2000CCB0  //DDRSS_PHY_331_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C530 0x20000140  //DDRSS_PHY_332_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C534 0x07FF0200  //DDRSS_PHY_333_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C538 0x0000DD01  //DDRSS_PHY_334_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C53C 0x10100303  //DDRSS_PHY_335_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C540 0x10101010  //DDRSS_PHY_336_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C544 0x10101010  //DDRSS_PHY_337_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C548 0x00021010  //DDRSS_PHY_338_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C54C 0x00100010  //DDRSS_PHY_339_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C550 0x00100010  //DDRSS_PHY_340_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C554 0x00100010  //DDRSS_PHY_341_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C558 0x00100010  //DDRSS_PHY_342_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C55C 0x02020010  //DDRSS_PHY_343_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C560 0x51515041  //DDRSS_PHY_344_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C564 0x31804000  //DDRSS_PHY_345_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C568 0x04BC0340  //DDRSS_PHY_346_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C56C 0x01008080  //DDRSS_PHY_347_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C570 0x04050001  //DDRSS_PHY_348_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C574 0x00000504  //DDRSS_PHY_349_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C578 0x42100010  //DDRSS_PHY_350_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C57C 0x010C053E  //DDRSS_PHY_351_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C580 0x000F0C14  //DDRSS_PHY_352_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C584 0x01000140  //DDRSS_PHY_353_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C588 0x007A0120  //DDRSS_PHY_354_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C58C 0x00000C00  //DDRSS_PHY_355_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C590 0x000001CC  //DDRSS_PHY_356_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C594 0x20100200  //DDRSS_PHY_357_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C598 0x00000005  //DDRSS_PHY_358_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C59C 0x76543210  //DDRSS_PHY_359_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A0 0x00000008  //DDRSS_PHY_360_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A4 0x02800280  //DDRSS_PHY_361_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A8 0x02800280  //DDRSS_PHY_362_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5AC 0x02800280  //DDRSS_PHY_363_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B0 0x02800280  //DDRSS_PHY_364_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B4 0x00420280  //DDRSS_PHY_365_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B8 0x0000B400  //DDRSS_PHY_366_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5BC 0x00A800B4  //DDRSS_PHY_367_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C0 0x00A800AE  //DDRSS_PHY_368_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C4 0x00B400AE  //DDRSS_PHY_369_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C8 0x00B400B4  //DDRSS_PHY_370_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5CC 0x00B400B4  //DDRSS_PHY_371_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D0 0x00B400AE  //DDRSS_PHY_372_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D4 0x00AE00B4  //DDRSS_PHY_373_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D8 0x00B400AE  //DDRSS_PHY_374_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5DC 0x019A00B4  //DDRSS_PHY_375_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E0 0x01000000  //DDRSS_PHY_376_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E4 0x00000000  //DDRSS_PHY_377_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E8 0x00000000  //DDRSS_PHY_378_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5EC 0x00080200  //DDRSS_PHY_379_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F0 0x00000000  //DDRSS_PHY_380_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F4 0x00000000  //DDRSS_PHY_381_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C800 0x00000100  //DDRSS_PHY_512_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C804 0x00001000  //DDRSS_PHY_513_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C808 0x00070000  //DDRSS_PHY_514_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C80C 0x00000000  //DDRSS_PHY_515_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C810 0x00000000  //DDRSS_PHY_516_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C814 0x00000100  //DDRSS_PHY_517_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C818 0x00000000  //DDRSS_PHY_518_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C81C 0x00000000  //DDRSS_PHY_519_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C820 0x00000000  //DDRSS_PHY_520_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C824 0x00000000  //DDRSS_PHY_521_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C828 0x00000000  //DDRSS_PHY_522_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C82C 0x00000000  //DDRSS_PHY_523_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C830 0x00000000  //DDRSS_PHY_524_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C834 0x00DCBA98  //DDRSS_PHY_525_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C838 0x00000000  //DDRSS_PHY_526_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C83C 0x00000000  //DDRSS_PHY_527_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C840 0x00000000  //DDRSS_PHY_528_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C844 0x00000000  //DDRSS_PHY_529_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C848 0x00000000  //DDRSS_PHY_530_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C84C 0x00000100  //DDRSS_PHY_531_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C850 0x00000000  //DDRSS_PHY_532_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C854 0x00000000  //DDRSS_PHY_533_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C858 0x00000000  //DDRSS_PHY_534_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C85C 0x00000000  //DDRSS_PHY_535_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C860 0x00000000  //DDRSS_PHY_536_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C864 0x00000000  //DDRSS_PHY_537_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C868 0x00000000  //DDRSS_PHY_538_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C86C 0x00000000  //DDRSS_PHY_539_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C870 0x0A418820  //DDRSS_PHY_540_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C874 0x103F0000  //DDRSS_PHY_541_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C878 0x000F0100  //DDRSS_PHY_542_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C87C 0x0000000F  //DDRSS_PHY_543_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C880 0x020002FF  //DDRSS_PHY_544_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C884 0x00030000  //DDRSS_PHY_545_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C888 0x00000300  //DDRSS_PHY_546_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C88C 0x00000300  //DDRSS_PHY_547_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C890 0x00000300  //DDRSS_PHY_548_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C894 0x00000300  //DDRSS_PHY_549_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C898 0x00000300  //DDRSS_PHY_550_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C89C 0x42080010  //DDRSS_PHY_551_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A0 0x0000003E  //DDRSS_PHY_552_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A4 0x00000000  //DDRSS_PHY_553_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A8 0x00000000  //DDRSS_PHY_554_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC00 0x00000100  //DDRSS_PHY_768_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC04 0x00001000  //DDRSS_PHY_769_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC08 0x00070000  //DDRSS_PHY_770_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC0C 0x00000000  //DDRSS_PHY_771_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC10 0x00000000  //DDRSS_PHY_772_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC14 0x00000100  //DDRSS_PHY_773_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC18 0x00000000  //DDRSS_PHY_774_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC1C 0x00000000  //DDRSS_PHY_775_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC20 0x00000000  //DDRSS_PHY_776_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC24 0x00000000  //DDRSS_PHY_777_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC28 0x00000000  //DDRSS_PHY_778_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC2C 0x00000000  //DDRSS_PHY_779_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC30 0x00000000  //DDRSS_PHY_780_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC34 0x00DCBA98  //DDRSS_PHY_781_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC38 0x00000000  //DDRSS_PHY_782_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC3C 0x00000000  //DDRSS_PHY_783_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC40 0x00000000  //DDRSS_PHY_784_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC44 0x00000000  //DDRSS_PHY_785_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC48 0x00000000  //DDRSS_PHY_786_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC4C 0x00000100  //DDRSS_PHY_787_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC50 0x00000000  //DDRSS_PHY_788_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC54 0x00000000  //DDRSS_PHY_789_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC58 0x00000000  //DDRSS_PHY_790_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC5C 0x00000000  //DDRSS_PHY_791_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC60 0x00000000  //DDRSS_PHY_792_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC64 0x00000000  //DDRSS_PHY_793_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC68 0x00000000  //DDRSS_PHY_794_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC6C 0x00000000  //DDRSS_PHY_795_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC70 0x16A4A0E6  //DDRSS_PHY_796_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC74 0x103F0000  //DDRSS_PHY_797_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC78 0x000F0000  //DDRSS_PHY_798_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC7C 0x0000000F  //DDRSS_PHY_799_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC80 0x020002FF  //DDRSS_PHY_800_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC84 0x00030000  //DDRSS_PHY_801_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC88 0x00000300  //DDRSS_PHY_802_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC8C 0x00000300  //DDRSS_PHY_803_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC90 0x00000300  //DDRSS_PHY_804_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC94 0x00000300  //DDRSS_PHY_805_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC98 0x00000300  //DDRSS_PHY_806_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC9C 0x42080010  //DDRSS_PHY_807_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA0 0x0000003E  //DDRSS_PHY_808_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA4 0x00000000  //DDRSS_PHY_809_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA8 0x00000000  //DDRSS_PHY_810_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D000 0x00000100  //DDRSS_PHY_1024_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D004 0x00001000  //DDRSS_PHY_1025_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D008 0x00070000  //DDRSS_PHY_1026_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D00C 0x00000000  //DDRSS_PHY_1027_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D010 0x00000000  //DDRSS_PHY_1028_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D014 0x00000100  //DDRSS_PHY_1029_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D018 0x00000000  //DDRSS_PHY_1030_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D01C 0x00000000  //DDRSS_PHY_1031_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D020 0x00000000  //DDRSS_PHY_1032_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D024 0x00000000  //DDRSS_PHY_1033_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D028 0x00000000  //DDRSS_PHY_1034_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D02C 0x00000000  //DDRSS_PHY_1035_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D030 0x00000000  //DDRSS_PHY_1036_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D034 0x00DCBA98  //DDRSS_PHY_1037_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D038 0x00000000  //DDRSS_PHY_1038_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D03C 0x00000000  //DDRSS_PHY_1039_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D040 0x00000000  //DDRSS_PHY_1040_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D044 0x00000000  //DDRSS_PHY_1041_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D048 0x00000000  //DDRSS_PHY_1042_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D04C 0x00000100  //DDRSS_PHY_1043_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D050 0x00000000  //DDRSS_PHY_1044_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D054 0x00000000  //DDRSS_PHY_1045_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D058 0x00000000  //DDRSS_PHY_1046_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D05C 0x00000000  //DDRSS_PHY_1047_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D060 0x00000000  //DDRSS_PHY_1048_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D064 0x00000000  //DDRSS_PHY_1049_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D068 0x00000000  //DDRSS_PHY_1050_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D06C 0x00000000  //DDRSS_PHY_1051_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D070 0x2307B9AC  //DDRSS_PHY_1052_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D074 0x10030000  //DDRSS_PHY_1053_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D078 0x000F0000  //DDRSS_PHY_1054_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D07C 0x0000000F  //DDRSS_PHY_1055_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D080 0x020002FF  //DDRSS_PHY_1056_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D084 0x00030000  //DDRSS_PHY_1057_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D088 0x00000300  //DDRSS_PHY_1058_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D08C 0x00000300  //DDRSS_PHY_1059_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D090 0x00000300  //DDRSS_PHY_1060_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D094 0x00000300  //DDRSS_PHY_1061_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D098 0x00000300  //DDRSS_PHY_1062_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D09C 0x42080010  //DDRSS_PHY_1063_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A0 0x0000003E  //DDRSS_PHY_1064_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A4 0x00000000  //DDRSS_PHY_1065_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A8 0x00000000  //DDRSS_PHY_1066_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D400 0x00000000  //DDRSS_PHY_1280_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D404 0x00000000  //DDRSS_PHY_1281_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D408 0x00000000  //DDRSS_PHY_1282_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D40C 0x00000000  //DDRSS_PHY_1283_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D410 0x00000000  //DDRSS_PHY_1284_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D414 0x00000000  //DDRSS_PHY_1285_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D418 0x00050000  //DDRSS_PHY_1286_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D41C 0x04000100  //DDRSS_PHY_1287_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D420 0x00000055  //DDRSS_PHY_1288_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D424 0x00000000  //DDRSS_PHY_1289_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D428 0x06800000  //DDRSS_PHY_1290_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D42C 0x00000000  //DDRSS_PHY_1291_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D430 0x00000000  //DDRSS_PHY_1292_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D434 0x01002000  //DDRSS_PHY_1293_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D438 0x00004001  //DDRSS_PHY_1294_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D43C 0x00020028  //DDRSS_PHY_1295_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D440 0x00010100  //DDRSS_PHY_1296_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D444 0x00000001  //DDRSS_PHY_1297_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D448 0x00000000  //DDRSS_PHY_1298_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D44C 0x0F0F0E06  //DDRSS_PHY_1299_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D450 0x00010101  //DDRSS_PHY_1300_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D454 0x010F0004  //DDRSS_PHY_1301_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D458 0x00000000  //DDRSS_PHY_1302_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D45C 0x20125770  //DDRSS_PHY_1303_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D460 0x00000064  //DDRSS_PHY_1304_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D464 0x00000000  //DDRSS_PHY_1305_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D468 0x00000000  //DDRSS_PHY_1306_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D46C 0x01020103  //DDRSS_PHY_1307_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D470 0x03020102  //DDRSS_PHY_1308_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D474 0x03030303  //DDRSS_PHY_1309_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D478 0x03030303  //DDRSS_PHY_1310_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D47C 0x00040000  //DDRSS_PHY_1311_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D480 0x00005201  //DDRSS_PHY_1312_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D484 0x00000003  //DDRSS_PHY_1313_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D488 0x00010000  //DDRSS_PHY_1314_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D48C 0x00000000  //DDRSS_PHY_1315_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D490 0x00000003  //DDRSS_PHY_1316_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D494 0x00010000  //DDRSS_PHY_1317_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D498 0x00000000  //DDRSS_PHY_1318_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D49C 0x07070001  //DDRSS_PHY_1319_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A0 0x00005400  //DDRSS_PHY_1320_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A4 0x000040A2  //DDRSS_PHY_1321_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A8 0x00034890  //DDRSS_PHY_1322_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4AC 0x00014890  //DDRSS_PHY_1323_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B0 0x00014890  //DDRSS_PHY_1324_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B4 0x00014890  //DDRSS_PHY_1325_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B8 0x0001488F  //DDRSS_PHY_1326_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4BC 0x0001488F  //DDRSS_PHY_1327_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C0 0x0001495E  //DDRSS_PHY_1328_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C4 0x0001495E  //DDRSS_PHY_1329_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C8 0x0001488F  //DDRSS_PHY_1330_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4CC 0x0001488F  //DDRSS_PHY_1331_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D0 0x00000000  //DDRSS_PHY_1332_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D4 0x00000046  //DDRSS_PHY_1333_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D8 0x00000400  //DDRSS_PHY_1334_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4DC 0x00000008  //DDRSS_PHY_1335_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E0 0x0081488F  //DDRSS_PHY_1336_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E4 0x0081495E  //DDRSS_PHY_1337_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E8 0x001488F0  //DDRSS_PHY_1338_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4EC 0x001495E8  //DDRSS_PHY_1339_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F0 0x00F488FF  //DDRSS_PHY_1340_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F4 0x03F495EF  //DDRSS_PHY_1341_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F8 0x00000000  //DDRSS_PHY_1342_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4FC 0x00000000  //DDRSS_PHY_1343_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D500 0xB3000000  //DDRSS_PHY_1344_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D504 0x04102006  //DDRSS_PHY_1345_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D508 0x00041020  //DDRSS_PHY_1346_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D50C 0x01C98C98  //DDRSS_PHY_1347_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D510 0x3F400000  //DDRSS_PHY_1348_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D514 0x3F3F1F3F  //DDRSS_PHY_1349_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D518 0x0000001F  //DDRSS_PHY_1350_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D51C 0x00000000  //DDRSS_PHY_1351_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D520 0x00000000  //DDRSS_PHY_1352_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D524 0x00000000  //DDRSS_PHY_1353_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D528 0x00000001  //DDRSS_PHY_1354_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D52C 0x00000000  //DDRSS_PHY_1355_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D530 0x00000000  //DDRSS_PHY_1356_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D534 0x00000000  //DDRSS_PHY_1357_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D538 0x00000000  //DDRSS_PHY_1358_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D53C 0x76543210  //DDRSS_PHY_1359_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D540 0x00000098  //DDRSS_PHY_1360_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D544 0x00000000  //DDRSS_PHY_1361_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D548 0x00000000  //DDRSS_PHY_1362_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D54C 0x00000000  //DDRSS_PHY_1363_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D550 0x00040700  //DDRSS_PHY_1364_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D554 0x00000000  //DDRSS_PHY_1365_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D558 0x00000000  //DDRSS_PHY_1366_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D55C 0x00000000  //DDRSS_PHY_1367_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D560 0x030F7102  //DDRSS_PHY_1368_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D564 0x00000100  //DDRSS_PHY_1369_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D568 0x00000000  //DDRSS_PHY_1370_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D56C 0x0001F7C2  //DDRSS_PHY_1371_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D570 0x00020002  //DDRSS_PHY_1372_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D574 0x00000000  //DDRSS_PHY_1373_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D578 0x00001142  //DDRSS_PHY_1374_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D57C 0x03020400  //DDRSS_PHY_1375_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D580 0x00000080  //DDRSS_PHY_1376_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D584 0x03900390  //DDRSS_PHY_1377_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D588 0x03900390  //DDRSS_PHY_1378_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D58C 0x03900390  //DDRSS_PHY_1379_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D590 0x03900390  //DDRSS_PHY_1380_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D594 0x03900390  //DDRSS_PHY_1381_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D598 0x03900390  //DDRSS_PHY_1382_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D59C 0x00000300  //DDRSS_PHY_1383_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A0 0x00000300  //DDRSS_PHY_1384_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A4 0x00000300  //DDRSS_PHY_1385_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A8 0x00000300  //DDRSS_PHY_1386_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5AC 0x31823FF7  //DDRSS_PHY_1387_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B0 0x00000000  //DDRSS_PHY_1388_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B4 0x0C000D3F  //DDRSS_PHY_1389_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B8 0x30000D3F  //DDRSS_PHY_1390_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5BC 0x300D3F11  //DDRSS_PHY_1391_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C0 0x01FF0000  //DDRSS_PHY_1392_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C4 0x000D3FFF  //DDRSS_PHY_1393_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C8 0x00000C11  //DDRSS_PHY_1394_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5CC 0x300D3F11  //DDRSS_PHY_1395_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D0 0x01FF0000  //DDRSS_PHY_1396_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D4 0x300C3F11  //DDRSS_PHY_1397_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D8 0x01FF0000  //DDRSS_PHY_1398_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5DC 0x300C3F11  //DDRSS_PHY_1399_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E0 0x01FF0000  //DDRSS_PHY_1400_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E4 0x300D3F11  //DDRSS_PHY_1401_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E8 0x01FF0000  //DDRSS_PHY_1402_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5EC 0x300D3F11  //DDRSS_PHY_1403_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F0 0x01FF0000  //DDRSS_PHY_1404_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F4 0x20040004  //DDRSS_PHY_1405_DATA_F0

And here is the register dump when the program has run several cycles of DDR write and read:

MAIN_Cortex_R5_0_0: GEL Output: 0x0F308000 0x10460A01  //DDRSS_CTL_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308004 0x5D1AF3C3  //DDRSS_CTL_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308008 0x0171A610  //DDRSS_CTL_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30800C 0x40020A11  //DDRSS_CTL_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308010 0x00052006  //DDRSS_CTL_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308014 0x02050020  //DDRSS_CTL_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308018 0x03070101  //DDRSS_CTL_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30801C 0x00089070  //DDRSS_CTL_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308020 0x00000000  //DDRSS_CTL_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308024 0x00000000  //DDRSS_CTL_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308028 0x00000000  //DDRSS_CTL_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30802C 0x00089070  //DDRSS_CTL_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308030 0x00000000  //DDRSS_CTL_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308034 0x00000000  //DDRSS_CTL_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308038 0x00000000  //DDRSS_CTL_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30803C 0x00089070  //DDRSS_CTL_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308040 0x00000000  //DDRSS_CTL_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308044 0x00000000  //DDRSS_CTL_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308048 0x00000000  //DDRSS_CTL_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30804C 0x01010100  //DDRSS_CTL_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308050 0x01000101  //DDRSS_CTL_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308054 0x01000110  //DDRSS_CTL_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308058 0x02010002  //DDRSS_CTL_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30805C 0x00027100  //DDRSS_CTL_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308060 0x00061A80  //DDRSS_CTL_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308064 0x02550255  //DDRSS_CTL_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308068 0x00000255  //DDRSS_CTL_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30806C 0x00000000  //DDRSS_CTL_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308070 0x00000000  //DDRSS_CTL_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308074 0x00000000  //DDRSS_CTL_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308078 0x00000000  //DDRSS_CTL_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30807C 0x00000000  //DDRSS_CTL_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308080 0x00000000  //DDRSS_CTL_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308084 0x00000000  //DDRSS_CTL_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308088 0x00000000  //DDRSS_CTL_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30808C 0x00000000  //DDRSS_CTL_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308090 0x00000000  //DDRSS_CTL_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308094 0x00000000  //DDRSS_CTL_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308098 0x04000B16  //DDRSS_CTL_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30809C 0x1C1C1C1C  //DDRSS_CTL_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A0 0x04000B16  //DDRSS_CTL_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A4 0x1C1C1C1C  //DDRSS_CTL_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A8 0x04000B16  //DDRSS_CTL_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080AC 0x1C1C1C1C  //DDRSS_CTL_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B0 0x05050404  //DDRSS_CTL_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B4 0x00002706  //DDRSS_CTL_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B8 0x0602001D  //DDRSS_CTL_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080BC 0x05001D0B  //DDRSS_CTL_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C0 0x00270605  //DDRSS_CTL_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C4 0x0602001D  //DDRSS_CTL_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C8 0x05001D0B  //DDRSS_CTL_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080CC 0x00270605  //DDRSS_CTL_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D0 0x0602001D  //DDRSS_CTL_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D4 0x07001D0B  //DDRSS_CTL_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D8 0x00180807  //DDRSS_CTL_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080DC 0x0400DB60  //DDRSS_CTL_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E0 0x07070009  //DDRSS_CTL_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E4 0x00001808  //DDRSS_CTL_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E8 0x0400DB60  //DDRSS_CTL_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080EC 0x07070009  //DDRSS_CTL_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F0 0x00001808  //DDRSS_CTL_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F4 0x0400DB60  //DDRSS_CTL_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F8 0x03000009  //DDRSS_CTL_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080FC 0x0D0C0002  //DDRSS_CTL_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308100 0x0D0C0D0C  //DDRSS_CTL_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308104 0x01010000  //DDRSS_CTL_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308108 0x03191919  //DDRSS_CTL_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30810C 0x0B0B0B0B  //DDRSS_CTL_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308110 0x00000B0B  //DDRSS_CTL_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308114 0x00000101  //DDRSS_CTL_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308118 0x00000000  //DDRSS_CTL_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30811C 0x01000000  //DDRSS_CTL_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308120 0x00D00803  //DDRSS_CTL_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308124 0x00001860  //DDRSS_CTL_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308128 0x000000D0  //DDRSS_CTL_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30812C 0x00001860  //DDRSS_CTL_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308130 0x000000D0  //DDRSS_CTL_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308134 0x00001860  //DDRSS_CTL_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308138 0x00000005  //DDRSS_CTL_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30813C 0x00000000  //DDRSS_CTL_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308140 0x00000000  //DDRSS_CTL_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308144 0x00000000  //DDRSS_CTL_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308148 0x00000000  //DDRSS_CTL_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30814C 0x00000000  //DDRSS_CTL_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308150 0x00000000  //DDRSS_CTL_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308154 0x00000000  //DDRSS_CTL_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308158 0x00000000  //DDRSS_CTL_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30815C 0x00090009  //DDRSS_CTL_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308160 0x00000009  //DDRSS_CTL_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308164 0x00000000  //DDRSS_CTL_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308168 0x00000000  //DDRSS_CTL_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30816C 0x00000000  //DDRSS_CTL_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308170 0x00000000  //DDRSS_CTL_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308174 0x00000000  //DDRSS_CTL_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308178 0x00010001  //DDRSS_CTL_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30817C 0x00025501  //DDRSS_CTL_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308180 0x025500D8  //DDRSS_CTL_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308184 0x025500D8  //DDRSS_CTL_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308188 0x00D800D8  //DDRSS_CTL_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30818C 0x00D800D8  //DDRSS_CTL_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308190 0x00000000  //DDRSS_CTL_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308194 0x00000000  //DDRSS_CTL_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308198 0x00000000  //DDRSS_CTL_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30819C 0x00000000  //DDRSS_CTL_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A0 0x00000000  //DDRSS_CTL_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A4 0x00000000  //DDRSS_CTL_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A8 0x03010000  //DDRSS_CTL_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081AC 0x00010000  //DDRSS_CTL_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B0 0x00000000  //DDRSS_CTL_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B4 0x01000000  //DDRSS_CTL_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B8 0x80104002  //DDRSS_CTL_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081BC 0x00040003  //DDRSS_CTL_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C0 0x00040005  //DDRSS_CTL_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C4 0x00030000  //DDRSS_CTL_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C8 0x00050004  //DDRSS_CTL_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081CC 0x00000004  //DDRSS_CTL_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D0 0x00040003  //DDRSS_CTL_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D4 0x00040005  //DDRSS_CTL_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D8 0x00000000  //DDRSS_CTL_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081DC 0x00061800  //DDRSS_CTL_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E0 0x00061800  //DDRSS_CTL_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E4 0x00061800  //DDRSS_CTL_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E8 0x00061800  //DDRSS_CTL_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081EC 0x00061800  //DDRSS_CTL_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F0 0x00000000  //DDRSS_CTL_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F4 0x0000AAA0  //DDRSS_CTL_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F8 0x00061800  //DDRSS_CTL_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081FC 0x00061800  //DDRSS_CTL_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308200 0x00061800  //DDRSS_CTL_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308204 0x00061800  //DDRSS_CTL_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308208 0x00061800  //DDRSS_CTL_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30820C 0x00000000  //DDRSS_CTL_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308210 0x0000AAA0  //DDRSS_CTL_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308214 0x00061800  //DDRSS_CTL_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308218 0x00061800  //DDRSS_CTL_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30821C 0x00061800  //DDRSS_CTL_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308220 0x00061800  //DDRSS_CTL_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308224 0x00061800  //DDRSS_CTL_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308228 0x00000000  //DDRSS_CTL_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30822C 0x0000AAA0  //DDRSS_CTL_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308230 0x00000000  //DDRSS_CTL_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308234 0x00000000  //DDRSS_CTL_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308238 0x00000000  //DDRSS_CTL_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30823C 0x00000000  //DDRSS_CTL_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308240 0x00000000  //DDRSS_CTL_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308244 0x00000000  //DDRSS_CTL_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308248 0x00000000  //DDRSS_CTL_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30824C 0x00000000  //DDRSS_CTL_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308250 0x00000000  //DDRSS_CTL_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308254 0x00000000  //DDRSS_CTL_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308258 0x00000000  //DDRSS_CTL_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30825C 0x00000000  //DDRSS_CTL_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308260 0x00000000  //DDRSS_CTL_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308264 0x00000000  //DDRSS_CTL_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308268 0x00000000  //DDRSS_CTL_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30826C 0x00000000  //DDRSS_CTL_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308270 0x080C0000  //DDRSS_CTL_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308274 0x080C080C  //DDRSS_CTL_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308278 0x00000000  //DDRSS_CTL_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30827C 0x07010A09  //DDRSS_CTL_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308280 0x000E0A09  //DDRSS_CTL_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308284 0x010A0900  //DDRSS_CTL_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308288 0x0E0A0907  //DDRSS_CTL_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30828C 0x0A090000  //DDRSS_CTL_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308290 0x0A090701  //DDRSS_CTL_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308294 0x0000080E  //DDRSS_CTL_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308298 0x00040003  //DDRSS_CTL_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30829C 0x00004007  //DDRSS_CTL_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A0 0x00000000  //DDRSS_CTL_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A4 0x00000000  //DDRSS_CTL_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A8 0x00000000  //DDRSS_CTL_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082AC 0x00000000  //DDRSS_CTL_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B0 0x00000000  //DDRSS_CTL_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B4 0x00000000  //DDRSS_CTL_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B8 0x01000000  //DDRSS_CTL_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082BC 0x00000000  //DDRSS_CTL_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C0 0x00001500  //DDRSS_CTL_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C4 0x0000100E  //DDRSS_CTL_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C8 0x00000000  //DDRSS_CTL_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082CC 0x00000000  //DDRSS_CTL_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D0 0x00000001  //DDRSS_CTL_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D4 0x00000002  //DDRSS_CTL_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D8 0x00000C00  //DDRSS_CTL_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082DC 0x00001000  //DDRSS_CTL_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E0 0x00000C00  //DDRSS_CTL_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E4 0x00001000  //DDRSS_CTL_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E8 0x00000C00  //DDRSS_CTL_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082EC 0x00001000  //DDRSS_CTL_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F0 0x00000000  //DDRSS_CTL_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F4 0x00000000  //DDRSS_CTL_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F8 0x00000000  //DDRSS_CTL_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082FC 0x00000000  //DDRSS_CTL_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308300 0x00000000  //DDRSS_CTL_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308304 0x00000000  //DDRSS_CTL_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308308 0x00000000  //DDRSS_CTL_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30830C 0x00000000  //DDRSS_CTL_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308310 0x00000000  //DDRSS_CTL_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308314 0x00000000  //DDRSS_CTL_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308318 0x00000000  //DDRSS_CTL_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30831C 0x00000000  //DDRSS_CTL_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308320 0x00000000  //DDRSS_CTL_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308324 0x00000000  //DDRSS_CTL_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308328 0x00000000  //DDRSS_CTL_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30832C 0x00000000  //DDRSS_CTL_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308330 0x00041000  //DDRSS_CTL_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308334 0x00000503  //DDRSS_CTL_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308338 0x00000010  //DDRSS_CTL_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30833C 0x00000410  //DDRSS_CTL_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308340 0x00000503  //DDRSS_CTL_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308344 0x00000010  //DDRSS_CTL_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308348 0x00000410  //DDRSS_CTL_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30834C 0x00000503  //DDRSS_CTL_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308350 0x00000010  //DDRSS_CTL_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308354 0x00000410  //DDRSS_CTL_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308358 0x00000503  //DDRSS_CTL_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30835C 0x00000010  //DDRSS_CTL_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308360 0x00000410  //DDRSS_CTL_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308364 0x00000503  //DDRSS_CTL_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308368 0x00000010  //DDRSS_CTL_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30836C 0x00000410  //DDRSS_CTL_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308370 0x00000503  //DDRSS_CTL_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308374 0x00000010  //DDRSS_CTL_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308378 0x00000000  //DDRSS_CTL_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30837C 0x00000000  //DDRSS_CTL_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308380 0x00000000  //DDRSS_CTL_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308384 0x00000000  //DDRSS_CTL_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308388 0x00000000  //DDRSS_CTL_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30838C 0x00000000  //DDRSS_CTL_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308390 0x00000000  //DDRSS_CTL_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308394 0x00000000  //DDRSS_CTL_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308398 0x00000000  //DDRSS_CTL_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30839C 0x00000000  //DDRSS_CTL_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A0 0x00000000  //DDRSS_CTL_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A4 0x00000000  //DDRSS_CTL_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A8 0x00000000  //DDRSS_CTL_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083AC 0x00000000  //DDRSS_CTL_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B0 0x00001401  //DDRSS_CTL_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B4 0x00001401  //DDRSS_CTL_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B8 0x00001401  //DDRSS_CTL_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083BC 0x00001401  //DDRSS_CTL_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C0 0x00001401  //DDRSS_CTL_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C4 0x00001401  //DDRSS_CTL_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C8 0x00000493  //DDRSS_CTL_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083CC 0x00000493  //DDRSS_CTL_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D0 0x00000493  //DDRSS_CTL_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D4 0x00000493  //DDRSS_CTL_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D8 0x00000493  //DDRSS_CTL_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083DC 0x00000493  //DDRSS_CTL_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E0 0x00000000  //DDRSS_CTL_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E4 0x00000000  //DDRSS_CTL_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E8 0x00000000  //DDRSS_CTL_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083EC 0x00000000  //DDRSS_CTL_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F0 0x00000000  //DDRSS_CTL_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F4 0x00000000  //DDRSS_CTL_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F8 0x00000000  //DDRSS_CTL_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083FC 0x00000000  //DDRSS_CTL_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308400 0x00000000  //DDRSS_CTL_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308404 0x00000000  //DDRSS_CTL_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308408 0x00000000  //DDRSS_CTL_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30840C 0x00000000  //DDRSS_CTL_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308410 0x00000000  //DDRSS_CTL_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308414 0x00000000  //DDRSS_CTL_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308418 0x00000000  //DDRSS_CTL_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30841C 0x00000000  //DDRSS_CTL_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308420 0x00000000  //DDRSS_CTL_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308424 0x00000000  //DDRSS_CTL_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308428 0x00000000  //DDRSS_CTL_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30842C 0x00000000  //DDRSS_CTL_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308430 0x00000000  //DDRSS_CTL_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308434 0x00000000  //DDRSS_CTL_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308438 0x00000000  //DDRSS_CTL_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30843C 0x00000000  //DDRSS_CTL_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308440 0x00000000  //DDRSS_CTL_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308444 0x00000000  //DDRSS_CTL_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308448 0x00000000  //DDRSS_CTL_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30844C 0x00000000  //DDRSS_CTL_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308450 0x00000000  //DDRSS_CTL_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308454 0x00010000  //DDRSS_CTL_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308458 0x00000000  //DDRSS_CTL_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30845C 0x00000100  //DDRSS_CTL_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308460 0x00000000  //DDRSS_CTL_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308464 0x00000101  //DDRSS_CTL_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308468 0x00000000  //DDRSS_CTL_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30846C 0x00000000  //DDRSS_CTL_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308470 0x00000000  //DDRSS_CTL_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308474 0x00000000  //DDRSS_CTL_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308478 0x00000000  //DDRSS_CTL_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30847C 0x00000000  //DDRSS_CTL_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308480 0x00000000  //DDRSS_CTL_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308484 0x00000FFF  //DDRSS_CTL_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308488 0x0C181511  //DDRSS_CTL_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30848C 0x00000304  //DDRSS_CTL_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308490 0x00000000  //DDRSS_CTL_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308494 0x00000000  //DDRSS_CTL_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308498 0x00000000  //DDRSS_CTL_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30849C 0x00000000  //DDRSS_CTL_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A0 0x00000000  //DDRSS_CTL_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A4 0x00000000  //DDRSS_CTL_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A8 0x00000000  //DDRSS_CTL_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084AC 0x00000000  //DDRSS_CTL_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B0 0x00000000  //DDRSS_CTL_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B4 0x00000000  //DDRSS_CTL_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B8 0x00000000  //DDRSS_CTL_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084BC 0x00000000  //DDRSS_CTL_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C0 0x00000000  //DDRSS_CTL_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C4 0x00040000  //DDRSS_CTL_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C8 0x00800200  //DDRSS_CTL_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084CC 0x00000000  //DDRSS_CTL_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D0 0x02000400  //DDRSS_CTL_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D4 0x00000080  //DDRSS_CTL_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D8 0x00040000  //DDRSS_CTL_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084DC 0x00800200  //DDRSS_CTL_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E0 0x00000000  //DDRSS_CTL_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E4 0x00000000  //DDRSS_CTL_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E8 0x00000000  //DDRSS_CTL_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084EC 0x00000100  //DDRSS_CTL_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F0 0x01010000  //DDRSS_CTL_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F4 0x00000202  //DDRSS_CTL_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F8 0x0FFF0000  //DDRSS_CTL_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084FC 0x000FFF00  //DDRSS_CTL_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308500 0xFFFFFFFF  //DDRSS_CTL_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308504 0x00FFFF00  //DDRSS_CTL_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308508 0x0A000000  //DDRSS_CTL_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30850C 0x0001FFFF  //DDRSS_CTL_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308510 0x01010101  //DDRSS_CTL_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308514 0x01010101  //DDRSS_CTL_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308518 0x00000118  //DDRSS_CTL_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30851C 0x00000C01  //DDRSS_CTL_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308520 0x00000000  //DDRSS_CTL_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308524 0x00000000  //DDRSS_CTL_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308528 0x00000000  //DDRSS_CTL_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30852C 0x01000000  //DDRSS_CTL_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308530 0x00000100  //DDRSS_CTL_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308534 0x00010000  //DDRSS_CTL_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308538 0x00000000  //DDRSS_CTL_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30853C 0x00000000  //DDRSS_CTL_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308540 0x00000000  //DDRSS_CTL_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308544 0x00000000  //DDRSS_CTL_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308548 0x00000000  //DDRSS_CTL_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30854C 0x00000000  //DDRSS_CTL_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308550 0x00000000  //DDRSS_CTL_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308554 0x00000000  //DDRSS_CTL_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308558 0x00000000  //DDRSS_CTL_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30855C 0x00000000  //DDRSS_CTL_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308560 0x00000000  //DDRSS_CTL_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308564 0x00000000  //DDRSS_CTL_345_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308568 0x00000000  //DDRSS_CTL_346_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30856C 0x00000000  //DDRSS_CTL_347_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308570 0x00000000  //DDRSS_CTL_348_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308574 0x00000000  //DDRSS_CTL_349_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308578 0x00000000  //DDRSS_CTL_350_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30857C 0x00000000  //DDRSS_CTL_351_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308580 0x00000000  //DDRSS_CTL_352_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308584 0x00000000  //DDRSS_CTL_353_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308588 0x00000000  //DDRSS_CTL_354_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30858C 0x00000000  //DDRSS_CTL_355_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308590 0x00000000  //DDRSS_CTL_356_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308594 0x00000000  //DDRSS_CTL_357_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308598 0x00000000  //DDRSS_CTL_358_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30859C 0x00000000  //DDRSS_CTL_359_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A0 0x00000000  //DDRSS_CTL_360_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A4 0x00000000  //DDRSS_CTL_361_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A8 0x00000000  //DDRSS_CTL_362_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085AC 0x00000000  //DDRSS_CTL_363_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B0 0x00000000  //DDRSS_CTL_364_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B4 0x00000001  //DDRSS_CTL_365_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B8 0x00000001  //DDRSS_CTL_366_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085BC 0x0000A670  //DDRSS_CTL_367_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C0 0x00000000  //DDRSS_CTL_368_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C4 0x00000000  //DDRSS_CTL_369_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C8 0x0E000000  //DDRSS_CTL_370_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085CC 0x060E0606  //DDRSS_CTL_371_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D0 0x06060E06  //DDRSS_CTL_372_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D4 0x00010101  //DDRSS_CTL_373_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D8 0x02000000  //DDRSS_CTL_374_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085DC 0x00020101  //DDRSS_CTL_375_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E0 0x00000000  //DDRSS_CTL_376_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E4 0x02020200  //DDRSS_CTL_377_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E8 0x02020202  //DDRSS_CTL_378_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085EC 0x02020202  //DDRSS_CTL_379_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F0 0x02020202  //DDRSS_CTL_380_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F4 0x00000000  //DDRSS_CTL_381_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F8 0x00000000  //DDRSS_CTL_382_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085FC 0x04000100  //DDRSS_CTL_383_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308600 0x1E000304  //DDRSS_CTL_384_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308604 0x000030C0  //DDRSS_CTL_385_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308608 0x00000200  //DDRSS_CTL_386_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30860C 0x00000200  //DDRSS_CTL_387_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308610 0x00000200  //DDRSS_CTL_388_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308614 0x00000200  //DDRSS_CTL_389_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308618 0x0000DB60  //DDRSS_CTL_390_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30861C 0x0001E780  //DDRSS_CTL_391_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308620 0x090A0302  //DDRSS_CTL_392_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308624 0x001E0B0C  //DDRSS_CTL_393_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308628 0x000030C0  //DDRSS_CTL_394_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30862C 0x00000200  //DDRSS_CTL_395_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308630 0x00000200  //DDRSS_CTL_396_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308634 0x00000200  //DDRSS_CTL_397_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308638 0x00000200  //DDRSS_CTL_398_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30863C 0x0000DB60  //DDRSS_CTL_399_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308640 0x0001E780  //DDRSS_CTL_400_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308644 0x090A0302  //DDRSS_CTL_401_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308648 0x001E0B0C  //DDRSS_CTL_402_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30864C 0x000030C0  //DDRSS_CTL_403_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308650 0x00000200  //DDRSS_CTL_404_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308654 0x00000200  //DDRSS_CTL_405_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308658 0x00000200  //DDRSS_CTL_406_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30865C 0x00000200  //DDRSS_CTL_407_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308660 0x0000DB60  //DDRSS_CTL_408_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308664 0x0001E780  //DDRSS_CTL_409_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308668 0x090A0302  //DDRSS_CTL_410_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30866C 0x00000B0C  //DDRSS_CTL_411_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308670 0x00000000  //DDRSS_CTL_412_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308674 0x0302000A  //DDRSS_CTL_413_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308678 0x01000500  //DDRSS_CTL_414_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30867C 0x01010001  //DDRSS_CTL_415_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308680 0x00010001  //DDRSS_CTL_416_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308684 0x01010001  //DDRSS_CTL_417_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308688 0x02010000  //DDRSS_CTL_418_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30868C 0x00000200  //DDRSS_CTL_419_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308690 0x02000201  //DDRSS_CTL_420_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308694 0x00000000  //DDRSS_CTL_421_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308698 0x00202020  //DDRSS_CTL_422_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A000 0x00000A01  //DDRSS_PI_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A004 0xAE8D79E2  //DDRSS_PI_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A008 0x0714B570  //DDRSS_PI_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A00C 0x01011387  //DDRSS_PI_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A010 0x00000001  //DDRSS_PI_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A014 0x00010064  //DDRSS_PI_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A018 0x00000000  //DDRSS_PI_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A01C 0x00000000  //DDRSS_PI_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A020 0x00000000  //DDRSS_PI_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A024 0x00000003  //DDRSS_PI_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A028 0x0000000F  //DDRSS_PI_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A02C 0x00000000  //DDRSS_PI_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A030 0x00000000  //DDRSS_PI_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A034 0x00010001  //DDRSS_PI_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A038 0x00000000  //DDRSS_PI_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A03C 0x00010001  //DDRSS_PI_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A040 0x00000005  //DDRSS_PI_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A044 0x00010000  //DDRSS_PI_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A048 0x00000000  //DDRSS_PI_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A04C 0x00000000  //DDRSS_PI_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A050 0x00000000  //DDRSS_PI_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A054 0x00000000  //DDRSS_PI_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A058 0x00000000  //DDRSS_PI_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A05C 0x00000000  //DDRSS_PI_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A060 0x280D0001  //DDRSS_PI_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A064 0x00000000  //DDRSS_PI_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A068 0x00010000  //DDRSS_PI_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A06C 0x00003200  //DDRSS_PI_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A070 0x00000000  //DDRSS_PI_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A074 0x00000000  //DDRSS_PI_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A078 0x00060602  //DDRSS_PI_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A07C 0x00000000  //DDRSS_PI_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A080 0x00000000  //DDRSS_PI_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A084 0x00000000  //DDRSS_PI_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A088 0x00000001  //DDRSS_PI_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A08C 0x00000055  //DDRSS_PI_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A090 0x000000AA  //DDRSS_PI_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A094 0x000000AD  //DDRSS_PI_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A098 0x00000052  //DDRSS_PI_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A09C 0x0000006A  //DDRSS_PI_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A0 0x00000095  //DDRSS_PI_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A4 0x00000095  //DDRSS_PI_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A8 0x000000AD  //DDRSS_PI_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0AC 0x00000000  //DDRSS_PI_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B0 0x00000000  //DDRSS_PI_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B4 0x00010100  //DDRSS_PI_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B8 0x00000014  //DDRSS_PI_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0BC 0x000007D0  //DDRSS_PI_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C0 0x00000300  //DDRSS_PI_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C4 0x00000000  //DDRSS_PI_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C8 0x00000000  //DDRSS_PI_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0CC 0x01000000  //DDRSS_PI_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D0 0x00010101  //DDRSS_PI_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D4 0x01000B09  //DDRSS_PI_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D8 0x00000000  //DDRSS_PI_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0DC 0x00010000  //DDRSS_PI_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E0 0x00000000  //DDRSS_PI_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E4 0x00000000  //DDRSS_PI_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E8 0x00000000  //DDRSS_PI_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0EC 0x00000000  //DDRSS_PI_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F0 0x00001400  //DDRSS_PI_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F4 0x00000000  //DDRSS_PI_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F8 0x01000000  //DDRSS_PI_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0FC 0x00000404  //DDRSS_PI_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A100 0x00000001  //DDRSS_PI_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A104 0x0001010E  //DDRSS_PI_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A108 0x02040100  //DDRSS_PI_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A10C 0x00010000  //DDRSS_PI_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A110 0x00000034  //DDRSS_PI_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A114 0x00000000  //DDRSS_PI_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A118 0x00000000  //DDRSS_PI_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A11C 0x00000000  //DDRSS_PI_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A120 0x00000000  //DDRSS_PI_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A124 0x00000000  //DDRSS_PI_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A128 0x00000000  //DDRSS_PI_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A12C 0x00000005  //DDRSS_PI_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A130 0x01000000  //DDRSS_PI_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A134 0x04020100  //DDRSS_PI_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A138 0x00020000  //DDRSS_PI_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A13C 0x00010002  //DDRSS_PI_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A140 0x00000001  //DDRSS_PI_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A144 0x00020001  //DDRSS_PI_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A148 0x00020002  //DDRSS_PI_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A14C 0x29C02000  //DDRSS_PI_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A150 0x00000000  //DDRSS_PI_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A154 0x00000000  //DDRSS_PI_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A158 0x00000000  //DDRSS_PI_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A15C 0x00000000  //DDRSS_PI_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A160 0x00000000  //DDRSS_PI_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A164 0x00000000  //DDRSS_PI_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A168 0x00000000  //DDRSS_PI_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A16C 0x00000300  //DDRSS_PI_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A170 0x0A090B0C  //DDRSS_PI_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A174 0x04060708  //DDRSS_PI_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A178 0x01000005  //DDRSS_PI_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A17C 0x00000800  //DDRSS_PI_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A180 0x00000000  //DDRSS_PI_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A184 0x00010008  //DDRSS_PI_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A188 0x00000000  //DDRSS_PI_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A18C 0x0000AA00  //DDRSS_PI_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A190 0x00000000  //DDRSS_PI_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A194 0x00010000  //DDRSS_PI_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A198 0x00000000  //DDRSS_PI_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A19C 0x00000000  //DDRSS_PI_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A0 0x00000000  //DDRSS_PI_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A4 0x00000000  //DDRSS_PI_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A8 0x00000000  //DDRSS_PI_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1AC 0x00000000  //DDRSS_PI_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B0 0x00000000  //DDRSS_PI_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B4 0x00000000  //DDRSS_PI_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B8 0x00000000  //DDRSS_PI_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1BC 0x00000000  //DDRSS_PI_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C0 0x00000000  //DDRSS_PI_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C4 0x00000000  //DDRSS_PI_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C8 0x00000000  //DDRSS_PI_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1CC 0x00000000  //DDRSS_PI_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D0 0x00000000  //DDRSS_PI_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D4 0x00000000  //DDRSS_PI_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D8 0x00000000  //DDRSS_PI_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1DC 0x00000000  //DDRSS_PI_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E0 0x00000000  //DDRSS_PI_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E4 0x00000000  //DDRSS_PI_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E8 0x00000000  //DDRSS_PI_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1EC 0x00000000  //DDRSS_PI_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F0 0x00000008  //DDRSS_PI_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F4 0x00000000  //DDRSS_PI_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F8 0x00000000  //DDRSS_PI_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1FC 0x00000000  //DDRSS_PI_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A200 0x00000000  //DDRSS_PI_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A204 0x00000000  //DDRSS_PI_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A208 0x00000000  //DDRSS_PI_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A20C 0x00000000  //DDRSS_PI_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A210 0x00000000  //DDRSS_PI_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A214 0x00010100  //DDRSS_PI_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A218 0x00000000  //DDRSS_PI_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A21C 0x00000000  //DDRSS_PI_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A220 0x00027100  //DDRSS_PI_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A224 0x00061A80  //DDRSS_PI_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A228 0x00000100  //DDRSS_PI_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A22C 0x00000000  //DDRSS_PI_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A230 0x00000000  //DDRSS_PI_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A234 0x00000000  //DDRSS_PI_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A238 0x00000000  //DDRSS_PI_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A23C 0x00000000  //DDRSS_PI_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A240 0x01000000  //DDRSS_PI_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A244 0xC1010003  //DDRSS_PI_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A248 0x02000101  //DDRSS_PI_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A24C 0x01030101  //DDRSS_PI_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A250 0x00010400  //DDRSS_PI_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A254 0x06000105  //DDRSS_PI_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A258 0x01070001  //DDRSS_PI_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A25C 0x00000000  //DDRSS_PI_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A260 0x00000000  //DDRSS_PI_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A264 0x00000001  //DDRSS_PI_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A268 0x00010000  //DDRSS_PI_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A26C 0x00000000  //DDRSS_PI_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A270 0x00000000  //DDRSS_PI_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A274 0x00000000  //DDRSS_PI_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A278 0x00000000  //DDRSS_PI_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A27C 0x00010000  //DDRSS_PI_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A280 0x00000004  //DDRSS_PI_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A284 0x00000000  //DDRSS_PI_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A288 0x00000000  //DDRSS_PI_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A28C 0x00000000  //DDRSS_PI_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A290 0x00007800  //DDRSS_PI_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A294 0x00780078  //DDRSS_PI_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A298 0x00141414  //DDRSS_PI_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A29C 0x00000037  //DDRSS_PI_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A0 0x00000037  //DDRSS_PI_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A4 0x00040037  //DDRSS_PI_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A8 0x04000400  //DDRSS_PI_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2AC 0x6804000B  //DDRSS_PI_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B0 0x04000B16  //DDRSS_PI_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B4 0x000B1668  //DDRSS_PI_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B8 0x00166804  //DDRSS_PI_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2BC 0x000000D0  //DDRSS_PI_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C0 0x00001860  //DDRSS_PI_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C4 0x000000D0  //DDRSS_PI_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C8 0x00001860  //DDRSS_PI_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2CC 0x000000D0  //DDRSS_PI_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D0 0x04001860  //DDRSS_PI_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D4 0x01010404  //DDRSS_PI_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D8 0x00001901  //DDRSS_PI_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2DC 0x00190019  //DDRSS_PI_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E0 0x010E010E  //DDRSS_PI_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E4 0x0000010E  //DDRSS_PI_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E8 0x00000000  //DDRSS_PI_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2EC 0x00000000  //DDRSS_PI_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F0 0x01010000  //DDRSS_PI_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F4 0x01010101  //DDRSS_PI_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F8 0x00181818  //DDRSS_PI_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2FC 0x00000000  //DDRSS_PI_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A300 0x00000000  //DDRSS_PI_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A304 0x0A000000  //DDRSS_PI_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A308 0x0C0C0A0A  //DDRSS_PI_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A30C 0x0303030C  //DDRSS_PI_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A310 0x00000000  //DDRSS_PI_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A314 0x00000000  //DDRSS_PI_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A318 0x00000000  //DDRSS_PI_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A31C 0x00000000  //DDRSS_PI_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A320 0x00000000  //DDRSS_PI_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A324 0x00000000  //DDRSS_PI_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A328 0x00000000  //DDRSS_PI_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A32C 0x00000000  //DDRSS_PI_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A330 0x00000000  //DDRSS_PI_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A334 0x00000000  //DDRSS_PI_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A338 0x00000000  //DDRSS_PI_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A33C 0x00000000  //DDRSS_PI_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A340 0x00000000  //DDRSS_PI_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A344 0x0D090000  //DDRSS_PI_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A348 0x0D09000D  //DDRSS_PI_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A34C 0x0D09000D  //DDRSS_PI_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A350 0x0000000D  //DDRSS_PI_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A354 0x00000000  //DDRSS_PI_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A358 0x00000000  //DDRSS_PI_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A35C 0x00000000  //DDRSS_PI_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A360 0x00000000  //DDRSS_PI_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A364 0x16000000  //DDRSS_PI_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A368 0x001600C8  //DDRSS_PI_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A36C 0x001600C8  //DDRSS_PI_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A370 0x010100C8  //DDRSS_PI_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A374 0x00001D01  //DDRSS_PI_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A378 0x1F0F004E  //DDRSS_PI_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A37C 0x02000001  //DDRSS_PI_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A380 0x001D0A0A  //DDRSS_PI_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A384 0x1F0F004E  //DDRSS_PI_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A388 0x02000001  //DDRSS_PI_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A38C 0x001D0A0A  //DDRSS_PI_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A390 0x1F0F004E  //DDRSS_PI_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A394 0x02000001  //DDRSS_PI_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A398 0x00010A0A  //DDRSS_PI_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A39C 0x0C0B0700  //DDRSS_PI_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A0 0x000D0605  //DDRSS_PI_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A4 0x0000C570  //DDRSS_PI_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A8 0x0000001D  //DDRSS_PI_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3AC 0x180A0800  //DDRSS_PI_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B0 0x0B071C1C  //DDRSS_PI_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B4 0x0D06050C  //DDRSS_PI_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B8 0x0000C570  //DDRSS_PI_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3BC 0x0000001D  //DDRSS_PI_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C0 0x180A0800  //DDRSS_PI_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C4 0x0B071C1C  //DDRSS_PI_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C8 0x0D06050C  //DDRSS_PI_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3CC 0x0000C570  //DDRSS_PI_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D0 0x0000001D  //DDRSS_PI_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D4 0x180A0800  //DDRSS_PI_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D8 0x00001C1C  //DDRSS_PI_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3DC 0x000030C0  //DDRSS_PI_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E0 0x0001E780  //DDRSS_PI_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E4 0x000030C0  //DDRSS_PI_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E8 0x0001E780  //DDRSS_PI_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3EC 0x000030C0  //DDRSS_PI_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F0 0x0001E780  //DDRSS_PI_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F4 0x02550255  //DDRSS_PI_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F8 0x03030255  //DDRSS_PI_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3FC 0x00025503  //DDRSS_PI_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A400 0x02550255  //DDRSS_PI_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A404 0x0C080C08  //DDRSS_PI_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A408 0x00000C08  //DDRSS_PI_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A40C 0x00089070  //DDRSS_PI_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A410 0x00000000  //DDRSS_PI_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A414 0x00000000  //DDRSS_PI_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A418 0x00000000  //DDRSS_PI_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A41C 0x000000D8  //DDRSS_PI_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A420 0x00089070  //DDRSS_PI_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A424 0x00000000  //DDRSS_PI_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A428 0x00000000  //DDRSS_PI_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A42C 0x00000000  //DDRSS_PI_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A430 0x000000D8  //DDRSS_PI_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A434 0x00089070  //DDRSS_PI_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A438 0x00000000  //DDRSS_PI_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A43C 0x00000000  //DDRSS_PI_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A440 0x00000000  //DDRSS_PI_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A444 0x020000D8  //DDRSS_PI_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A448 0x00000080  //DDRSS_PI_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A44C 0x00020000  //DDRSS_PI_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A450 0x00000080  //DDRSS_PI_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A454 0x00020000  //DDRSS_PI_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A458 0x00000080  //DDRSS_PI_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A45C 0x00000000  //DDRSS_PI_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A460 0x00000000  //DDRSS_PI_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A464 0x00040404  //DDRSS_PI_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A468 0x00000000  //DDRSS_PI_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A46C 0x02010102  //DDRSS_PI_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A470 0x67676767  //DDRSS_PI_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A474 0x00000202  //DDRSS_PI_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A478 0x00000000  //DDRSS_PI_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A47C 0x00000000  //DDRSS_PI_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A480 0x00000000  //DDRSS_PI_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A484 0x00000000  //DDRSS_PI_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A488 0x00000000  //DDRSS_PI_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A48C 0x0D100F00  //DDRSS_PI_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A490 0x0003020E  //DDRSS_PI_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A494 0x00000001  //DDRSS_PI_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A498 0x01000000  //DDRSS_PI_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A49C 0x00020201  //DDRSS_PI_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A0 0x00000000  //DDRSS_PI_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A4 0x00000410  //DDRSS_PI_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A8 0x00000503  //DDRSS_PI_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4AC 0x00000010  //DDRSS_PI_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B0 0x00000000  //DDRSS_PI_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B4 0x00000000  //DDRSS_PI_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B8 0x00001401  //DDRSS_PI_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4BC 0x00000493  //DDRSS_PI_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C0 0x00000000  //DDRSS_PI_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C4 0x00000410  //DDRSS_PI_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C8 0x00000503  //DDRSS_PI_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4CC 0x00000010  //DDRSS_PI_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D0 0x00000000  //DDRSS_PI_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D4 0x00000000  //DDRSS_PI_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D8 0x00001401  //DDRSS_PI_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4DC 0x00000493  //DDRSS_PI_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E0 0x00000000  //DDRSS_PI_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E4 0x00000410  //DDRSS_PI_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E8 0x00000503  //DDRSS_PI_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4EC 0x00000010  //DDRSS_PI_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F0 0x00000000  //DDRSS_PI_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F4 0x00000000  //DDRSS_PI_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F8 0x00001401  //DDRSS_PI_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4FC 0x00000493  //DDRSS_PI_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A500 0x00000000  //DDRSS_PI_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A504 0x00000410  //DDRSS_PI_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A508 0x00000503  //DDRSS_PI_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A50C 0x00000010  //DDRSS_PI_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A510 0x00000000  //DDRSS_PI_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A514 0x00000000  //DDRSS_PI_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A518 0x00001401  //DDRSS_PI_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A51C 0x00000493  //DDRSS_PI_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A520 0x00000000  //DDRSS_PI_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A524 0x00000410  //DDRSS_PI_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A528 0x00000503  //DDRSS_PI_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A52C 0x00000010  //DDRSS_PI_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A530 0x00000000  //DDRSS_PI_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A534 0x00000000  //DDRSS_PI_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A538 0x00001401  //DDRSS_PI_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A53C 0x00000493  //DDRSS_PI_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A540 0x00000000  //DDRSS_PI_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A544 0x00000410  //DDRSS_PI_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A548 0x00000503  //DDRSS_PI_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A54C 0x00000010  //DDRSS_PI_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A550 0x00000000  //DDRSS_PI_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A554 0x00000000  //DDRSS_PI_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A558 0x00001401  //DDRSS_PI_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A55C 0x00000493  //DDRSS_PI_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A560 0x00000000  //DDRSS_PI_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C000 0x04C00000  //DDRSS_PHY_0_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C004 0x00000000  //DDRSS_PHY_1_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C008 0x00000200  //DDRSS_PHY_2_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C00C 0x00000000  //DDRSS_PHY_3_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C010 0x00000000  //DDRSS_PHY_4_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C014 0x00000000  //DDRSS_PHY_5_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C018 0x00000000  //DDRSS_PHY_6_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C01C 0x00000000  //DDRSS_PHY_7_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C020 0x00000001  //DDRSS_PHY_8_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C024 0x00000000  //DDRSS_PHY_9_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C028 0x0A0C0000  //DDRSS_PHY_10_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C02C 0x010101FF  //DDRSS_PHY_11_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C030 0x00010000  //DDRSS_PHY_12_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C034 0x00C04004  //DDRSS_PHY_13_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C038 0x00CC0008  //DDRSS_PHY_14_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C03C 0x00660201  //DDRSS_PHY_15_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C040 0x00000000  //DDRSS_PHY_16_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C044 0x00000000  //DDRSS_PHY_17_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C048 0x00000000  //DDRSS_PHY_18_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C04C 0x0000AAAA  //DDRSS_PHY_19_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C050 0x00005555  //DDRSS_PHY_20_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C054 0x0000B5B5  //DDRSS_PHY_21_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C058 0x00004A4A  //DDRSS_PHY_22_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C05C 0x00005656  //DDRSS_PHY_23_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C060 0x0000A9A9  //DDRSS_PHY_24_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C064 0x0000B7B7  //DDRSS_PHY_25_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C068 0x00004848  //DDRSS_PHY_26_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C06C 0x00000000  //DDRSS_PHY_27_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C070 0x00000000  //DDRSS_PHY_28_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C074 0x08000000  //DDRSS_PHY_29_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C078 0x0F000008  //DDRSS_PHY_30_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C07C 0x00000F0F  //DDRSS_PHY_31_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C080 0x00E4E400  //DDRSS_PHY_32_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C084 0x00070820  //DDRSS_PHY_33_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C088 0x000C0020  //DDRSS_PHY_34_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C08C 0x00062000  //DDRSS_PHY_35_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C090 0x00000000  //DDRSS_PHY_36_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C094 0x55555555  //DDRSS_PHY_37_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C098 0xAAAAAAAA  //DDRSS_PHY_38_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C09C 0x55555555  //DDRSS_PHY_39_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A0 0xAAAAAAAA  //DDRSS_PHY_40_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A4 0x00005555  //DDRSS_PHY_41_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A8 0x01000100  //DDRSS_PHY_42_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0AC 0x00800180  //DDRSS_PHY_43_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B0 0x00000000  //DDRSS_PHY_44_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B4 0x00100000  //DDRSS_PHY_45_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B8 0x00000000  //DDRSS_PHY_46_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0BC 0x05070010  //DDRSS_PHY_47_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C0 0x0000000C  //DDRSS_PHY_48_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C4 0x00000000  //DDRSS_PHY_49_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C8 0x00300024  //DDRSS_PHY_50_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0CC 0x00000FFF  //DDRSS_PHY_51_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D0 0x00000000  //DDRSS_PHY_52_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D4 0x02B802AC  //DDRSS_PHY_53_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D8 0x00000030  //DDRSS_PHY_54_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0DC 0x0114003C  //DDRSS_PHY_55_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E0 0x00000000  //DDRSS_PHY_56_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E4 0x0C000000  //DDRSS_PHY_57_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E8 0x07FF0000  //DDRSS_PHY_58_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0EC 0x00000000  //DDRSS_PHY_59_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F0 0x00000000  //DDRSS_PHY_60_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F4 0x00000000  //DDRSS_PHY_61_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F8 0x00000000  //DDRSS_PHY_62_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0FC 0x00000000  //DDRSS_PHY_63_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C100 0x00000000  //DDRSS_PHY_64_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C104 0x00000004  //DDRSS_PHY_65_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C108 0x00000000  //DDRSS_PHY_66_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C10C 0x00000000  //DDRSS_PHY_67_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C110 0x00000000  //DDRSS_PHY_68_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C114 0x00000000  //DDRSS_PHY_69_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C118 0x00000000  //DDRSS_PHY_70_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C11C 0x00000000  //DDRSS_PHY_71_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C120 0x041F07FF  //DDRSS_PHY_72_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C124 0x00000000  //DDRSS_PHY_73_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C128 0x01CCB001  //DDRSS_PHY_74_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C12C 0x2000CCB0  //DDRSS_PHY_75_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C130 0x20000140  //DDRSS_PHY_76_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C134 0x07FF0200  //DDRSS_PHY_77_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C138 0x0000DD01  //DDRSS_PHY_78_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C13C 0x10100303  //DDRSS_PHY_79_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C140 0x10101010  //DDRSS_PHY_80_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C144 0x10101010  //DDRSS_PHY_81_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C148 0x00021010  //DDRSS_PHY_82_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C14C 0x00100010  //DDRSS_PHY_83_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C150 0x00100010  //DDRSS_PHY_84_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C154 0x00100010  //DDRSS_PHY_85_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C158 0x00100010  //DDRSS_PHY_86_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C15C 0x02020010  //DDRSS_PHY_87_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C160 0x51515041  //DDRSS_PHY_88_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C164 0x31804000  //DDRSS_PHY_89_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C168 0x04C00340  //DDRSS_PHY_90_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C16C 0x01008080  //DDRSS_PHY_91_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C170 0x04050001  //DDRSS_PHY_92_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C174 0x00000504  //DDRSS_PHY_93_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C178 0x42100010  //DDRSS_PHY_94_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C17C 0x010C053E  //DDRSS_PHY_95_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C180 0x000F0C14  //DDRSS_PHY_96_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C184 0x01000140  //DDRSS_PHY_97_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C188 0x007A0120  //DDRSS_PHY_98_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C18C 0x00000C00  //DDRSS_PHY_99_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C190 0x000001CC  //DDRSS_PHY_100_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C194 0x20100200  //DDRSS_PHY_101_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C198 0x00000005  //DDRSS_PHY_102_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C19C 0x76543210  //DDRSS_PHY_103_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A0 0x00000008  //DDRSS_PHY_104_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A4 0x02800280  //DDRSS_PHY_105_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A8 0x02800280  //DDRSS_PHY_106_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1AC 0x02800280  //DDRSS_PHY_107_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B0 0x02800280  //DDRSS_PHY_108_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B4 0x002A0280  //DDRSS_PHY_109_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B8 0x0000A800  //DDRSS_PHY_110_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1BC 0x00A800AE  //DDRSS_PHY_111_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C0 0x00A800B4  //DDRSS_PHY_112_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C4 0x00B400AE  //DDRSS_PHY_113_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C8 0x00B400BA  //DDRSS_PHY_114_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1CC 0x00A800B4  //DDRSS_PHY_115_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D0 0x00A800AE  //DDRSS_PHY_116_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D4 0x00A800AE  //DDRSS_PHY_117_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D8 0x00A800AE  //DDRSS_PHY_118_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1DC 0x01B200AE  //DDRSS_PHY_119_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E0 0x01000000  //DDRSS_PHY_120_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E4 0x00000000  //DDRSS_PHY_121_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E8 0x00000000  //DDRSS_PHY_122_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1EC 0x00080200  //DDRSS_PHY_123_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F0 0x00000000  //DDRSS_PHY_124_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F4 0x00000000  //DDRSS_PHY_125_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C400 0x04C00000  //DDRSS_PHY_256_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C404 0x00000000  //DDRSS_PHY_257_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C408 0x00000200  //DDRSS_PHY_258_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C40C 0x00000000  //DDRSS_PHY_259_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C410 0x00000000  //DDRSS_PHY_260_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C414 0x00000000  //DDRSS_PHY_261_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C418 0x00000000  //DDRSS_PHY_262_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C41C 0x00000000  //DDRSS_PHY_263_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C420 0x00000001  //DDRSS_PHY_264_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C424 0x00000000  //DDRSS_PHY_265_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C428 0x0A0C0000  //DDRSS_PHY_266_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C42C 0x010101FF  //DDRSS_PHY_267_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C430 0x00010000  //DDRSS_PHY_268_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C434 0x00C03C04  //DDRSS_PHY_269_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C438 0x00CC0008  //DDRSS_PHY_270_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C43C 0x00660201  //DDRSS_PHY_271_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C440 0x00000000  //DDRSS_PHY_272_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C444 0x00000000  //DDRSS_PHY_273_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C448 0x00000000  //DDRSS_PHY_274_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C44C 0x0000AAAA  //DDRSS_PHY_275_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C450 0x00005555  //DDRSS_PHY_276_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C454 0x0000B5B5  //DDRSS_PHY_277_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C458 0x00004A4A  //DDRSS_PHY_278_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C45C 0x00005656  //DDRSS_PHY_279_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C460 0x0000A9A9  //DDRSS_PHY_280_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C464 0x0000B7B7  //DDRSS_PHY_281_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C468 0x00004848  //DDRSS_PHY_282_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C46C 0x00000000  //DDRSS_PHY_283_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C470 0x00000000  //DDRSS_PHY_284_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C474 0x08000000  //DDRSS_PHY_285_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C478 0x0F000008  //DDRSS_PHY_286_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C47C 0x00000F0F  //DDRSS_PHY_287_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C480 0x00E4E400  //DDRSS_PHY_288_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C484 0x00070820  //DDRSS_PHY_289_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C488 0x000C0020  //DDRSS_PHY_290_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C48C 0x00062000  //DDRSS_PHY_291_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C490 0x00000000  //DDRSS_PHY_292_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C494 0x55555555  //DDRSS_PHY_293_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C498 0xAAAAAAAA  //DDRSS_PHY_294_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C49C 0x55555555  //DDRSS_PHY_295_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A0 0xAAAAAAAA  //DDRSS_PHY_296_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A4 0x00005555  //DDRSS_PHY_297_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A8 0x01000100  //DDRSS_PHY_298_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4AC 0x00800180  //DDRSS_PHY_299_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B0 0x00000000  //DDRSS_PHY_300_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B4 0x00100000  //DDRSS_PHY_301_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B8 0x00000000  //DDRSS_PHY_302_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4BC 0x14070010  //DDRSS_PHY_303_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C0 0x00000014  //DDRSS_PHY_304_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C4 0x00010600  //DDRSS_PHY_305_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C8 0x0048003C  //DDRSS_PHY_306_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4CC 0x00000FFF  //DDRSS_PHY_307_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D0 0x00000000  //DDRSS_PHY_308_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D4 0x02A00294  //DDRSS_PHY_309_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D8 0x00000030  //DDRSS_PHY_310_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4DC 0x01200048  //DDRSS_PHY_311_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E0 0x00000000  //DDRSS_PHY_312_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E4 0x0C000000  //DDRSS_PHY_313_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E8 0x07FF0000  //DDRSS_PHY_314_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4EC 0x00000000  //DDRSS_PHY_315_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F0 0x00000000  //DDRSS_PHY_316_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F4 0x00000000  //DDRSS_PHY_317_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F8 0x00000000  //DDRSS_PHY_318_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4FC 0x00000000  //DDRSS_PHY_319_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C500 0x00000000  //DDRSS_PHY_320_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C504 0x00000004  //DDRSS_PHY_321_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C508 0x00000000  //DDRSS_PHY_322_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C50C 0x00000000  //DDRSS_PHY_323_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C510 0x00000000  //DDRSS_PHY_324_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C514 0x00000000  //DDRSS_PHY_325_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C518 0x00000000  //DDRSS_PHY_326_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C51C 0x00000000  //DDRSS_PHY_327_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C520 0x041F07FF  //DDRSS_PHY_328_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C524 0x00000000  //DDRSS_PHY_329_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C528 0x01CCB001  //DDRSS_PHY_330_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C52C 0x2000CCB0  //DDRSS_PHY_331_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C530 0x20000140  //DDRSS_PHY_332_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C534 0x07FF0200  //DDRSS_PHY_333_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C538 0x0000DD01  //DDRSS_PHY_334_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C53C 0x10100303  //DDRSS_PHY_335_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C540 0x10101010  //DDRSS_PHY_336_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C544 0x10101010  //DDRSS_PHY_337_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C548 0x00021010  //DDRSS_PHY_338_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C54C 0x00100010  //DDRSS_PHY_339_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C550 0x00100010  //DDRSS_PHY_340_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C554 0x00100010  //DDRSS_PHY_341_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C558 0x00100010  //DDRSS_PHY_342_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C55C 0x02020010  //DDRSS_PHY_343_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C560 0x51515041  //DDRSS_PHY_344_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C564 0x31804000  //DDRSS_PHY_345_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C568 0x04BC0340  //DDRSS_PHY_346_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C56C 0x01008080  //DDRSS_PHY_347_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C570 0x04050001  //DDRSS_PHY_348_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C574 0x00000504  //DDRSS_PHY_349_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C578 0x42100010  //DDRSS_PHY_350_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C57C 0x010C053E  //DDRSS_PHY_351_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C580 0x000F0C14  //DDRSS_PHY_352_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C584 0x01000140  //DDRSS_PHY_353_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C588 0x007A0120  //DDRSS_PHY_354_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C58C 0x00000C00  //DDRSS_PHY_355_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C590 0x000001CC  //DDRSS_PHY_356_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C594 0x20100200  //DDRSS_PHY_357_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C598 0x00000005  //DDRSS_PHY_358_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C59C 0x76543210  //DDRSS_PHY_359_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A0 0x00000008  //DDRSS_PHY_360_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A4 0x02800280  //DDRSS_PHY_361_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A8 0x02800280  //DDRSS_PHY_362_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5AC 0x02800280  //DDRSS_PHY_363_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B0 0x02800280  //DDRSS_PHY_364_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B4 0x00420280  //DDRSS_PHY_365_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B8 0x0000B400  //DDRSS_PHY_366_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5BC 0x00A800B4  //DDRSS_PHY_367_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C0 0x00A800AE  //DDRSS_PHY_368_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C4 0x00B400AE  //DDRSS_PHY_369_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C8 0x00B400B4  //DDRSS_PHY_370_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5CC 0x00B400B4  //DDRSS_PHY_371_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D0 0x00B400AE  //DDRSS_PHY_372_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D4 0x00AE00B4  //DDRSS_PHY_373_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D8 0x00B400AE  //DDRSS_PHY_374_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5DC 0x019A00B4  //DDRSS_PHY_375_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E0 0x01000000  //DDRSS_PHY_376_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E4 0x00000000  //DDRSS_PHY_377_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E8 0x00000000  //DDRSS_PHY_378_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5EC 0x00080200  //DDRSS_PHY_379_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F0 0x00000000  //DDRSS_PHY_380_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F4 0x00000000  //DDRSS_PHY_381_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C800 0x00000100  //DDRSS_PHY_512_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C804 0x00001000  //DDRSS_PHY_513_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C808 0x00070000  //DDRSS_PHY_514_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C80C 0x00000000  //DDRSS_PHY_515_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C810 0x00000000  //DDRSS_PHY_516_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C814 0x00000100  //DDRSS_PHY_517_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C818 0x00000000  //DDRSS_PHY_518_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C81C 0x00000000  //DDRSS_PHY_519_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C820 0x00000000  //DDRSS_PHY_520_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C824 0x00000000  //DDRSS_PHY_521_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C828 0x00000000  //DDRSS_PHY_522_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C82C 0x00000000  //DDRSS_PHY_523_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C830 0x00000000  //DDRSS_PHY_524_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C834 0x00DCBA98  //DDRSS_PHY_525_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C838 0x00000000  //DDRSS_PHY_526_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C83C 0x00000000  //DDRSS_PHY_527_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C840 0x00000000  //DDRSS_PHY_528_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C844 0x00000000  //DDRSS_PHY_529_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C848 0x00000000  //DDRSS_PHY_530_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C84C 0x00000100  //DDRSS_PHY_531_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C850 0x00000000  //DDRSS_PHY_532_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C854 0x00000000  //DDRSS_PHY_533_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C858 0x00000000  //DDRSS_PHY_534_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C85C 0x00000000  //DDRSS_PHY_535_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C860 0x00000000  //DDRSS_PHY_536_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C864 0x00000000  //DDRSS_PHY_537_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C868 0x00000000  //DDRSS_PHY_538_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C86C 0x00000000  //DDRSS_PHY_539_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C870 0x0A418820  //DDRSS_PHY_540_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C874 0x103F0000  //DDRSS_PHY_541_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C878 0x000F0100  //DDRSS_PHY_542_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C87C 0x0000000F  //DDRSS_PHY_543_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C880 0x020002FF  //DDRSS_PHY_544_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C884 0x00030000  //DDRSS_PHY_545_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C888 0x00000300  //DDRSS_PHY_546_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C88C 0x00000300  //DDRSS_PHY_547_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C890 0x00000300  //DDRSS_PHY_548_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C894 0x00000300  //DDRSS_PHY_549_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C898 0x00000300  //DDRSS_PHY_550_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C89C 0x42080010  //DDRSS_PHY_551_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A0 0x0000003E  //DDRSS_PHY_552_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A4 0x00000000  //DDRSS_PHY_553_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A8 0x00000000  //DDRSS_PHY_554_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC00 0x00000100  //DDRSS_PHY_768_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC04 0x00001000  //DDRSS_PHY_769_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC08 0x00070000  //DDRSS_PHY_770_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC0C 0x00000000  //DDRSS_PHY_771_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC10 0x00000000  //DDRSS_PHY_772_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC14 0x00000100  //DDRSS_PHY_773_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC18 0x00000000  //DDRSS_PHY_774_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC1C 0x00000000  //DDRSS_PHY_775_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC20 0x00000000  //DDRSS_PHY_776_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC24 0x00000000  //DDRSS_PHY_777_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC28 0x00000000  //DDRSS_PHY_778_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC2C 0x00000000  //DDRSS_PHY_779_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC30 0x00000000  //DDRSS_PHY_780_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC34 0x00DCBA98  //DDRSS_PHY_781_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC38 0x00000000  //DDRSS_PHY_782_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC3C 0x00000000  //DDRSS_PHY_783_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC40 0x00000000  //DDRSS_PHY_784_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC44 0x00000000  //DDRSS_PHY_785_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC48 0x00000000  //DDRSS_PHY_786_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC4C 0x00000100  //DDRSS_PHY_787_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC50 0x00000000  //DDRSS_PHY_788_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC54 0x00000000  //DDRSS_PHY_789_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC58 0x00000000  //DDRSS_PHY_790_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC5C 0x00000000  //DDRSS_PHY_791_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC60 0x00000000  //DDRSS_PHY_792_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC64 0x00000000  //DDRSS_PHY_793_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC68 0x00000000  //DDRSS_PHY_794_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC6C 0x00000000  //DDRSS_PHY_795_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC70 0x16A4A0E6  //DDRSS_PHY_796_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC74 0x103F0000  //DDRSS_PHY_797_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC78 0x000F0000  //DDRSS_PHY_798_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC7C 0x0000000F  //DDRSS_PHY_799_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC80 0x020002FF  //DDRSS_PHY_800_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC84 0x00030000  //DDRSS_PHY_801_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC88 0x00000300  //DDRSS_PHY_802_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC8C 0x00000300  //DDRSS_PHY_803_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC90 0x00000300  //DDRSS_PHY_804_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC94 0x00000300  //DDRSS_PHY_805_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC98 0x00000300  //DDRSS_PHY_806_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC9C 0x42080010  //DDRSS_PHY_807_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA0 0x0000003E  //DDRSS_PHY_808_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA4 0x00000000  //DDRSS_PHY_809_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA8 0x00000000  //DDRSS_PHY_810_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D000 0x00000100  //DDRSS_PHY_1024_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D004 0x00001000  //DDRSS_PHY_1025_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D008 0x00070000  //DDRSS_PHY_1026_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D00C 0x00000000  //DDRSS_PHY_1027_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D010 0x00000000  //DDRSS_PHY_1028_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D014 0x00000100  //DDRSS_PHY_1029_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D018 0x00000000  //DDRSS_PHY_1030_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D01C 0x00000000  //DDRSS_PHY_1031_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D020 0x00000000  //DDRSS_PHY_1032_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D024 0x00000000  //DDRSS_PHY_1033_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D028 0x00000000  //DDRSS_PHY_1034_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D02C 0x00000000  //DDRSS_PHY_1035_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D030 0x00000000  //DDRSS_PHY_1036_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D034 0x00DCBA98  //DDRSS_PHY_1037_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D038 0x00000000  //DDRSS_PHY_1038_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D03C 0x00000000  //DDRSS_PHY_1039_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D040 0x00000000  //DDRSS_PHY_1040_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D044 0x00000000  //DDRSS_PHY_1041_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D048 0x00000000  //DDRSS_PHY_1042_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D04C 0x00000100  //DDRSS_PHY_1043_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D050 0x00000000  //DDRSS_PHY_1044_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D054 0x00000000  //DDRSS_PHY_1045_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D058 0x00000000  //DDRSS_PHY_1046_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D05C 0x00000000  //DDRSS_PHY_1047_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D060 0x00000000  //DDRSS_PHY_1048_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D064 0x00000000  //DDRSS_PHY_1049_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D068 0x00000000  //DDRSS_PHY_1050_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D06C 0x00000000  //DDRSS_PHY_1051_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D070 0x2307B9AC  //DDRSS_PHY_1052_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D074 0x10030000  //DDRSS_PHY_1053_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D078 0x000F0000  //DDRSS_PHY_1054_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D07C 0x0000000F  //DDRSS_PHY_1055_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D080 0x020002FF  //DDRSS_PHY_1056_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D084 0x00030000  //DDRSS_PHY_1057_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D088 0x00000300  //DDRSS_PHY_1058_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D08C 0x00000300  //DDRSS_PHY_1059_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D090 0x00000300  //DDRSS_PHY_1060_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D094 0x00000300  //DDRSS_PHY_1061_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D098 0x00000300  //DDRSS_PHY_1062_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D09C 0x42080010  //DDRSS_PHY_1063_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A0 0x0000003E  //DDRSS_PHY_1064_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A4 0x00000000  //DDRSS_PHY_1065_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A8 0x00000000  //DDRSS_PHY_1066_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D400 0x00000000  //DDRSS_PHY_1280_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D404 0x00000000  //DDRSS_PHY_1281_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D408 0x00000000  //DDRSS_PHY_1282_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D40C 0x00000000  //DDRSS_PHY_1283_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D410 0x00000000  //DDRSS_PHY_1284_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D414 0x00000000  //DDRSS_PHY_1285_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D418 0x00050000  //DDRSS_PHY_1286_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D41C 0x04000100  //DDRSS_PHY_1287_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D420 0x00000055  //DDRSS_PHY_1288_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D424 0x00000000  //DDRSS_PHY_1289_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D428 0x06800000  //DDRSS_PHY_1290_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D42C 0x00000000  //DDRSS_PHY_1291_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D430 0x00000000  //DDRSS_PHY_1292_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D434 0x01002000  //DDRSS_PHY_1293_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D438 0x00004001  //DDRSS_PHY_1294_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D43C 0x00020028  //DDRSS_PHY_1295_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D440 0x00010100  //DDRSS_PHY_1296_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D444 0x00000001  //DDRSS_PHY_1297_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D448 0x00000000  //DDRSS_PHY_1298_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D44C 0x0F0F0E06  //DDRSS_PHY_1299_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D450 0x00010101  //DDRSS_PHY_1300_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D454 0x010F0004  //DDRSS_PHY_1301_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D458 0x00000000  //DDRSS_PHY_1302_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D45C 0x20125770  //DDRSS_PHY_1303_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D460 0x00000064  //DDRSS_PHY_1304_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D464 0x00000000  //DDRSS_PHY_1305_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D468 0x00000000  //DDRSS_PHY_1306_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D46C 0x01020103  //DDRSS_PHY_1307_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D470 0x03020102  //DDRSS_PHY_1308_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D474 0x03030303  //DDRSS_PHY_1309_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D478 0x03030303  //DDRSS_PHY_1310_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D47C 0x00040000  //DDRSS_PHY_1311_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D480 0x00005201  //DDRSS_PHY_1312_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D484 0x00000003  //DDRSS_PHY_1313_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D488 0x00010000  //DDRSS_PHY_1314_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D48C 0x00000000  //DDRSS_PHY_1315_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D490 0x00000003  //DDRSS_PHY_1316_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D494 0x00010000  //DDRSS_PHY_1317_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D498 0x00000000  //DDRSS_PHY_1318_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D49C 0x07070001  //DDRSS_PHY_1319_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A0 0x00005400  //DDRSS_PHY_1320_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A4 0x000040A2  //DDRSS_PHY_1321_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A8 0x00034890  //DDRSS_PHY_1322_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4AC 0x00014890  //DDRSS_PHY_1323_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B0 0x00014890  //DDRSS_PHY_1324_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B4 0x00014890  //DDRSS_PHY_1325_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B8 0x0001488F  //DDRSS_PHY_1326_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4BC 0x00014890  //DDRSS_PHY_1327_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C0 0x0001491E  //DDRSS_PHY_1328_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C4 0x0001491E  //DDRSS_PHY_1329_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C8 0x00014890  //DDRSS_PHY_1330_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4CC 0x00014890  //DDRSS_PHY_1331_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D0 0x00000000  //DDRSS_PHY_1332_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D4 0x00000046  //DDRSS_PHY_1333_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D8 0x00000400  //DDRSS_PHY_1334_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4DC 0x00000008  //DDRSS_PHY_1335_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E0 0x00814890  //DDRSS_PHY_1336_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E4 0x0081491E  //DDRSS_PHY_1337_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E8 0x00148900  //DDRSS_PHY_1338_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4EC 0x001491E8  //DDRSS_PHY_1339_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F0 0x00F4890F  //DDRSS_PHY_1340_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F4 0x03F491EF  //DDRSS_PHY_1341_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F8 0x00000000  //DDRSS_PHY_1342_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4FC 0x00000000  //DDRSS_PHY_1343_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D500 0xB3000000  //DDRSS_PHY_1344_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D504 0x04102006  //DDRSS_PHY_1345_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D508 0x00041020  //DDRSS_PHY_1346_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D50C 0x01C98C98  //DDRSS_PHY_1347_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D510 0x3F400000  //DDRSS_PHY_1348_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D514 0x3F3F1F3F  //DDRSS_PHY_1349_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D518 0x0000001F  //DDRSS_PHY_1350_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D51C 0x00000000  //DDRSS_PHY_1351_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D520 0x00000000  //DDRSS_PHY_1352_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D524 0x00000000  //DDRSS_PHY_1353_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D528 0x00000001  //DDRSS_PHY_1354_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D52C 0x00000000  //DDRSS_PHY_1355_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D530 0x00000000  //DDRSS_PHY_1356_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D534 0x00000000  //DDRSS_PHY_1357_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D538 0x00000000  //DDRSS_PHY_1358_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D53C 0x76543210  //DDRSS_PHY_1359_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D540 0x00000098  //DDRSS_PHY_1360_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D544 0x00000000  //DDRSS_PHY_1361_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D548 0x00000000  //DDRSS_PHY_1362_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D54C 0x00000000  //DDRSS_PHY_1363_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D550 0x00040700  //DDRSS_PHY_1364_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D554 0x00000000  //DDRSS_PHY_1365_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D558 0x00000000  //DDRSS_PHY_1366_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D55C 0x00000000  //DDRSS_PHY_1367_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D560 0x030F7102  //DDRSS_PHY_1368_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D564 0x00000100  //DDRSS_PHY_1369_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D568 0x00000000  //DDRSS_PHY_1370_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D56C 0x0001F7C2  //DDRSS_PHY_1371_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D570 0x00020002  //DDRSS_PHY_1372_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D574 0x00000000  //DDRSS_PHY_1373_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D578 0x00001142  //DDRSS_PHY_1374_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D57C 0x03020400  //DDRSS_PHY_1375_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D580 0x00000080  //DDRSS_PHY_1376_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D584 0x03900390  //DDRSS_PHY_1377_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D588 0x03900390  //DDRSS_PHY_1378_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D58C 0x03900390  //DDRSS_PHY_1379_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D590 0x03900390  //DDRSS_PHY_1380_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D594 0x03900390  //DDRSS_PHY_1381_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D598 0x03900390  //DDRSS_PHY_1382_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D59C 0x00000300  //DDRSS_PHY_1383_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A0 0x00000300  //DDRSS_PHY_1384_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A4 0x00000300  //DDRSS_PHY_1385_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A8 0x00000300  //DDRSS_PHY_1386_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5AC 0x31823FF7  //DDRSS_PHY_1387_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B0 0x00000000  //DDRSS_PHY_1388_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B4 0x0C000D3F  //DDRSS_PHY_1389_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B8 0x30000D3F  //DDRSS_PHY_1390_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5BC 0x300D3F11  //DDRSS_PHY_1391_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C0 0x01FF0000  //DDRSS_PHY_1392_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C4 0x000D3FFF  //DDRSS_PHY_1393_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C8 0x00000C11  //DDRSS_PHY_1394_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5CC 0x300D3F11  //DDRSS_PHY_1395_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D0 0x01FF0000  //DDRSS_PHY_1396_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D4 0x300C3F11  //DDRSS_PHY_1397_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D8 0x01FF0000  //DDRSS_PHY_1398_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5DC 0x300C3F11  //DDRSS_PHY_1399_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E0 0x01FF0000  //DDRSS_PHY_1400_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E4 0x300D3F11  //DDRSS_PHY_1401_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E8 0x01FF0000  //DDRSS_PHY_1402_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5EC 0x300D3F11  //DDRSS_PHY_1403_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F0 0x01FF0000  //DDRSS_PHY_1404_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F4 0x20040004  //DDRSS_PHY_1405_DATA_F0

The log shows with 2T read the readback data mismatching happens less frequently:

Date: 2024-09-29
File: DDR4-1600_800MHz_CL14_CWL11_RPRCD1375_XPR5_board_ddrReginit_preamble: cntr 331: 0x01000001
Delay: NO
start addr: 0x80000000

Fail DDR addr 0x8002219C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8002F27C failed Write value: 0x0000000F, read value: 0x00FF000F

Fail DDR addr 0x800311DC failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x80034AFC failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8005F0DC failed Write value: 0x00000007, read value: 0x00FF0007

Fail DDR addr 0x8007CC9C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x80084CFC failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x800949FC failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x800A05BC failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x800B623C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x800D509C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x800DF11C failed Write value: 0x00000003, read value: 0x00FF0003

Fail DDR addr 0x800E213C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x800FC2BC failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8010541C failed Write value: 0x00000003, read value: 0x00FF0003

Fail DDR addr 0x801074BC failed Write value: 0x00000003, read value: 0x00FF0003

Fail DDR addr 0x8010E19C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8011AF3C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8012FA9C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8013503C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8015841C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x801586DC failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8015967C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8015F5FC failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8016B2BC failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8018873C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8019D1FC failed Write value: 0xFFFFFFEA, read value: 0xFF00FFEA

Fail DDR addr 0x801C709C failed Write value: 0x00000003, read value: 0x00FF0003

Fail DDR addr 0x801FBABC failed Write value: 0x0000000F, read value: 0x00FF000F

Fail DDR addr 0x801FF0DC failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x802100BC failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8021FD1C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8021FF9C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8022829C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8024609C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8024663C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8024911C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x802492FC failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x802544BC failed Write value: 0x00000007, read value: 0x00FF0007

Fail DDR addr 0x8027B73C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x8028FDFC failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x80291FBC failed Write value: 0x00000003, read value: 0x00FF0003

Fail DDR addr 0x802965DC failed Write value: 0xFFFFFF55, read value: 0xFF00FF55

Fail DDR addr 0x802B311C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x802C517C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x802C8A7C failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x802C92DC failed Write value: 0x00000001, read value: 0x00FF0001

Fail DDR addr 0x802E913C failed Write value: 0x00000001, read value: 0x00FF0001

Would you pls let me know what we can do next? thanks.

Regards,

Larry

Larry, it seems the training isn't quite completing.

Can you please try with the attached configuration.  Please send the register dump as you did before.

/cfs-file/__key/communityserver-discussions-components-files/908/board_5F00_ddrReginit.h

Regards,

James

Hi James,

Thanks for the suggestion. It's our holiday week until Oct 7.  I'll post the register dump once back to office.

Regards,

Larry 

ok, ill be OOO beginning of next week, but can help on Wednesday.

Regards,

James

Hi James,

The downloaded configuration H file is "board_ddrReginit.h",  i.e. the name is different from that in the link you posted,"board_5F00_ddrReginit.h". 

I post the configuration file here to make sure it is as you expected:

/* Copyright (c) 2022, Texas Instruments Incorporated
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
#define DDR_TYPE DDR4

#ifndef BOARD_DDRREGINIT_H_
#define BOARD_DDRREGINIT_H_

#ifdef __cplusplus
extern "C" {
#endif

/*
 * This file was generated with the
 * AM243x_ALV SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02 
 * Mon Sep 30 2024 18:09:56 GMT-0500 (Central Daylight Time)
 * DDR Type: DDR4
 * Frequency = 800MHz (1600MTs)
 * Density: 4Gb
 * Number of Ranks: 1
*/

#define DDRSS_PLL_FHS_CNT 6
#define DDRSS_PLL_FREQUENCY_1 400000000
#define DDRSS_PLL_FREQUENCY_2 400000000
#define DDRSS_SDRAM_IDX 13
#define DDRSS_REGION_IDX 15

#define DDRSS_CTL_REG_INIT_COUNT (423U)
#define DDRSS_PHY_INDEP_REG_INIT_COUNT (345U)
#define DDRSS_PHY_REG_INIT_COUNT (507U)

uint32_t DDRSS_ctlReg[] = {
    0x00000A00U, // DDRSS_CTL_0_VAL
    0x00000000U, // DDRSS_CTL_1_VAL
    0x00000000U, // DDRSS_CTL_2_VAL
    0x00000000U, // DDRSS_CTL_3_VAL
    0x00000000U, // DDRSS_CTL_4_VAL
    0x00000000U, // DDRSS_CTL_5_VAL
    0x00000000U, // DDRSS_CTL_6_VAL
    0x00089070U, // DDRSS_CTL_7_VAL
    0x00000000U, // DDRSS_CTL_8_VAL
    0x00000000U, // DDRSS_CTL_9_VAL
    0x00000000U, // DDRSS_CTL_10_VAL
    0x00089070U, // DDRSS_CTL_11_VAL
    0x00000000U, // DDRSS_CTL_12_VAL
    0x00000000U, // DDRSS_CTL_13_VAL
    0x00000000U, // DDRSS_CTL_14_VAL
    0x00089070U, // DDRSS_CTL_15_VAL
    0x00000000U, // DDRSS_CTL_16_VAL
    0x00000000U, // DDRSS_CTL_17_VAL
    0x00000000U, // DDRSS_CTL_18_VAL
    0x01010100U, // DDRSS_CTL_19_VAL
    0x01000100U, // DDRSS_CTL_20_VAL
    0x01000110U, // DDRSS_CTL_21_VAL
    0x02010002U, // DDRSS_CTL_22_VAL
    0x00027100U, // DDRSS_CTL_23_VAL
    0x00061A80U, // DDRSS_CTL_24_VAL
    0x02550255U, // DDRSS_CTL_25_VAL
    0x00000255U, // DDRSS_CTL_26_VAL
    0x00000000U, // DDRSS_CTL_27_VAL
    0x00000000U, // DDRSS_CTL_28_VAL
    0x00000000U, // DDRSS_CTL_29_VAL
    0x00000000U, // DDRSS_CTL_30_VAL
    0x00000000U, // DDRSS_CTL_31_VAL
    0x00000000U, // DDRSS_CTL_32_VAL
    0x00000000U, // DDRSS_CTL_33_VAL
    0x00000000U, // DDRSS_CTL_34_VAL
    0x00000000U, // DDRSS_CTL_35_VAL
    0x00000000U, // DDRSS_CTL_36_VAL
    0x00000000U, // DDRSS_CTL_37_VAL
    0x0400091CU, // DDRSS_CTL_38_VAL
    0x1C1C1C1CU, // DDRSS_CTL_39_VAL
    0x0400091CU, // DDRSS_CTL_40_VAL
    0x1C1C1C1CU, // DDRSS_CTL_41_VAL
    0x0400091CU, // DDRSS_CTL_42_VAL
    0x1C1C1C1CU, // DDRSS_CTL_43_VAL
    0x05050404U, // DDRSS_CTL_44_VAL
    0x00002606U, // DDRSS_CTL_45_VAL
    0x0602001BU, // DDRSS_CTL_46_VAL
    0x05001D0CU, // DDRSS_CTL_47_VAL
    0x00260605U, // DDRSS_CTL_48_VAL
    0x0602001BU, // DDRSS_CTL_49_VAL
    0x05001D0CU, // DDRSS_CTL_50_VAL
    0x00260605U, // DDRSS_CTL_51_VAL
    0x0602001BU, // DDRSS_CTL_52_VAL
    0x07001D0CU, // DDRSS_CTL_53_VAL
    0x00180807U, // DDRSS_CTL_54_VAL
    0x0400DB60U, // DDRSS_CTL_55_VAL
    0x07070009U, // DDRSS_CTL_56_VAL
    0x00001808U, // DDRSS_CTL_57_VAL
    0x0400DB60U, // DDRSS_CTL_58_VAL
    0x07070009U, // DDRSS_CTL_59_VAL
    0x00001808U, // DDRSS_CTL_60_VAL
    0x0400DB60U, // DDRSS_CTL_61_VAL
    0x03000009U, // DDRSS_CTL_62_VAL
    0x0D0D0002U, // DDRSS_CTL_63_VAL
    0x0D0D0D0DU, // DDRSS_CTL_64_VAL
    0x01010000U, // DDRSS_CTL_65_VAL
    0x031A1A1AU, // DDRSS_CTL_66_VAL
    0x0C0C0C0CU, // DDRSS_CTL_67_VAL
    0x00000C0CU, // DDRSS_CTL_68_VAL
    0x00000101U, // DDRSS_CTL_69_VAL
    0x00000000U, // DDRSS_CTL_70_VAL
    0x01000000U, // DDRSS_CTL_71_VAL
    0x00D00803U, // DDRSS_CTL_72_VAL
    0x00001860U, // DDRSS_CTL_73_VAL
    0x000000D0U, // DDRSS_CTL_74_VAL
    0x00001860U, // DDRSS_CTL_75_VAL
    0x000000D0U, // DDRSS_CTL_76_VAL
    0x00001860U, // DDRSS_CTL_77_VAL
    0x00000005U, // DDRSS_CTL_78_VAL
    0x00000000U, // DDRSS_CTL_79_VAL
    0x00000000U, // DDRSS_CTL_80_VAL
    0x00000000U, // DDRSS_CTL_81_VAL
    0x00000000U, // DDRSS_CTL_82_VAL
    0x00000000U, // DDRSS_CTL_83_VAL
    0x00000000U, // DDRSS_CTL_84_VAL
    0x00000000U, // DDRSS_CTL_85_VAL
    0x00000000U, // DDRSS_CTL_86_VAL
    0x00090009U, // DDRSS_CTL_87_VAL
    0x00000009U, // DDRSS_CTL_88_VAL
    0x00000000U, // DDRSS_CTL_89_VAL
    0x00000000U, // DDRSS_CTL_90_VAL
    0x00000000U, // DDRSS_CTL_91_VAL
    0x00000000U, // DDRSS_CTL_92_VAL
    0x00000000U, // DDRSS_CTL_93_VAL
    0x00010001U, // DDRSS_CTL_94_VAL
    0x00025501U, // DDRSS_CTL_95_VAL
    0x025500D8U, // DDRSS_CTL_96_VAL
    0x025500D8U, // DDRSS_CTL_97_VAL
    0x00D800D8U, // DDRSS_CTL_98_VAL
    0x00D800D8U, // DDRSS_CTL_99_VAL
    0x00000000U, // DDRSS_CTL_100_VAL
    0x00000000U, // DDRSS_CTL_101_VAL
    0x00000000U, // DDRSS_CTL_102_VAL
    0x00000000U, // DDRSS_CTL_103_VAL
    0x00000000U, // DDRSS_CTL_104_VAL
    0x00000000U, // DDRSS_CTL_105_VAL
    0x03010000U, // DDRSS_CTL_106_VAL
    0x00010000U, // DDRSS_CTL_107_VAL
    0x00000000U, // DDRSS_CTL_108_VAL
    0x01000000U, // DDRSS_CTL_109_VAL
    0x80104002U, // DDRSS_CTL_110_VAL
    0x00040003U, // DDRSS_CTL_111_VAL
    0x00040005U, // DDRSS_CTL_112_VAL
    0x00030000U, // DDRSS_CTL_113_VAL
    0x00050004U, // DDRSS_CTL_114_VAL
    0x00000004U, // DDRSS_CTL_115_VAL
    0x00040003U, // DDRSS_CTL_116_VAL
    0x00040005U, // DDRSS_CTL_117_VAL
    0x00000000U, // DDRSS_CTL_118_VAL
    0x00061800U, // DDRSS_CTL_119_VAL
    0x00061800U, // DDRSS_CTL_120_VAL
    0x00061800U, // DDRSS_CTL_121_VAL
    0x00061800U, // DDRSS_CTL_122_VAL
    0x00061800U, // DDRSS_CTL_123_VAL
    0x00000000U, // DDRSS_CTL_124_VAL
    0x0000AAA0U, // DDRSS_CTL_125_VAL
    0x00061800U, // DDRSS_CTL_126_VAL
    0x00061800U, // DDRSS_CTL_127_VAL
    0x00061800U, // DDRSS_CTL_128_VAL
    0x00061800U, // DDRSS_CTL_129_VAL
    0x00061800U, // DDRSS_CTL_130_VAL
    0x00000000U, // DDRSS_CTL_131_VAL
    0x0000AAA0U, // DDRSS_CTL_132_VAL
    0x00061800U, // DDRSS_CTL_133_VAL
    0x00061800U, // DDRSS_CTL_134_VAL
    0x00061800U, // DDRSS_CTL_135_VAL
    0x00061800U, // DDRSS_CTL_136_VAL
    0x00061800U, // DDRSS_CTL_137_VAL
    0x00000000U, // DDRSS_CTL_138_VAL
    0x0000AAA0U, // DDRSS_CTL_139_VAL
    0x00000000U, // DDRSS_CTL_140_VAL
    0x00000000U, // DDRSS_CTL_141_VAL
    0x00000000U, // DDRSS_CTL_142_VAL
    0x00000000U, // DDRSS_CTL_143_VAL
    0x00000000U, // DDRSS_CTL_144_VAL
    0x00000000U, // DDRSS_CTL_145_VAL
    0x00000000U, // DDRSS_CTL_146_VAL
    0x00000000U, // DDRSS_CTL_147_VAL
    0x00000000U, // DDRSS_CTL_148_VAL
    0x00000000U, // DDRSS_CTL_149_VAL
    0x00000000U, // DDRSS_CTL_150_VAL
    0x00000000U, // DDRSS_CTL_151_VAL
    0x00000000U, // DDRSS_CTL_152_VAL
    0x00000000U, // DDRSS_CTL_153_VAL
    0x00000000U, // DDRSS_CTL_154_VAL
    0x00000000U, // DDRSS_CTL_155_VAL
    0x080C0000U, // DDRSS_CTL_156_VAL
    0x080C080CU, // DDRSS_CTL_157_VAL
    0x00000000U, // DDRSS_CTL_158_VAL
    0x07010A09U, // DDRSS_CTL_159_VAL
    0x000E0A09U, // DDRSS_CTL_160_VAL
    0x010A0900U, // DDRSS_CTL_161_VAL
    0x0E0A0907U, // DDRSS_CTL_162_VAL
    0x0A090000U, // DDRSS_CTL_163_VAL
    0x0A090701U, // DDRSS_CTL_164_VAL
    0x0000080EU, // DDRSS_CTL_165_VAL
    0x00040003U, // DDRSS_CTL_166_VAL
    0x00000007U, // DDRSS_CTL_167_VAL
    0x00000000U, // DDRSS_CTL_168_VAL
    0x00000000U, // DDRSS_CTL_169_VAL
    0x00000000U, // DDRSS_CTL_170_VAL
    0x00000000U, // DDRSS_CTL_171_VAL
    0x00000000U, // DDRSS_CTL_172_VAL
    0x00000000U, // DDRSS_CTL_173_VAL
    0x01000000U, // DDRSS_CTL_174_VAL
    0x00000000U, // DDRSS_CTL_175_VAL
    0x00001500U, // DDRSS_CTL_176_VAL
    0x0000100EU, // DDRSS_CTL_177_VAL
    0x00000000U, // DDRSS_CTL_178_VAL
    0x00000000U, // DDRSS_CTL_179_VAL
    0x00000001U, // DDRSS_CTL_180_VAL
    0x00000002U, // DDRSS_CTL_181_VAL
    0x00000C00U, // DDRSS_CTL_182_VAL
    0x00001000U, // DDRSS_CTL_183_VAL
    0x00000C00U, // DDRSS_CTL_184_VAL
    0x00001000U, // DDRSS_CTL_185_VAL
    0x00000C00U, // DDRSS_CTL_186_VAL
    0x00001000U, // DDRSS_CTL_187_VAL
    0x00000000U, // DDRSS_CTL_188_VAL
    0x00000000U, // DDRSS_CTL_189_VAL
    0x00000000U, // DDRSS_CTL_190_VAL
    0x00000000U, // DDRSS_CTL_191_VAL
    0x00000000U, // DDRSS_CTL_192_VAL
    0x00000000U, // DDRSS_CTL_193_VAL
    0x00000000U, // DDRSS_CTL_194_VAL
    0x00000000U, // DDRSS_CTL_195_VAL
    0x00000000U, // DDRSS_CTL_196_VAL
    0x00000000U, // DDRSS_CTL_197_VAL
    0x00000000U, // DDRSS_CTL_198_VAL
    0x00000000U, // DDRSS_CTL_199_VAL
    0x00000000U, // DDRSS_CTL_200_VAL
    0x00000000U, // DDRSS_CTL_201_VAL
    0x00000000U, // DDRSS_CTL_202_VAL
    0x00000000U, // DDRSS_CTL_203_VAL
    0x00042400U, // DDRSS_CTL_204_VAL
    0x00000301U, // DDRSS_CTL_205_VAL
    0x00000000U, // DDRSS_CTL_206_VAL
    0x00000424U, // DDRSS_CTL_207_VAL
    0x00000301U, // DDRSS_CTL_208_VAL
    0x00000000U, // DDRSS_CTL_209_VAL
    0x00000424U, // DDRSS_CTL_210_VAL
    0x00000301U, // DDRSS_CTL_211_VAL
    0x00000000U, // DDRSS_CTL_212_VAL
    0x00000424U, // DDRSS_CTL_213_VAL
    0x00000301U, // DDRSS_CTL_214_VAL
    0x00000000U, // DDRSS_CTL_215_VAL
    0x00000424U, // DDRSS_CTL_216_VAL
    0x00000301U, // DDRSS_CTL_217_VAL
    0x00000000U, // DDRSS_CTL_218_VAL
    0x00000424U, // DDRSS_CTL_219_VAL
    0x00000301U, // DDRSS_CTL_220_VAL
    0x00000000U, // DDRSS_CTL_221_VAL
    0x00000000U, // DDRSS_CTL_222_VAL
    0x00000000U, // DDRSS_CTL_223_VAL
    0x00000000U, // DDRSS_CTL_224_VAL
    0x00000000U, // DDRSS_CTL_225_VAL
    0x00000000U, // DDRSS_CTL_226_VAL
    0x00000000U, // DDRSS_CTL_227_VAL
    0x00000000U, // DDRSS_CTL_228_VAL
    0x00000000U, // DDRSS_CTL_229_VAL
    0x00000000U, // DDRSS_CTL_230_VAL
    0x00000000U, // DDRSS_CTL_231_VAL
    0x00000000U, // DDRSS_CTL_232_VAL
    0x00000000U, // DDRSS_CTL_233_VAL
    0x00000000U, // DDRSS_CTL_234_VAL
    0x00000000U, // DDRSS_CTL_235_VAL
    0x00001401U, // DDRSS_CTL_236_VAL
    0x00001401U, // DDRSS_CTL_237_VAL
    0x00001401U, // DDRSS_CTL_238_VAL
    0x00001401U, // DDRSS_CTL_239_VAL
    0x00001401U, // DDRSS_CTL_240_VAL
    0x00001401U, // DDRSS_CTL_241_VAL
    0x00000493U, // DDRSS_CTL_242_VAL
    0x00000493U, // DDRSS_CTL_243_VAL
    0x00000493U, // DDRSS_CTL_244_VAL
    0x00000493U, // DDRSS_CTL_245_VAL
    0x00000493U, // DDRSS_CTL_246_VAL
    0x00000493U, // DDRSS_CTL_247_VAL
    0x00000000U, // DDRSS_CTL_248_VAL
    0x00000000U, // DDRSS_CTL_249_VAL
    0x00000000U, // DDRSS_CTL_250_VAL
    0x00000000U, // DDRSS_CTL_251_VAL
    0x00000000U, // DDRSS_CTL_252_VAL
    0x00000000U, // DDRSS_CTL_253_VAL
    0x00000000U, // DDRSS_CTL_254_VAL
    0x00000000U, // DDRSS_CTL_255_VAL
    0x00000000U, // DDRSS_CTL_256_VAL
    0x00000000U, // DDRSS_CTL_257_VAL
    0x00000000U, // DDRSS_CTL_258_VAL
    0x00000000U, // DDRSS_CTL_259_VAL
    0x00000000U, // DDRSS_CTL_260_VAL
    0x00000000U, // DDRSS_CTL_261_VAL
    0x00000000U, // DDRSS_CTL_262_VAL
    0x00000000U, // DDRSS_CTL_263_VAL
    0x00000000U, // DDRSS_CTL_264_VAL
    0x00000000U, // DDRSS_CTL_265_VAL
    0x00000000U, // DDRSS_CTL_266_VAL
    0x00000000U, // DDRSS_CTL_267_VAL
    0x00000000U, // DDRSS_CTL_268_VAL
    0x00000000U, // DDRSS_CTL_269_VAL
    0x00000000U, // DDRSS_CTL_270_VAL
    0x00000000U, // DDRSS_CTL_271_VAL
    0x00000000U, // DDRSS_CTL_272_VAL
    0x00000000U, // DDRSS_CTL_273_VAL
    0x00000000U, // DDRSS_CTL_274_VAL
    0x00000000U, // DDRSS_CTL_275_VAL
    0x00000000U, // DDRSS_CTL_276_VAL
    0x00010000U, // DDRSS_CTL_277_VAL
    0x00000000U, // DDRSS_CTL_278_VAL
    0x00000000U, // DDRSS_CTL_279_VAL
    0x00000000U, // DDRSS_CTL_280_VAL
    0x00000101U, // DDRSS_CTL_281_VAL
    0x00000000U, // DDRSS_CTL_282_VAL
    0x00000000U, // DDRSS_CTL_283_VAL
    0x00000000U, // DDRSS_CTL_284_VAL
    0x00000000U, // DDRSS_CTL_285_VAL
    0x00000000U, // DDRSS_CTL_286_VAL
    0x00000000U, // DDRSS_CTL_287_VAL
    0x00000000U, // DDRSS_CTL_288_VAL
    0x00000000U, // DDRSS_CTL_289_VAL
    0x0C181511U, // DDRSS_CTL_290_VAL
    0x00000304U, // DDRSS_CTL_291_VAL
    0x00000000U, // DDRSS_CTL_292_VAL
    0x00000000U, // DDRSS_CTL_293_VAL
    0x00000000U, // DDRSS_CTL_294_VAL
    0x00000000U, // DDRSS_CTL_295_VAL
    0x00000000U, // DDRSS_CTL_296_VAL
    0x00000000U, // DDRSS_CTL_297_VAL
    0x00000000U, // DDRSS_CTL_298_VAL
    0x00000000U, // DDRSS_CTL_299_VAL
    0x00000000U, // DDRSS_CTL_300_VAL
    0x00000000U, // DDRSS_CTL_301_VAL
    0x00000000U, // DDRSS_CTL_302_VAL
    0x00000000U, // DDRSS_CTL_303_VAL
    0x00000000U, // DDRSS_CTL_304_VAL
    0x00040000U, // DDRSS_CTL_305_VAL
    0x00800200U, // DDRSS_CTL_306_VAL
    0x00000000U, // DDRSS_CTL_307_VAL
    0x02000400U, // DDRSS_CTL_308_VAL
    0x00000080U, // DDRSS_CTL_309_VAL
    0x00040000U, // DDRSS_CTL_310_VAL
    0x00800200U, // DDRSS_CTL_311_VAL
    0x00000000U, // DDRSS_CTL_312_VAL
    0x00000000U, // DDRSS_CTL_313_VAL
    0x00000000U, // DDRSS_CTL_314_VAL
    0x00000100U, // DDRSS_CTL_315_VAL
    0x01010000U, // DDRSS_CTL_316_VAL
    0x00000202U, // DDRSS_CTL_317_VAL
    0x0FFF0000U, // DDRSS_CTL_318_VAL
    0x000FFF00U, // DDRSS_CTL_319_VAL
    0xFFFFFFFFU, // DDRSS_CTL_320_VAL
    0x00FFFF00U, // DDRSS_CTL_321_VAL
    0x0A000000U, // DDRSS_CTL_322_VAL
    0x0001FFFFU, // DDRSS_CTL_323_VAL
    0x01010101U, // DDRSS_CTL_324_VAL
    0x01010101U, // DDRSS_CTL_325_VAL
    0x00000118U, // DDRSS_CTL_326_VAL
    0x00000C01U, // DDRSS_CTL_327_VAL
    0x00000000U, // DDRSS_CTL_328_VAL
    0x00000000U, // DDRSS_CTL_329_VAL
    0x00000000U, // DDRSS_CTL_330_VAL
    0x01000000U, // DDRSS_CTL_331_VAL
    0x00000100U, // DDRSS_CTL_332_VAL
    0x00010000U, // DDRSS_CTL_333_VAL
    0x00000000U, // DDRSS_CTL_334_VAL
    0x00000000U, // DDRSS_CTL_335_VAL
    0x00000000U, // DDRSS_CTL_336_VAL
    0x00000000U, // DDRSS_CTL_337_VAL
    0x00000000U, // DDRSS_CTL_338_VAL
    0x00000000U, // DDRSS_CTL_339_VAL
    0x00000000U, // DDRSS_CTL_340_VAL
    0x00000000U, // DDRSS_CTL_341_VAL
    0x00000000U, // DDRSS_CTL_342_VAL
    0x00000000U, // DDRSS_CTL_343_VAL
    0x00000000U, // DDRSS_CTL_344_VAL
    0x00000000U, // DDRSS_CTL_345_VAL
    0x00000000U, // DDRSS_CTL_346_VAL
    0x00000000U, // DDRSS_CTL_347_VAL
    0x00000000U, // DDRSS_CTL_348_VAL
    0x00000000U, // DDRSS_CTL_349_VAL
    0x00000000U, // DDRSS_CTL_350_VAL
    0x00000000U, // DDRSS_CTL_351_VAL
    0x00000000U, // DDRSS_CTL_352_VAL
    0x00000000U, // DDRSS_CTL_353_VAL
    0x00000000U, // DDRSS_CTL_354_VAL
    0x00000000U, // DDRSS_CTL_355_VAL
    0x00000000U, // DDRSS_CTL_356_VAL
    0x00000000U, // DDRSS_CTL_357_VAL
    0x00000000U, // DDRSS_CTL_358_VAL
    0x00000000U, // DDRSS_CTL_359_VAL
    0x00000000U, // DDRSS_CTL_360_VAL
    0x00000000U, // DDRSS_CTL_361_VAL
    0x00000000U, // DDRSS_CTL_362_VAL
    0x00000000U, // DDRSS_CTL_363_VAL
    0x00000000U, // DDRSS_CTL_364_VAL
    0x00000000U, // DDRSS_CTL_365_VAL
    0x00000000U, // DDRSS_CTL_366_VAL
    0x00000000U, // DDRSS_CTL_367_VAL
    0x00000000U, // DDRSS_CTL_368_VAL
    0x00000000U, // DDRSS_CTL_369_VAL
    0x0C000000U, // DDRSS_CTL_370_VAL
    0x060C0606U, // DDRSS_CTL_371_VAL
    0x06060C06U, // DDRSS_CTL_372_VAL
    0x00010101U, // DDRSS_CTL_373_VAL
    0x02000000U, // DDRSS_CTL_374_VAL
    0x05020101U, // DDRSS_CTL_375_VAL
    0x00000505U, // DDRSS_CTL_376_VAL
    0x02020200U, // DDRSS_CTL_377_VAL
    0x02020202U, // DDRSS_CTL_378_VAL
    0x02020202U, // DDRSS_CTL_379_VAL
    0x02020202U, // DDRSS_CTL_380_VAL
    0x00000000U, // DDRSS_CTL_381_VAL
    0x00000000U, // DDRSS_CTL_382_VAL
    0x04000100U, // DDRSS_CTL_383_VAL
    0x1E000004U, // DDRSS_CTL_384_VAL
    0x000030C0U, // DDRSS_CTL_385_VAL
    0x00000200U, // DDRSS_CTL_386_VAL
    0x00000200U, // DDRSS_CTL_387_VAL
    0x00000200U, // DDRSS_CTL_388_VAL
    0x00000200U, // DDRSS_CTL_389_VAL
    0x0000DB60U, // DDRSS_CTL_390_VAL
    0x0001E780U, // DDRSS_CTL_391_VAL
    0x0C0D0302U, // DDRSS_CTL_392_VAL
    0x001E090AU, // DDRSS_CTL_393_VAL
    0x000030C0U, // DDRSS_CTL_394_VAL
    0x00000200U, // DDRSS_CTL_395_VAL
    0x00000200U, // DDRSS_CTL_396_VAL
    0x00000200U, // DDRSS_CTL_397_VAL
    0x00000200U, // DDRSS_CTL_398_VAL
    0x0000DB60U, // DDRSS_CTL_399_VAL
    0x0001E780U, // DDRSS_CTL_400_VAL
    0x0C0D0302U, // DDRSS_CTL_401_VAL
    0x001E090AU, // DDRSS_CTL_402_VAL
    0x000030C0U, // DDRSS_CTL_403_VAL
    0x00000200U, // DDRSS_CTL_404_VAL
    0x00000200U, // DDRSS_CTL_405_VAL
    0x00000200U, // DDRSS_CTL_406_VAL
    0x00000200U, // DDRSS_CTL_407_VAL
    0x0000DB60U, // DDRSS_CTL_408_VAL
    0x0001E780U, // DDRSS_CTL_409_VAL
    0x0C0D0302U, // DDRSS_CTL_410_VAL
    0x0000090AU, // DDRSS_CTL_411_VAL
    0x00000000U, // DDRSS_CTL_412_VAL
    0x0302000AU, // DDRSS_CTL_413_VAL
    0x01000500U, // DDRSS_CTL_414_VAL
    0x01010001U, // DDRSS_CTL_415_VAL
    0x00010001U, // DDRSS_CTL_416_VAL
    0x01010001U, // DDRSS_CTL_417_VAL
    0x02010000U, // DDRSS_CTL_418_VAL
    0x00000200U, // DDRSS_CTL_419_VAL
    0x02000201U, // DDRSS_CTL_420_VAL
    0x00000000U, // DDRSS_CTL_421_VAL
    0x00202020U, // DDRSS_CTL_422_VAL
};

uint32_t DDRSS_phyIndepReg[] = {
    0x00000A00U, // DDRSS_PI_0_VAL
    0x00000000U, // DDRSS_PI_1_VAL
    0x00000000U, // DDRSS_PI_2_VAL
    0x01000000U, // DDRSS_PI_3_VAL
    0x00000001U, // DDRSS_PI_4_VAL
    0x00010064U, // DDRSS_PI_5_VAL
    0x00000000U, // DDRSS_PI_6_VAL
    0x00000000U, // DDRSS_PI_7_VAL
    0x00000000U, // DDRSS_PI_8_VAL
    0x00000000U, // DDRSS_PI_9_VAL
    0x00000000U, // DDRSS_PI_10_VAL
    0x00000000U, // DDRSS_PI_11_VAL
    0x00000000U, // DDRSS_PI_12_VAL
    0x00010001U, // DDRSS_PI_13_VAL
    0x00000000U, // DDRSS_PI_14_VAL
    0x00010001U, // DDRSS_PI_15_VAL
    0x00000005U, // DDRSS_PI_16_VAL
    0x00000000U, // DDRSS_PI_17_VAL
    0x00000000U, // DDRSS_PI_18_VAL
    0x00000000U, // DDRSS_PI_19_VAL
    0x00000000U, // DDRSS_PI_20_VAL
    0x00000000U, // DDRSS_PI_21_VAL
    0x00000000U, // DDRSS_PI_22_VAL
    0x00000000U, // DDRSS_PI_23_VAL
    0x280D0001U, // DDRSS_PI_24_VAL
    0x00000000U, // DDRSS_PI_25_VAL
    0x00010000U, // DDRSS_PI_26_VAL
    0x00003200U, // DDRSS_PI_27_VAL
    0x00000000U, // DDRSS_PI_28_VAL
    0x00000000U, // DDRSS_PI_29_VAL
    0x00060602U, // DDRSS_PI_30_VAL
    0x00000000U, // DDRSS_PI_31_VAL
    0x00000000U, // DDRSS_PI_32_VAL
    0x00000000U, // DDRSS_PI_33_VAL
    0x00000001U, // DDRSS_PI_34_VAL
    0x00000055U, // DDRSS_PI_35_VAL
    0x000000AAU, // DDRSS_PI_36_VAL
    0x000000ADU, // DDRSS_PI_37_VAL
    0x00000052U, // DDRSS_PI_38_VAL
    0x0000006AU, // DDRSS_PI_39_VAL
    0x00000095U, // DDRSS_PI_40_VAL
    0x00000095U, // DDRSS_PI_41_VAL
    0x000000ADU, // DDRSS_PI_42_VAL
    0x00000000U, // DDRSS_PI_43_VAL
    0x00000000U, // DDRSS_PI_44_VAL
    0x00010100U, // DDRSS_PI_45_VAL
    0x00000014U, // DDRSS_PI_46_VAL
    0x000007D0U, // DDRSS_PI_47_VAL
    0x00000300U, // DDRSS_PI_48_VAL
    0x00000000U, // DDRSS_PI_49_VAL
    0x00000000U, // DDRSS_PI_50_VAL
    0x01000000U, // DDRSS_PI_51_VAL
    0x00010101U, // DDRSS_PI_52_VAL
    0x01000000U, // DDRSS_PI_53_VAL
    0x00000000U, // DDRSS_PI_54_VAL
    0x00010000U, // DDRSS_PI_55_VAL
    0x00000000U, // DDRSS_PI_56_VAL
    0x00000000U, // DDRSS_PI_57_VAL
    0x00000000U, // DDRSS_PI_58_VAL
    0x00000000U, // DDRSS_PI_59_VAL
    0x00001400U, // DDRSS_PI_60_VAL
    0x00000000U, // DDRSS_PI_61_VAL
    0x01000000U, // DDRSS_PI_62_VAL
    0x00000404U, // DDRSS_PI_63_VAL
    0x00000001U, // DDRSS_PI_64_VAL
    0x0001010EU, // DDRSS_PI_65_VAL
    0x02040100U, // DDRSS_PI_66_VAL
    0x00010000U, // DDRSS_PI_67_VAL
    0x00000034U, // DDRSS_PI_68_VAL
    0x00000000U, // DDRSS_PI_69_VAL
    0x00000000U, // DDRSS_PI_70_VAL
    0x00000000U, // DDRSS_PI_71_VAL
    0x00000000U, // DDRSS_PI_72_VAL
    0x00000000U, // DDRSS_PI_73_VAL
    0x00000000U, // DDRSS_PI_74_VAL
    0x00000005U, // DDRSS_PI_75_VAL
    0x01000000U, // DDRSS_PI_76_VAL
    0x04020100U, // DDRSS_PI_77_VAL
    0x00020000U, // DDRSS_PI_78_VAL
    0x00010002U, // DDRSS_PI_79_VAL
    0x00000001U, // DDRSS_PI_80_VAL
    0x00020001U, // DDRSS_PI_81_VAL
    0x00020002U, // DDRSS_PI_82_VAL
    0x00000000U, // DDRSS_PI_83_VAL
    0x00000000U, // DDRSS_PI_84_VAL
    0x00000000U, // DDRSS_PI_85_VAL
    0x00000000U, // DDRSS_PI_86_VAL
    0x00000000U, // DDRSS_PI_87_VAL
    0x00000000U, // DDRSS_PI_88_VAL
    0x00000000U, // DDRSS_PI_89_VAL
    0x00000000U, // DDRSS_PI_90_VAL
    0x00000300U, // DDRSS_PI_91_VAL
    0x0A090B0CU, // DDRSS_PI_92_VAL
    0x04060708U, // DDRSS_PI_93_VAL
    0x01000005U, // DDRSS_PI_94_VAL
    0x00000800U, // DDRSS_PI_95_VAL
    0x00000000U, // DDRSS_PI_96_VAL
    0x00010008U, // DDRSS_PI_97_VAL
    0x00000000U, // DDRSS_PI_98_VAL
    0x0000AA00U, // DDRSS_PI_99_VAL
    0x00000000U, // DDRSS_PI_100_VAL
    0x00010000U, // DDRSS_PI_101_VAL
    0x00000000U, // DDRSS_PI_102_VAL
    0x00000000U, // DDRSS_PI_103_VAL
    0x00000000U, // DDRSS_PI_104_VAL
    0x00000000U, // DDRSS_PI_105_VAL
    0x00000000U, // DDRSS_PI_106_VAL
    0x00000000U, // DDRSS_PI_107_VAL
    0x00000000U, // DDRSS_PI_108_VAL
    0x00000000U, // DDRSS_PI_109_VAL
    0x00000000U, // DDRSS_PI_110_VAL
    0x00000000U, // DDRSS_PI_111_VAL
    0x00000000U, // DDRSS_PI_112_VAL
    0x00000000U, // DDRSS_PI_113_VAL
    0x00000000U, // DDRSS_PI_114_VAL
    0x00000000U, // DDRSS_PI_115_VAL
    0x00000000U, // DDRSS_PI_116_VAL
    0x00000000U, // DDRSS_PI_117_VAL
    0x00000000U, // DDRSS_PI_118_VAL
    0x00000000U, // DDRSS_PI_119_VAL
    0x00000000U, // DDRSS_PI_120_VAL
    0x00000000U, // DDRSS_PI_121_VAL
    0x00000000U, // DDRSS_PI_122_VAL
    0x00000000U, // DDRSS_PI_123_VAL
    0x00000008U, // DDRSS_PI_124_VAL
    0x00000000U, // DDRSS_PI_125_VAL
    0x00000000U, // DDRSS_PI_126_VAL
    0x00000000U, // DDRSS_PI_127_VAL
    0x00000000U, // DDRSS_PI_128_VAL
    0x00000000U, // DDRSS_PI_129_VAL
    0x00000000U, // DDRSS_PI_130_VAL
    0x00000000U, // DDRSS_PI_131_VAL
    0x00000000U, // DDRSS_PI_132_VAL
    0x00010100U, // DDRSS_PI_133_VAL
    0x00000000U, // DDRSS_PI_134_VAL
    0x00000000U, // DDRSS_PI_135_VAL
    0x00027100U, // DDRSS_PI_136_VAL
    0x00061A80U, // DDRSS_PI_137_VAL
    0x00000100U, // DDRSS_PI_138_VAL
    0x00000000U, // DDRSS_PI_139_VAL
    0x00000000U, // DDRSS_PI_140_VAL
    0x00000000U, // DDRSS_PI_141_VAL
    0x00000000U, // DDRSS_PI_142_VAL
    0x00000000U, // DDRSS_PI_143_VAL
    0x01000000U, // DDRSS_PI_144_VAL
    0x00010003U, // DDRSS_PI_145_VAL
    0x02000101U, // DDRSS_PI_146_VAL
    0x01030001U, // DDRSS_PI_147_VAL
    0x00010400U, // DDRSS_PI_148_VAL
    0x06000105U, // DDRSS_PI_149_VAL
    0x01070001U, // DDRSS_PI_150_VAL
    0x00000000U, // DDRSS_PI_151_VAL
    0x00000000U, // DDRSS_PI_152_VAL
    0x00000000U, // DDRSS_PI_153_VAL
    0x00010000U, // DDRSS_PI_154_VAL
    0x00000000U, // DDRSS_PI_155_VAL
    0x00000000U, // DDRSS_PI_156_VAL
    0x00000000U, // DDRSS_PI_157_VAL
    0x00000000U, // DDRSS_PI_158_VAL
    0x00010000U, // DDRSS_PI_159_VAL
    0x00000004U, // DDRSS_PI_160_VAL
    0x00000000U, // DDRSS_PI_161_VAL
    0x00000000U, // DDRSS_PI_162_VAL
    0x00000000U, // DDRSS_PI_163_VAL
    0x00007800U, // DDRSS_PI_164_VAL
    0x00780078U, // DDRSS_PI_165_VAL
    0x00141414U, // DDRSS_PI_166_VAL
    0x0000003AU, // DDRSS_PI_167_VAL
    0x0000003AU, // DDRSS_PI_168_VAL
    0x0004003AU, // DDRSS_PI_169_VAL
    0x04000400U, // DDRSS_PI_170_VAL
    0xC8040009U, // DDRSS_PI_171_VAL
    0x0400091CU, // DDRSS_PI_172_VAL
    0x00091CC8U, // DDRSS_PI_173_VAL
    0x001CC804U, // DDRSS_PI_174_VAL
    0x000000D0U, // DDRSS_PI_175_VAL
    0x00001860U, // DDRSS_PI_176_VAL
    0x000000D0U, // DDRSS_PI_177_VAL
    0x00001860U, // DDRSS_PI_178_VAL
    0x000000D0U, // DDRSS_PI_179_VAL
    0x04001860U, // DDRSS_PI_180_VAL
    0x01010404U, // DDRSS_PI_181_VAL
    0x00001901U, // DDRSS_PI_182_VAL
    0x00190019U, // DDRSS_PI_183_VAL
    0x010C010CU, // DDRSS_PI_184_VAL
    0x0000010CU, // DDRSS_PI_185_VAL
    0x00000000U, // DDRSS_PI_186_VAL
    0x05000000U, // DDRSS_PI_187_VAL
    0x01010505U, // DDRSS_PI_188_VAL
    0x01010101U, // DDRSS_PI_189_VAL
    0x00181818U, // DDRSS_PI_190_VAL
    0x00000000U, // DDRSS_PI_191_VAL
    0x00000000U, // DDRSS_PI_192_VAL
    0x0D000000U, // DDRSS_PI_193_VAL
    0x0A0A0D0DU, // DDRSS_PI_194_VAL
    0x0303030AU, // DDRSS_PI_195_VAL
    0x00000000U, // DDRSS_PI_196_VAL
    0x00000000U, // DDRSS_PI_197_VAL
    0x00000000U, // DDRSS_PI_198_VAL
    0x00000000U, // DDRSS_PI_199_VAL
    0x00000000U, // DDRSS_PI_200_VAL
    0x00000000U, // DDRSS_PI_201_VAL
    0x00000000U, // DDRSS_PI_202_VAL
    0x00000000U, // DDRSS_PI_203_VAL
    0x00000000U, // DDRSS_PI_204_VAL
    0x00000000U, // DDRSS_PI_205_VAL
    0x00000000U, // DDRSS_PI_206_VAL
    0x00000000U, // DDRSS_PI_207_VAL
    0x00000000U, // DDRSS_PI_208_VAL
    0x0D090000U, // DDRSS_PI_209_VAL
    0x0D09000DU, // DDRSS_PI_210_VAL
    0x0D09000DU, // DDRSS_PI_211_VAL
    0x0000000DU, // DDRSS_PI_212_VAL
    0x00000000U, // DDRSS_PI_213_VAL
    0x00000000U, // DDRSS_PI_214_VAL
    0x00000000U, // DDRSS_PI_215_VAL
    0x00000000U, // DDRSS_PI_216_VAL
    0x16000000U, // DDRSS_PI_217_VAL
    0x001600C8U, // DDRSS_PI_218_VAL
    0x001600C8U, // DDRSS_PI_219_VAL
    0x010100C8U, // DDRSS_PI_220_VAL
    0x00001B01U, // DDRSS_PI_221_VAL
    0x1F0F0053U, // DDRSS_PI_222_VAL
    0x05000001U, // DDRSS_PI_223_VAL
    0x001B0A0DU, // DDRSS_PI_224_VAL
    0x1F0F0053U, // DDRSS_PI_225_VAL
    0x05000001U, // DDRSS_PI_226_VAL
    0x001B0A0DU, // DDRSS_PI_227_VAL
    0x1F0F0053U, // DDRSS_PI_228_VAL
    0x05000001U, // DDRSS_PI_229_VAL
    0x00010A0DU, // DDRSS_PI_230_VAL
    0x0D0C0700U, // DDRSS_PI_231_VAL
    0x000D0605U, // DDRSS_PI_232_VAL
    0x0000C570U, // DDRSS_PI_233_VAL
    0x0000001BU, // DDRSS_PI_234_VAL
    0x180A0800U, // DDRSS_PI_235_VAL
    0x0C071C1CU, // DDRSS_PI_236_VAL
    0x0D06050DU, // DDRSS_PI_237_VAL
    0x0000C570U, // DDRSS_PI_238_VAL
    0x0000001BU, // DDRSS_PI_239_VAL
    0x180A0800U, // DDRSS_PI_240_VAL
    0x0C071C1CU, // DDRSS_PI_241_VAL
    0x0D06050DU, // DDRSS_PI_242_VAL
    0x0000C570U, // DDRSS_PI_243_VAL
    0x0000001BU, // DDRSS_PI_244_VAL
    0x180A0800U, // DDRSS_PI_245_VAL
    0x00001C1CU, // DDRSS_PI_246_VAL
    0x000030C0U, // DDRSS_PI_247_VAL
    0x0001E780U, // DDRSS_PI_248_VAL
    0x000030C0U, // DDRSS_PI_249_VAL
    0x0001E780U, // DDRSS_PI_250_VAL
    0x000030C0U, // DDRSS_PI_251_VAL
    0x0001E780U, // DDRSS_PI_252_VAL
    0x02550255U, // DDRSS_PI_253_VAL
    0x03030255U, // DDRSS_PI_254_VAL
    0x00025503U, // DDRSS_PI_255_VAL
    0x02550255U, // DDRSS_PI_256_VAL
    0x0C080C08U, // DDRSS_PI_257_VAL
    0x00000C08U, // DDRSS_PI_258_VAL
    0x00089070U, // DDRSS_PI_259_VAL
    0x00000000U, // DDRSS_PI_260_VAL
    0x00000000U, // DDRSS_PI_261_VAL
    0x00000000U, // DDRSS_PI_262_VAL
    0x000000D8U, // DDRSS_PI_263_VAL
    0x00089070U, // DDRSS_PI_264_VAL
    0x00000000U, // DDRSS_PI_265_VAL
    0x00000000U, // DDRSS_PI_266_VAL
    0x00000000U, // DDRSS_PI_267_VAL
    0x000000D8U, // DDRSS_PI_268_VAL
    0x00089070U, // DDRSS_PI_269_VAL
    0x00000000U, // DDRSS_PI_270_VAL
    0x00000000U, // DDRSS_PI_271_VAL
    0x00000000U, // DDRSS_PI_272_VAL
    0x020000D8U, // DDRSS_PI_273_VAL
    0x00000080U, // DDRSS_PI_274_VAL
    0x00020000U, // DDRSS_PI_275_VAL
    0x00000080U, // DDRSS_PI_276_VAL
    0x00020000U, // DDRSS_PI_277_VAL
    0x00000080U, // DDRSS_PI_278_VAL
    0x00000000U, // DDRSS_PI_279_VAL
    0x00000000U, // DDRSS_PI_280_VAL
    0x00040404U, // DDRSS_PI_281_VAL
    0x00000000U, // DDRSS_PI_282_VAL
    0x02010102U, // DDRSS_PI_283_VAL
    0x67676767U, // DDRSS_PI_284_VAL
    0x00000202U, // DDRSS_PI_285_VAL
    0x00000000U, // DDRSS_PI_286_VAL
    0x00000000U, // DDRSS_PI_287_VAL
    0x00000000U, // DDRSS_PI_288_VAL
    0x00000000U, // DDRSS_PI_289_VAL
    0x00000000U, // DDRSS_PI_290_VAL
    0x0D100F00U, // DDRSS_PI_291_VAL
    0x0003020EU, // DDRSS_PI_292_VAL
    0x00000001U, // DDRSS_PI_293_VAL
    0x01000000U, // DDRSS_PI_294_VAL
    0x00020201U, // DDRSS_PI_295_VAL
    0x00000000U, // DDRSS_PI_296_VAL
    0x00000424U, // DDRSS_PI_297_VAL
    0x00000301U, // DDRSS_PI_298_VAL
    0x00000000U, // DDRSS_PI_299_VAL
    0x00000000U, // DDRSS_PI_300_VAL
    0x00000000U, // DDRSS_PI_301_VAL
    0x00001401U, // DDRSS_PI_302_VAL
    0x00000493U, // DDRSS_PI_303_VAL
    0x00000000U, // DDRSS_PI_304_VAL
    0x00000424U, // DDRSS_PI_305_VAL
    0x00000301U, // DDRSS_PI_306_VAL
    0x00000000U, // DDRSS_PI_307_VAL
    0x00000000U, // DDRSS_PI_308_VAL
    0x00000000U, // DDRSS_PI_309_VAL
    0x00001401U, // DDRSS_PI_310_VAL
    0x00000493U, // DDRSS_PI_311_VAL
    0x00000000U, // DDRSS_PI_312_VAL
    0x00000424U, // DDRSS_PI_313_VAL
    0x00000301U, // DDRSS_PI_314_VAL
    0x00000000U, // DDRSS_PI_315_VAL
    0x00000000U, // DDRSS_PI_316_VAL
    0x00000000U, // DDRSS_PI_317_VAL
    0x00001401U, // DDRSS_PI_318_VAL
    0x00000493U, // DDRSS_PI_319_VAL
    0x00000000U, // DDRSS_PI_320_VAL
    0x00000424U, // DDRSS_PI_321_VAL
    0x00000301U, // DDRSS_PI_322_VAL
    0x00000000U, // DDRSS_PI_323_VAL
    0x00000000U, // DDRSS_PI_324_VAL
    0x00000000U, // DDRSS_PI_325_VAL
    0x00001401U, // DDRSS_PI_326_VAL
    0x00000493U, // DDRSS_PI_327_VAL
    0x00000000U, // DDRSS_PI_328_VAL
    0x00000424U, // DDRSS_PI_329_VAL
    0x00000301U, // DDRSS_PI_330_VAL
    0x00000000U, // DDRSS_PI_331_VAL
    0x00000000U, // DDRSS_PI_332_VAL
    0x00000000U, // DDRSS_PI_333_VAL
    0x00001401U, // DDRSS_PI_334_VAL
    0x00000493U, // DDRSS_PI_335_VAL
    0x00000000U, // DDRSS_PI_336_VAL
    0x00000424U, // DDRSS_PI_337_VAL
    0x00000301U, // DDRSS_PI_338_VAL
    0x00000000U, // DDRSS_PI_339_VAL
    0x00000000U, // DDRSS_PI_340_VAL
    0x00000000U, // DDRSS_PI_341_VAL
    0x00001401U, // DDRSS_PI_342_VAL
    0x00000493U, // DDRSS_PI_343_VAL
    0x00000000U, // DDRSS_PI_344_VAL
};

uint32_t DDRSS_phyReg[] = {
    0x04C00000U, // DDRSS_PHY_0_VAL
    0x00000000U, // DDRSS_PHY_1_VAL
    0x00000200U, // DDRSS_PHY_2_VAL
    0x00000000U, // DDRSS_PHY_3_VAL
    0x00000000U, // DDRSS_PHY_4_VAL
    0x00000000U, // DDRSS_PHY_5_VAL
    0x00000000U, // DDRSS_PHY_6_VAL
    0x00000000U, // DDRSS_PHY_7_VAL
    0x00000001U, // DDRSS_PHY_8_VAL
    0x00000000U, // DDRSS_PHY_9_VAL
    0x00000000U, // DDRSS_PHY_10_VAL
    0x010101FFU, // DDRSS_PHY_11_VAL
    0x00010000U, // DDRSS_PHY_12_VAL
    0x00C00004U, // DDRSS_PHY_13_VAL
    0x00CC0008U, // DDRSS_PHY_14_VAL
    0x00660201U, // DDRSS_PHY_15_VAL
    0x00000000U, // DDRSS_PHY_16_VAL
    0x00000000U, // DDRSS_PHY_17_VAL
    0x00000000U, // DDRSS_PHY_18_VAL
    0x0000AAAAU, // DDRSS_PHY_19_VAL
    0x00005555U, // DDRSS_PHY_20_VAL
    0x0000B5B5U, // DDRSS_PHY_21_VAL
    0x00004A4AU, // DDRSS_PHY_22_VAL
    0x00005656U, // DDRSS_PHY_23_VAL
    0x0000A9A9U, // DDRSS_PHY_24_VAL
    0x0000B7B7U, // DDRSS_PHY_25_VAL
    0x00004848U, // DDRSS_PHY_26_VAL
    0x00000000U, // DDRSS_PHY_27_VAL
    0x00000000U, // DDRSS_PHY_28_VAL
    0x08000000U, // DDRSS_PHY_29_VAL
    0x0F000008U, // DDRSS_PHY_30_VAL
    0x00000F0FU, // DDRSS_PHY_31_VAL
    0x00E4E400U, // DDRSS_PHY_32_VAL
    0x00070820U, // DDRSS_PHY_33_VAL
    0x000C0020U, // DDRSS_PHY_34_VAL
    0x00062000U, // DDRSS_PHY_35_VAL
    0x00000000U, // DDRSS_PHY_36_VAL
    0x55555555U, // DDRSS_PHY_37_VAL
    0xAAAAAAAAU, // DDRSS_PHY_38_VAL
    0x55555555U, // DDRSS_PHY_39_VAL
    0xAAAAAAAAU, // DDRSS_PHY_40_VAL
    0x00005555U, // DDRSS_PHY_41_VAL
    0x01000100U, // DDRSS_PHY_42_VAL
    0x00800180U, // DDRSS_PHY_43_VAL
    0x00000000U, // DDRSS_PHY_44_VAL
    0x00000000U, // DDRSS_PHY_45_VAL
    0x00000000U, // DDRSS_PHY_46_VAL
    0x00000000U, // DDRSS_PHY_47_VAL
    0x00000000U, // DDRSS_PHY_48_VAL
    0x00000000U, // DDRSS_PHY_49_VAL
    0x00000000U, // DDRSS_PHY_50_VAL
    0x00000000U, // DDRSS_PHY_51_VAL
    0x00000000U, // DDRSS_PHY_52_VAL
    0x00000000U, // DDRSS_PHY_53_VAL
    0x00000000U, // DDRSS_PHY_54_VAL
    0x00000000U, // DDRSS_PHY_55_VAL
    0x00000000U, // DDRSS_PHY_56_VAL
    0x00000000U, // DDRSS_PHY_57_VAL
    0x00000000U, // DDRSS_PHY_58_VAL
    0x00000000U, // DDRSS_PHY_59_VAL
    0x00000000U, // DDRSS_PHY_60_VAL
    0x00000000U, // DDRSS_PHY_61_VAL
    0x00000000U, // DDRSS_PHY_62_VAL
    0x00000000U, // DDRSS_PHY_63_VAL
    0x00000000U, // DDRSS_PHY_64_VAL
    0x00000004U, // DDRSS_PHY_65_VAL
    0x00000000U, // DDRSS_PHY_66_VAL
    0x00000000U, // DDRSS_PHY_67_VAL
    0x00000000U, // DDRSS_PHY_68_VAL
    0x00000000U, // DDRSS_PHY_69_VAL
    0x00000000U, // DDRSS_PHY_70_VAL
    0x00000000U, // DDRSS_PHY_71_VAL
    0x041F07FFU, // DDRSS_PHY_72_VAL
    0x00000000U, // DDRSS_PHY_73_VAL
    0x01CCB001U, // DDRSS_PHY_74_VAL
    0x2000CCB0U, // DDRSS_PHY_75_VAL
    0x20000140U, // DDRSS_PHY_76_VAL
    0x07FF0200U, // DDRSS_PHY_77_VAL
    0x0000DD01U, // DDRSS_PHY_78_VAL
    0x10100303U, // DDRSS_PHY_79_VAL
    0x10101010U, // DDRSS_PHY_80_VAL
    0x10101010U, // DDRSS_PHY_81_VAL
    0x00021010U, // DDRSS_PHY_82_VAL
    0x00100010U, // DDRSS_PHY_83_VAL
    0x00100010U, // DDRSS_PHY_84_VAL
    0x00100010U, // DDRSS_PHY_85_VAL
    0x00100010U, // DDRSS_PHY_86_VAL
    0x02020010U, // DDRSS_PHY_87_VAL
    0x51515041U, // DDRSS_PHY_88_VAL
    0x31804000U, // DDRSS_PHY_89_VAL
    0x04BF0340U, // DDRSS_PHY_90_VAL
    0x01008080U, // DDRSS_PHY_91_VAL
    0x04050001U, // DDRSS_PHY_92_VAL
    0x00000504U, // DDRSS_PHY_93_VAL
    0x42100010U, // DDRSS_PHY_94_VAL
    0x010C053EU, // DDRSS_PHY_95_VAL
    0x000F0C14U, // DDRSS_PHY_96_VAL
    0x01000140U, // DDRSS_PHY_97_VAL
    0x007A0120U, // DDRSS_PHY_98_VAL
    0x00000C00U, // DDRSS_PHY_99_VAL
    0x000001CCU, // DDRSS_PHY_100_VAL
    0x20100200U, // DDRSS_PHY_101_VAL
    0x00000005U, // DDRSS_PHY_102_VAL
    0x76543210U, // DDRSS_PHY_103_VAL
    0x00000008U, // DDRSS_PHY_104_VAL
    0x02800280U, // DDRSS_PHY_105_VAL
    0x02800280U, // DDRSS_PHY_106_VAL
    0x02800280U, // DDRSS_PHY_107_VAL
    0x02800280U, // DDRSS_PHY_108_VAL
    0x00000280U, // DDRSS_PHY_109_VAL
    0x00008000U, // DDRSS_PHY_110_VAL
    0x00800080U, // DDRSS_PHY_111_VAL
    0x00800080U, // DDRSS_PHY_112_VAL
    0x00800080U, // DDRSS_PHY_113_VAL
    0x00800080U, // DDRSS_PHY_114_VAL
    0x00800080U, // DDRSS_PHY_115_VAL
    0x00800080U, // DDRSS_PHY_116_VAL
    0x00800080U, // DDRSS_PHY_117_VAL
    0x00800080U, // DDRSS_PHY_118_VAL
    0x01000080U, // DDRSS_PHY_119_VAL
    0x01000000U, // DDRSS_PHY_120_VAL
    0x00000000U, // DDRSS_PHY_121_VAL
    0x00000000U, // DDRSS_PHY_122_VAL
    0x00080200U, // DDRSS_PHY_123_VAL
    0x00000000U, // DDRSS_PHY_124_VAL
    0x00000000U, // DDRSS_PHY_125_VAL
    0x04C00000U, // DDRSS_PHY_256_VAL
    0x00000000U, // DDRSS_PHY_257_VAL
    0x00000200U, // DDRSS_PHY_258_VAL
    0x00000000U, // DDRSS_PHY_259_VAL
    0x00000000U, // DDRSS_PHY_260_VAL
    0x00000000U, // DDRSS_PHY_261_VAL
    0x00000000U, // DDRSS_PHY_262_VAL
    0x00000000U, // DDRSS_PHY_263_VAL
    0x00000001U, // DDRSS_PHY_264_VAL
    0x00000000U, // DDRSS_PHY_265_VAL
    0x00000000U, // DDRSS_PHY_266_VAL
    0x010101FFU, // DDRSS_PHY_267_VAL
    0x00010000U, // DDRSS_PHY_268_VAL
    0x00C00004U, // DDRSS_PHY_269_VAL
    0x00CC0008U, // DDRSS_PHY_270_VAL
    0x00660201U, // DDRSS_PHY_271_VAL
    0x00000000U, // DDRSS_PHY_272_VAL
    0x00000000U, // DDRSS_PHY_273_VAL
    0x00000000U, // DDRSS_PHY_274_VAL
    0x0000AAAAU, // DDRSS_PHY_275_VAL
    0x00005555U, // DDRSS_PHY_276_VAL
    0x0000B5B5U, // DDRSS_PHY_277_VAL
    0x00004A4AU, // DDRSS_PHY_278_VAL
    0x00005656U, // DDRSS_PHY_279_VAL
    0x0000A9A9U, // DDRSS_PHY_280_VAL
    0x0000B7B7U, // DDRSS_PHY_281_VAL
    0x00004848U, // DDRSS_PHY_282_VAL
    0x00000000U, // DDRSS_PHY_283_VAL
    0x00000000U, // DDRSS_PHY_284_VAL
    0x08000000U, // DDRSS_PHY_285_VAL
    0x0F000008U, // DDRSS_PHY_286_VAL
    0x00000F0FU, // DDRSS_PHY_287_VAL
    0x00E4E400U, // DDRSS_PHY_288_VAL
    0x00070820U, // DDRSS_PHY_289_VAL
    0x000C0020U, // DDRSS_PHY_290_VAL
    0x00062000U, // DDRSS_PHY_291_VAL
    0x00000000U, // DDRSS_PHY_292_VAL
    0x55555555U, // DDRSS_PHY_293_VAL
    0xAAAAAAAAU, // DDRSS_PHY_294_VAL
    0x55555555U, // DDRSS_PHY_295_VAL
    0xAAAAAAAAU, // DDRSS_PHY_296_VAL
    0x00005555U, // DDRSS_PHY_297_VAL
    0x01000100U, // DDRSS_PHY_298_VAL
    0x00800180U, // DDRSS_PHY_299_VAL
    0x00000000U, // DDRSS_PHY_300_VAL
    0x00000000U, // DDRSS_PHY_301_VAL
    0x00000000U, // DDRSS_PHY_302_VAL
    0x00000000U, // DDRSS_PHY_303_VAL
    0x00000000U, // DDRSS_PHY_304_VAL
    0x00000000U, // DDRSS_PHY_305_VAL
    0x00000000U, // DDRSS_PHY_306_VAL
    0x00000000U, // DDRSS_PHY_307_VAL
    0x00000000U, // DDRSS_PHY_308_VAL
    0x00000000U, // DDRSS_PHY_309_VAL
    0x00000000U, // DDRSS_PHY_310_VAL
    0x00000000U, // DDRSS_PHY_311_VAL
    0x00000000U, // DDRSS_PHY_312_VAL
    0x00000000U, // DDRSS_PHY_313_VAL
    0x00000000U, // DDRSS_PHY_314_VAL
    0x00000000U, // DDRSS_PHY_315_VAL
    0x00000000U, // DDRSS_PHY_316_VAL
    0x00000000U, // DDRSS_PHY_317_VAL
    0x00000000U, // DDRSS_PHY_318_VAL
    0x00000000U, // DDRSS_PHY_319_VAL
    0x00000000U, // DDRSS_PHY_320_VAL
    0x00000004U, // DDRSS_PHY_321_VAL
    0x00000000U, // DDRSS_PHY_322_VAL
    0x00000000U, // DDRSS_PHY_323_VAL
    0x00000000U, // DDRSS_PHY_324_VAL
    0x00000000U, // DDRSS_PHY_325_VAL
    0x00000000U, // DDRSS_PHY_326_VAL
    0x00000000U, // DDRSS_PHY_327_VAL
    0x041F07FFU, // DDRSS_PHY_328_VAL
    0x00000000U, // DDRSS_PHY_329_VAL
    0x01CCB001U, // DDRSS_PHY_330_VAL
    0x2000CCB0U, // DDRSS_PHY_331_VAL
    0x20000140U, // DDRSS_PHY_332_VAL
    0x07FF0200U, // DDRSS_PHY_333_VAL
    0x0000DD01U, // DDRSS_PHY_334_VAL
    0x10100303U, // DDRSS_PHY_335_VAL
    0x10101010U, // DDRSS_PHY_336_VAL
    0x10101010U, // DDRSS_PHY_337_VAL
    0x00021010U, // DDRSS_PHY_338_VAL
    0x00100010U, // DDRSS_PHY_339_VAL
    0x00100010U, // DDRSS_PHY_340_VAL
    0x00100010U, // DDRSS_PHY_341_VAL
    0x00100010U, // DDRSS_PHY_342_VAL
    0x02020010U, // DDRSS_PHY_343_VAL
    0x51515041U, // DDRSS_PHY_344_VAL
    0x31804000U, // DDRSS_PHY_345_VAL
    0x04BF0340U, // DDRSS_PHY_346_VAL
    0x01008080U, // DDRSS_PHY_347_VAL
    0x04050001U, // DDRSS_PHY_348_VAL
    0x00000504U, // DDRSS_PHY_349_VAL
    0x42100010U, // DDRSS_PHY_350_VAL
    0x010C053EU, // DDRSS_PHY_351_VAL
    0x000F0C14U, // DDRSS_PHY_352_VAL
    0x01000140U, // DDRSS_PHY_353_VAL
    0x007A0120U, // DDRSS_PHY_354_VAL
    0x00000C00U, // DDRSS_PHY_355_VAL
    0x000001CCU, // DDRSS_PHY_356_VAL
    0x20100200U, // DDRSS_PHY_357_VAL
    0x00000005U, // DDRSS_PHY_358_VAL
    0x76543210U, // DDRSS_PHY_359_VAL
    0x00000008U, // DDRSS_PHY_360_VAL
    0x02800280U, // DDRSS_PHY_361_VAL
    0x02800280U, // DDRSS_PHY_362_VAL
    0x02800280U, // DDRSS_PHY_363_VAL
    0x02800280U, // DDRSS_PHY_364_VAL
    0x00000280U, // DDRSS_PHY_365_VAL
    0x00008000U, // DDRSS_PHY_366_VAL
    0x00800080U, // DDRSS_PHY_367_VAL
    0x00800080U, // DDRSS_PHY_368_VAL
    0x00800080U, // DDRSS_PHY_369_VAL
    0x00800080U, // DDRSS_PHY_370_VAL
    0x00800080U, // DDRSS_PHY_371_VAL
    0x00800080U, // DDRSS_PHY_372_VAL
    0x00800080U, // DDRSS_PHY_373_VAL
    0x00800080U, // DDRSS_PHY_374_VAL
    0x01000080U, // DDRSS_PHY_375_VAL
    0x01000000U, // DDRSS_PHY_376_VAL
    0x00000000U, // DDRSS_PHY_377_VAL
    0x00000000U, // DDRSS_PHY_378_VAL
    0x00080200U, // DDRSS_PHY_379_VAL
    0x00000000U, // DDRSS_PHY_380_VAL
    0x00000000U, // DDRSS_PHY_381_VAL
    0x00000100U, // DDRSS_PHY_512_VAL
    0x00000000U, // DDRSS_PHY_513_VAL
    0x00000000U, // DDRSS_PHY_514_VAL
    0x00000000U, // DDRSS_PHY_515_VAL
    0x00000000U, // DDRSS_PHY_516_VAL
    0x00000100U, // DDRSS_PHY_517_VAL
    0x00000000U, // DDRSS_PHY_518_VAL
    0x00000000U, // DDRSS_PHY_519_VAL
    0x00000000U, // DDRSS_PHY_520_VAL
    0x00000000U, // DDRSS_PHY_521_VAL
    0x00000000U, // DDRSS_PHY_522_VAL
    0x00000000U, // DDRSS_PHY_523_VAL
    0x00000000U, // DDRSS_PHY_524_VAL
    0x00DCBA98U, // DDRSS_PHY_525_VAL
    0x00000000U, // DDRSS_PHY_526_VAL
    0x00000000U, // DDRSS_PHY_527_VAL
    0x00000000U, // DDRSS_PHY_528_VAL
    0x00000000U, // DDRSS_PHY_529_VAL
    0x00000000U, // DDRSS_PHY_530_VAL
    0x00000000U, // DDRSS_PHY_531_VAL
    0x00000000U, // DDRSS_PHY_532_VAL
    0x00000000U, // DDRSS_PHY_533_VAL
    0x00000000U, // DDRSS_PHY_534_VAL
    0x00000000U, // DDRSS_PHY_535_VAL
    0x00000000U, // DDRSS_PHY_536_VAL
    0x00000000U, // DDRSS_PHY_537_VAL
    0x00000000U, // DDRSS_PHY_538_VAL
    0x00000000U, // DDRSS_PHY_539_VAL
    0x0A418820U, // DDRSS_PHY_540_VAL
    0x103F0000U, // DDRSS_PHY_541_VAL
    0x000F0100U, // DDRSS_PHY_542_VAL
    0x0000000FU, // DDRSS_PHY_543_VAL
    0x020002CCU, // DDRSS_PHY_544_VAL
    0x00030000U, // DDRSS_PHY_545_VAL
    0x00000300U, // DDRSS_PHY_546_VAL
    0x00000300U, // DDRSS_PHY_547_VAL
    0x00000300U, // DDRSS_PHY_548_VAL
    0x00000300U, // DDRSS_PHY_549_VAL
    0x00000300U, // DDRSS_PHY_550_VAL
    0x42080010U, // DDRSS_PHY_551_VAL
    0x0000003EU, // DDRSS_PHY_552_VAL
    0x00000000U, // DDRSS_PHY_553_VAL
    0x00000000U, // DDRSS_PHY_554_VAL
    0x00000100U, // DDRSS_PHY_768_VAL
    0x00000000U, // DDRSS_PHY_769_VAL
    0x00000000U, // DDRSS_PHY_770_VAL
    0x00000000U, // DDRSS_PHY_771_VAL
    0x00000000U, // DDRSS_PHY_772_VAL
    0x00000100U, // DDRSS_PHY_773_VAL
    0x00000000U, // DDRSS_PHY_774_VAL
    0x00000000U, // DDRSS_PHY_775_VAL
    0x00000000U, // DDRSS_PHY_776_VAL
    0x00000000U, // DDRSS_PHY_777_VAL
    0x00000000U, // DDRSS_PHY_778_VAL
    0x00000000U, // DDRSS_PHY_779_VAL
    0x00000000U, // DDRSS_PHY_780_VAL
    0x00DCBA98U, // DDRSS_PHY_781_VAL
    0x00000000U, // DDRSS_PHY_782_VAL
    0x00000000U, // DDRSS_PHY_783_VAL
    0x00000000U, // DDRSS_PHY_784_VAL
    0x00000000U, // DDRSS_PHY_785_VAL
    0x00000000U, // DDRSS_PHY_786_VAL
    0x00000000U, // DDRSS_PHY_787_VAL
    0x00000000U, // DDRSS_PHY_788_VAL
    0x00000000U, // DDRSS_PHY_789_VAL
    0x00000000U, // DDRSS_PHY_790_VAL
    0x00000000U, // DDRSS_PHY_791_VAL
    0x00000000U, // DDRSS_PHY_792_VAL
    0x00000000U, // DDRSS_PHY_793_VAL
    0x00000000U, // DDRSS_PHY_794_VAL
    0x00000000U, // DDRSS_PHY_795_VAL
    0x16A4A0E6U, // DDRSS_PHY_796_VAL
    0x103F0000U, // DDRSS_PHY_797_VAL
    0x000F0000U, // DDRSS_PHY_798_VAL
    0x0000000FU, // DDRSS_PHY_799_VAL
    0x020002CCU, // DDRSS_PHY_800_VAL
    0x00030000U, // DDRSS_PHY_801_VAL
    0x00000300U, // DDRSS_PHY_802_VAL
    0x00000300U, // DDRSS_PHY_803_VAL
    0x00000300U, // DDRSS_PHY_804_VAL
    0x00000300U, // DDRSS_PHY_805_VAL
    0x00000300U, // DDRSS_PHY_806_VAL
    0x42080010U, // DDRSS_PHY_807_VAL
    0x0000003EU, // DDRSS_PHY_808_VAL
    0x00000000U, // DDRSS_PHY_809_VAL
    0x00000000U, // DDRSS_PHY_810_VAL
    0x00000100U, // DDRSS_PHY_1024_VAL
    0x00000000U, // DDRSS_PHY_1025_VAL
    0x00000000U, // DDRSS_PHY_1026_VAL
    0x00000000U, // DDRSS_PHY_1027_VAL
    0x00000000U, // DDRSS_PHY_1028_VAL
    0x00000100U, // DDRSS_PHY_1029_VAL
    0x00000000U, // DDRSS_PHY_1030_VAL
    0x00000000U, // DDRSS_PHY_1031_VAL
    0x00000000U, // DDRSS_PHY_1032_VAL
    0x00000000U, // DDRSS_PHY_1033_VAL
    0x00000000U, // DDRSS_PHY_1034_VAL
    0x00000000U, // DDRSS_PHY_1035_VAL
    0x00000000U, // DDRSS_PHY_1036_VAL
    0x00DCBA98U, // DDRSS_PHY_1037_VAL
    0x00000000U, // DDRSS_PHY_1038_VAL
    0x00000000U, // DDRSS_PHY_1039_VAL
    0x00000000U, // DDRSS_PHY_1040_VAL
    0x00000000U, // DDRSS_PHY_1041_VAL
    0x00000000U, // DDRSS_PHY_1042_VAL
    0x00000000U, // DDRSS_PHY_1043_VAL
    0x00000000U, // DDRSS_PHY_1044_VAL
    0x00000000U, // DDRSS_PHY_1045_VAL
    0x00000000U, // DDRSS_PHY_1046_VAL
    0x00000000U, // DDRSS_PHY_1047_VAL
    0x00000000U, // DDRSS_PHY_1048_VAL
    0x00000000U, // DDRSS_PHY_1049_VAL
    0x00000000U, // DDRSS_PHY_1050_VAL
    0x00000000U, // DDRSS_PHY_1051_VAL
    0x2307B9ACU, // DDRSS_PHY_1052_VAL
    0x10030000U, // DDRSS_PHY_1053_VAL
    0x000F0000U, // DDRSS_PHY_1054_VAL
    0x0000000FU, // DDRSS_PHY_1055_VAL
    0x020002CCU, // DDRSS_PHY_1056_VAL
    0x00030000U, // DDRSS_PHY_1057_VAL
    0x00000300U, // DDRSS_PHY_1058_VAL
    0x00000300U, // DDRSS_PHY_1059_VAL
    0x00000300U, // DDRSS_PHY_1060_VAL
    0x00000300U, // DDRSS_PHY_1061_VAL
    0x00000300U, // DDRSS_PHY_1062_VAL
    0x42080010U, // DDRSS_PHY_1063_VAL
    0x0000003EU, // DDRSS_PHY_1064_VAL
    0x00000000U, // DDRSS_PHY_1065_VAL
    0x00000000U, // DDRSS_PHY_1066_VAL
    0x00000000U, // DDRSS_PHY_1280_VAL
    0x00000100U, // DDRSS_PHY_1281_VAL
    0x00000000U, // DDRSS_PHY_1282_VAL
    0x00000000U, // DDRSS_PHY_1283_VAL
    0x00000000U, // DDRSS_PHY_1284_VAL
    0x00000000U, // DDRSS_PHY_1285_VAL
    0x00050000U, // DDRSS_PHY_1286_VAL
    0x04000100U, // DDRSS_PHY_1287_VAL
    0x00000055U, // DDRSS_PHY_1288_VAL
    0x00000000U, // DDRSS_PHY_1289_VAL
    0x00000000U, // DDRSS_PHY_1290_VAL
    0x00000000U, // DDRSS_PHY_1291_VAL
    0x00000000U, // DDRSS_PHY_1292_VAL
    0x01002000U, // DDRSS_PHY_1293_VAL
    0x00004001U, // DDRSS_PHY_1294_VAL
    0x00020028U, // DDRSS_PHY_1295_VAL
    0x00010100U, // DDRSS_PHY_1296_VAL
    0x00000001U, // DDRSS_PHY_1297_VAL
    0x00000000U, // DDRSS_PHY_1298_VAL
    0x0F0F0E06U, // DDRSS_PHY_1299_VAL
    0x00010101U, // DDRSS_PHY_1300_VAL
    0x010F0004U, // DDRSS_PHY_1301_VAL
    0x00000000U, // DDRSS_PHY_1302_VAL
    0x00000000U, // DDRSS_PHY_1303_VAL
    0x00000064U, // DDRSS_PHY_1304_VAL
    0x00000000U, // DDRSS_PHY_1305_VAL
    0x00000000U, // DDRSS_PHY_1306_VAL
    0x01020103U, // DDRSS_PHY_1307_VAL
    0x0F020102U, // DDRSS_PHY_1308_VAL
    0x03030303U, // DDRSS_PHY_1309_VAL
    0x03030303U, // DDRSS_PHY_1310_VAL
    0x00040000U, // DDRSS_PHY_1311_VAL
    0x00005201U, // DDRSS_PHY_1312_VAL
    0x00000000U, // DDRSS_PHY_1313_VAL
    0x00000000U, // DDRSS_PHY_1314_VAL
    0x00000000U, // DDRSS_PHY_1315_VAL
    0x00000000U, // DDRSS_PHY_1316_VAL
    0x00000000U, // DDRSS_PHY_1317_VAL
    0x00000000U, // DDRSS_PHY_1318_VAL
    0x07070001U, // DDRSS_PHY_1319_VAL
    0x00005400U, // DDRSS_PHY_1320_VAL
    0x000040A2U, // DDRSS_PHY_1321_VAL
    0x00024410U, // DDRSS_PHY_1322_VAL
    0x00004410U, // DDRSS_PHY_1323_VAL
    0x00004410U, // DDRSS_PHY_1324_VAL
    0x00004410U, // DDRSS_PHY_1325_VAL
    0x00004410U, // DDRSS_PHY_1326_VAL
    0x00004410U, // DDRSS_PHY_1327_VAL
    0x00004410U, // DDRSS_PHY_1328_VAL
    0x00004410U, // DDRSS_PHY_1329_VAL
    0x00004410U, // DDRSS_PHY_1330_VAL
    0x00004410U, // DDRSS_PHY_1331_VAL
    0x00000000U, // DDRSS_PHY_1332_VAL
    0x00000046U, // DDRSS_PHY_1333_VAL
    0x00000400U, // DDRSS_PHY_1334_VAL
    0x00000008U, // DDRSS_PHY_1335_VAL
    0x00000000U, // DDRSS_PHY_1336_VAL
    0x00000000U, // DDRSS_PHY_1337_VAL
    0x00000000U, // DDRSS_PHY_1338_VAL
    0x00000000U, // DDRSS_PHY_1339_VAL
    0x00000000U, // DDRSS_PHY_1340_VAL
    0x03000000U, // DDRSS_PHY_1341_VAL
    0x00000000U, // DDRSS_PHY_1342_VAL
    0x00000000U, // DDRSS_PHY_1343_VAL
    0x00000000U, // DDRSS_PHY_1344_VAL
    0x04102006U, // DDRSS_PHY_1345_VAL
    0x00041020U, // DDRSS_PHY_1346_VAL
    0x01C98C98U, // DDRSS_PHY_1347_VAL
    0x3F400000U, // DDRSS_PHY_1348_VAL
    0x3F3F1F3FU, // DDRSS_PHY_1349_VAL
    0x0000001FU, // DDRSS_PHY_1350_VAL
    0x00000000U, // DDRSS_PHY_1351_VAL
    0x00000000U, // DDRSS_PHY_1352_VAL
    0x00000000U, // DDRSS_PHY_1353_VAL
    0x00000001U, // DDRSS_PHY_1354_VAL
    0x00000000U, // DDRSS_PHY_1355_VAL
    0x00000000U, // DDRSS_PHY_1356_VAL
    0x00000000U, // DDRSS_PHY_1357_VAL
    0x00000000U, // DDRSS_PHY_1358_VAL
    0x76543210U, // DDRSS_PHY_1359_VAL
    0x00000098U, // DDRSS_PHY_1360_VAL
    0x00000000U, // DDRSS_PHY_1361_VAL
    0x00000000U, // DDRSS_PHY_1362_VAL
    0x00000000U, // DDRSS_PHY_1363_VAL
    0x00040700U, // DDRSS_PHY_1364_VAL
    0x00000000U, // DDRSS_PHY_1365_VAL
    0x00000000U, // DDRSS_PHY_1366_VAL
    0x00000000U, // DDRSS_PHY_1367_VAL
    0x00000002U, // DDRSS_PHY_1368_VAL
    0x00000100U, // DDRSS_PHY_1369_VAL
    0x00000000U, // DDRSS_PHY_1370_VAL
    0x0001F7C2U, // DDRSS_PHY_1371_VAL
    0x00020002U, // DDRSS_PHY_1372_VAL
    0x00000000U, // DDRSS_PHY_1373_VAL
    0x00001142U, // DDRSS_PHY_1374_VAL
    0x03020400U, // DDRSS_PHY_1375_VAL
    0x00000080U, // DDRSS_PHY_1376_VAL
    0x03900390U, // DDRSS_PHY_1377_VAL
    0x03900390U, // DDRSS_PHY_1378_VAL
    0x03900390U, // DDRSS_PHY_1379_VAL
    0x03900390U, // DDRSS_PHY_1380_VAL
    0x03900390U, // DDRSS_PHY_1381_VAL
    0x03900390U, // DDRSS_PHY_1382_VAL
    0x00000300U, // DDRSS_PHY_1383_VAL
    0x00000300U, // DDRSS_PHY_1384_VAL
    0x00000300U, // DDRSS_PHY_1385_VAL
    0x00000300U, // DDRSS_PHY_1386_VAL
    0x31823FC7U, // DDRSS_PHY_1387_VAL
    0x00000000U, // DDRSS_PHY_1388_VAL
    0x0C000D3FU, // DDRSS_PHY_1389_VAL
    0x30000D3FU, // DDRSS_PHY_1390_VAL
    0x300D3F11U, // DDRSS_PHY_1391_VAL
    0x01990000U, // DDRSS_PHY_1392_VAL
    0x000D3FCCU, // DDRSS_PHY_1393_VAL
    0x00000C11U, // DDRSS_PHY_1394_VAL
    0x300D3F11U, // DDRSS_PHY_1395_VAL
    0x01990000U, // DDRSS_PHY_1396_VAL
    0x300C3F11U, // DDRSS_PHY_1397_VAL
    0x01990000U, // DDRSS_PHY_1398_VAL
    0x300C3F11U, // DDRSS_PHY_1399_VAL
    0x01990000U, // DDRSS_PHY_1400_VAL
    0x300D3F11U, // DDRSS_PHY_1401_VAL
    0x01990000U, // DDRSS_PHY_1402_VAL
    0x300D3F11U, // DDRSS_PHY_1403_VAL
    0x01990000U, // DDRSS_PHY_1404_VAL
    0x20040004U, // DDRSS_PHY_1405_VAL
};

uint16_t DDRSS_ctlRegNum[] = {
    0,
    1,
    2,
    3,
    4,
    5,
    6,
    7,
    8,
    9,
    10,
    11,
    12,
    13,
    14,
    15,
    16,
    17,
    18,
    19,
    20,
    21,
    22,
    23,
    24,
    25,
    26,
    27,
    28,
    29,
    30,
    31,
    32,
    33,
    34,
    35,
    36,
    37,
    38,
    39,
    40,
    41,
    42,
    43,
    44,
    45,
    46,
    47,
    48,
    49,
    50,
    51,
    52,
    53,
    54,
    55,
    56,
    57,
    58,
    59,
    60,
    61,
    62,
    63,
    64,
    65,
    66,
    67,
    68,
    69,
    70,
    71,
    72,
    73,
    74,
    75,
    76,
    77,
    78,
    79,
    80,
    81,
    82,
    83,
    84,
    85,
    86,
    87,
    88,
    89,
    90,
    91,
    92,
    93,
    94,
    95,
    96,
    97,
    98,
    99,
    100,
    101,
    102,
    103,
    104,
    105,
    106,
    107,
    108,
    109,
    110,
    111,
    112,
    113,
    114,
    115,
    116,
    117,
    118,
    119,
    120,
    121,
    122,
    123,
    124,
    125,
    126,
    127,
    128,
    129,
    130,
    131,
    132,
    133,
    134,
    135,
    136,
    137,
    138,
    139,
    140,
    141,
    142,
    143,
    144,
    145,
    146,
    147,
    148,
    149,
    150,
    151,
    152,
    153,
    154,
    155,
    156,
    157,
    158,
    159,
    160,
    161,
    162,
    163,
    164,
    165,
    166,
    167,
    168,
    169,
    170,
    171,
    172,
    173,
    174,
    175,
    176,
    177,
    178,
    179,
    180,
    181,
    182,
    183,
    184,
    185,
    186,
    187,
    188,
    189,
    190,
    191,
    192,
    193,
    194,
    195,
    196,
    197,
    198,
    199,
    200,
    201,
    202,
    203,
    204,
    205,
    206,
    207,
    208,
    209,
    210,
    211,
    212,
    213,
    214,
    215,
    216,
    217,
    218,
    219,
    220,
    221,
    222,
    223,
    224,
    225,
    226,
    227,
    228,
    229,
    230,
    231,
    232,
    233,
    234,
    235,
    236,
    237,
    238,
    239,
    240,
    241,
    242,
    243,
    244,
    245,
    246,
    247,
    248,
    249,
    250,
    251,
    252,
    253,
    254,
    255,
    256,
    257,
    258,
    259,
    260,
    261,
    262,
    263,
    264,
    265,
    266,
    267,
    268,
    269,
    270,
    271,
    272,
    273,
    274,
    275,
    276,
    277,
    278,
    279,
    280,
    281,
    282,
    283,
    284,
    285,
    286,
    287,
    288,
    289,
    290,
    291,
    292,
    293,
    294,
    295,
    296,
    297,
    298,
    299,
    300,
    301,
    302,
    303,
    304,
    305,
    306,
    307,
    308,
    309,
    310,
    311,
    312,
    313,
    314,
    315,
    316,
    317,
    318,
    319,
    320,
    321,
    322,
    323,
    324,
    325,
    326,
    327,
    328,
    329,
    330,
    331,
    332,
    333,
    334,
    335,
    336,
    337,
    338,
    339,
    340,
    341,
    342,
    343,
    344,
    345,
    346,
    347,
    348,
    349,
    350,
    351,
    352,
    353,
    354,
    355,
    356,
    357,
    358,
    359,
    360,
    361,
    362,
    363,
    364,
    365,
    366,
    367,
    368,
    369,
    370,
    371,
    372,
    373,
    374,
    375,
    376,
    377,
    378,
    379,
    380,
    381,
    382,
    383,
    384,
    385,
    386,
    387,
    388,
    389,
    390,
    391,
    392,
    393,
    394,
    395,
    396,
    397,
    398,
    399,
    400,
    401,
    402,
    403,
    404,
    405,
    406,
    407,
    408,
    409,
    410,
    411,
    412,
    413,
    414,
    415,
    416,
    417,
    418,
    419,
    420,
    421,
    422,
};

uint16_t DDRSS_phyIndepRegNum[] = {
    0,
    1,
    2,
    3,
    4,
    5,
    6,
    7,
    8,
    9,
    10,
    11,
    12,
    13,
    14,
    15,
    16,
    17,
    18,
    19,
    20,
    21,
    22,
    23,
    24,
    25,
    26,
    27,
    28,
    29,
    30,
    31,
    32,
    33,
    34,
    35,
    36,
    37,
    38,
    39,
    40,
    41,
    42,
    43,
    44,
    45,
    46,
    47,
    48,
    49,
    50,
    51,
    52,
    53,
    54,
    55,
    56,
    57,
    58,
    59,
    60,
    61,
    62,
    63,
    64,
    65,
    66,
    67,
    68,
    69,
    70,
    71,
    72,
    73,
    74,
    75,
    76,
    77,
    78,
    79,
    80,
    81,
    82,
    83,
    84,
    85,
    86,
    87,
    88,
    89,
    90,
    91,
    92,
    93,
    94,
    95,
    96,
    97,
    98,
    99,
    100,
    101,
    102,
    103,
    104,
    105,
    106,
    107,
    108,
    109,
    110,
    111,
    112,
    113,
    114,
    115,
    116,
    117,
    118,
    119,
    120,
    121,
    122,
    123,
    124,
    125,
    126,
    127,
    128,
    129,
    130,
    131,
    132,
    133,
    134,
    135,
    136,
    137,
    138,
    139,
    140,
    141,
    142,
    143,
    144,
    145,
    146,
    147,
    148,
    149,
    150,
    151,
    152,
    153,
    154,
    155,
    156,
    157,
    158,
    159,
    160,
    161,
    162,
    163,
    164,
    165,
    166,
    167,
    168,
    169,
    170,
    171,
    172,
    173,
    174,
    175,
    176,
    177,
    178,
    179,
    180,
    181,
    182,
    183,
    184,
    185,
    186,
    187,
    188,
    189,
    190,
    191,
    192,
    193,
    194,
    195,
    196,
    197,
    198,
    199,
    200,
    201,
    202,
    203,
    204,
    205,
    206,
    207,
    208,
    209,
    210,
    211,
    212,
    213,
    214,
    215,
    216,
    217,
    218,
    219,
    220,
    221,
    222,
    223,
    224,
    225,
    226,
    227,
    228,
    229,
    230,
    231,
    232,
    233,
    234,
    235,
    236,
    237,
    238,
    239,
    240,
    241,
    242,
    243,
    244,
    245,
    246,
    247,
    248,
    249,
    250,
    251,
    252,
    253,
    254,
    255,
    256,
    257,
    258,
    259,
    260,
    261,
    262,
    263,
    264,
    265,
    266,
    267,
    268,
    269,
    270,
    271,
    272,
    273,
    274,
    275,
    276,
    277,
    278,
    279,
    280,
    281,
    282,
    283,
    284,
    285,
    286,
    287,
    288,
    289,
    290,
    291,
    292,
    293,
    294,
    295,
    296,
    297,
    298,
    299,
    300,
    301,
    302,
    303,
    304,
    305,
    306,
    307,
    308,
    309,
    310,
    311,
    312,
    313,
    314,
    315,
    316,
    317,
    318,
    319,
    320,
    321,
    322,
    323,
    324,
    325,
    326,
    327,
    328,
    329,
    330,
    331,
    332,
    333,
    334,
    335,
    336,
    337,
    338,
    339,
    340,
    341,
    342,
    343,
    344,
};

uint16_t DDRSS_phyRegNum[] = {
    0,
    1,
    2,
    3,
    4,
    5,
    6,
    7,
    8,
    9,
    10,
    11,
    12,
    13,
    14,
    15,
    16,
    17,
    18,
    19,
    20,
    21,
    22,
    23,
    24,
    25,
    26,
    27,
    28,
    29,
    30,
    31,
    32,
    33,
    34,
    35,
    36,
    37,
    38,
    39,
    40,
    41,
    42,
    43,
    44,
    45,
    46,
    47,
    48,
    49,
    50,
    51,
    52,
    53,
    54,
    55,
    56,
    57,
    58,
    59,
    60,
    61,
    62,
    63,
    64,
    65,
    66,
    67,
    68,
    69,
    70,
    71,
    72,
    73,
    74,
    75,
    76,
    77,
    78,
    79,
    80,
    81,
    82,
    83,
    84,
    85,
    86,
    87,
    88,
    89,
    90,
    91,
    92,
    93,
    94,
    95,
    96,
    97,
    98,
    99,
    100,
    101,
    102,
    103,
    104,
    105,
    106,
    107,
    108,
    109,
    110,
    111,
    112,
    113,
    114,
    115,
    116,
    117,
    118,
    119,
    120,
    121,
    122,
    123,
    124,
    125,
    256,
    257,
    258,
    259,
    260,
    261,
    262,
    263,
    264,
    265,
    266,
    267,
    268,
    269,
    270,
    271,
    272,
    273,
    274,
    275,
    276,
    277,
    278,
    279,
    280,
    281,
    282,
    283,
    284,
    285,
    286,
    287,
    288,
    289,
    290,
    291,
    292,
    293,
    294,
    295,
    296,
    297,
    298,
    299,
    300,
    301,
    302,
    303,
    304,
    305,
    306,
    307,
    308,
    309,
    310,
    311,
    312,
    313,
    314,
    315,
    316,
    317,
    318,
    319,
    320,
    321,
    322,
    323,
    324,
    325,
    326,
    327,
    328,
    329,
    330,
    331,
    332,
    333,
    334,
    335,
    336,
    337,
    338,
    339,
    340,
    341,
    342,
    343,
    344,
    345,
    346,
    347,
    348,
    349,
    350,
    351,
    352,
    353,
    354,
    355,
    356,
    357,
    358,
    359,
    360,
    361,
    362,
    363,
    364,
    365,
    366,
    367,
    368,
    369,
    370,
    371,
    372,
    373,
    374,
    375,
    376,
    377,
    378,
    379,
    380,
    381,
    512,
    513,
    514,
    515,
    516,
    517,
    518,
    519,
    520,
    521,
    522,
    523,
    524,
    525,
    526,
    527,
    528,
    529,
    530,
    531,
    532,
    533,
    534,
    535,
    536,
    537,
    538,
    539,
    540,
    541,
    542,
    543,
    544,
    545,
    546,
    547,
    548,
    549,
    550,
    551,
    552,
    553,
    554,
    768,
    769,
    770,
    771,
    772,
    773,
    774,
    775,
    776,
    777,
    778,
    779,
    780,
    781,
    782,
    783,
    784,
    785,
    786,
    787,
    788,
    789,
    790,
    791,
    792,
    793,
    794,
    795,
    796,
    797,
    798,
    799,
    800,
    801,
    802,
    803,
    804,
    805,
    806,
    807,
    808,
    809,
    810,
    1024,
    1025,
    1026,
    1027,
    1028,
    1029,
    1030,
    1031,
    1032,
    1033,
    1034,
    1035,
    1036,
    1037,
    1038,
    1039,
    1040,
    1041,
    1042,
    1043,
    1044,
    1045,
    1046,
    1047,
    1048,
    1049,
    1050,
    1051,
    1052,
    1053,
    1054,
    1055,
    1056,
    1057,
    1058,
    1059,
    1060,
    1061,
    1062,
    1063,
    1064,
    1065,
    1066,
    1280,
    1281,
    1282,
    1283,
    1284,
    1285,
    1286,
    1287,
    1288,
    1289,
    1290,
    1291,
    1292,
    1293,
    1294,
    1295,
    1296,
    1297,
    1298,
    1299,
    1300,
    1301,
    1302,
    1303,
    1304,
    1305,
    1306,
    1307,
    1308,
    1309,
    1310,
    1311,
    1312,
    1313,
    1314,
    1315,
    1316,
    1317,
    1318,
    1319,
    1320,
    1321,
    1322,
    1323,
    1324,
    1325,
    1326,
    1327,
    1328,
    1329,
    1330,
    1331,
    1332,
    1333,
    1334,
    1335,
    1336,
    1337,
    1338,
    1339,
    1340,
    1341,
    1342,
    1343,
    1344,
    1345,
    1346,
    1347,
    1348,
    1349,
    1350,
    1351,
    1352,
    1353,
    1354,
    1355,
    1356,
    1357,
    1358,
    1359,
    1360,
    1361,
    1362,
    1363,
    1364,
    1365,
    1366,
    1367,
    1368,
    1369,
    1370,
    1371,
    1372,
    1373,
    1374,
    1375,
    1376,
    1377,
    1378,
    1379,
    1380,
    1381,
    1382,
    1383,
    1384,
    1385,
    1386,
    1387,
    1388,
    1389,
    1390,
    1391,
    1392,
    1393,
    1394,
    1395,
    1396,
    1397,
    1398,
    1399,
    1400,
    1401,
    1402,
    1403,
    1404,
    1405,
};
#ifdef __cplusplus
} 
#endif

#endif

And the register dump with this configuration is: code runs to  before DDR write&read start,

MAIN_Cortex_R5_0_0: GEL Output: CPU reset (soft reset) has been issued through GEL.
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308000 0x10460A01  //DDRSS_CTL_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308004 0x5D1AF3C3  //DDRSS_CTL_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308008 0x0171A610  //DDRSS_CTL_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30800C 0x40020A11  //DDRSS_CTL_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308010 0x00052006  //DDRSS_CTL_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308014 0x02050020  //DDRSS_CTL_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308018 0x03070101  //DDRSS_CTL_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30801C 0x00089070  //DDRSS_CTL_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308020 0x00000000  //DDRSS_CTL_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308024 0x00000000  //DDRSS_CTL_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308028 0x00000000  //DDRSS_CTL_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30802C 0x00089070  //DDRSS_CTL_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308030 0x00000000  //DDRSS_CTL_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308034 0x00000000  //DDRSS_CTL_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308038 0x00000000  //DDRSS_CTL_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30803C 0x00089070  //DDRSS_CTL_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308040 0x00000000  //DDRSS_CTL_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308044 0x00000000  //DDRSS_CTL_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308048 0x00000000  //DDRSS_CTL_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30804C 0x01010100  //DDRSS_CTL_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308050 0x01000101  //DDRSS_CTL_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308054 0x01000110  //DDRSS_CTL_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308058 0x02010002  //DDRSS_CTL_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30805C 0x00027100  //DDRSS_CTL_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308060 0x00061A80  //DDRSS_CTL_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308064 0x02550255  //DDRSS_CTL_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308068 0x00000255  //DDRSS_CTL_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30806C 0x00000000  //DDRSS_CTL_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308070 0x00000000  //DDRSS_CTL_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308074 0x00000000  //DDRSS_CTL_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308078 0x00000000  //DDRSS_CTL_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30807C 0x00000000  //DDRSS_CTL_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308080 0x00000000  //DDRSS_CTL_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308084 0x00000000  //DDRSS_CTL_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308088 0x00000000  //DDRSS_CTL_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30808C 0x00000000  //DDRSS_CTL_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308090 0x00000000  //DDRSS_CTL_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308094 0x00000000  //DDRSS_CTL_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308098 0x04000B16  //DDRSS_CTL_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30809C 0x1C1C1C1C  //DDRSS_CTL_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A0 0x04000B16  //DDRSS_CTL_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A4 0x1C1C1C1C  //DDRSS_CTL_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A8 0x04000B16  //DDRSS_CTL_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080AC 0x1C1C1C1C  //DDRSS_CTL_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B0 0x05050404  //DDRSS_CTL_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B4 0x00002706  //DDRSS_CTL_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B8 0x0602001D  //DDRSS_CTL_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080BC 0x05001D0B  //DDRSS_CTL_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C0 0x00270605  //DDRSS_CTL_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C4 0x0602001D  //DDRSS_CTL_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C8 0x05001D0B  //DDRSS_CTL_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080CC 0x00270605  //DDRSS_CTL_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D0 0x0602001D  //DDRSS_CTL_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D4 0x07001D0B  //DDRSS_CTL_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D8 0x00180807  //DDRSS_CTL_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080DC 0x0400DB60  //DDRSS_CTL_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E0 0x07070009  //DDRSS_CTL_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E4 0x00001808  //DDRSS_CTL_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E8 0x0400DB60  //DDRSS_CTL_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080EC 0x07070009  //DDRSS_CTL_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F0 0x00001808  //DDRSS_CTL_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F4 0x0400DB60  //DDRSS_CTL_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F8 0x03000009  //DDRSS_CTL_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080FC 0x0D0C0002  //DDRSS_CTL_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308100 0x0D0C0D0C  //DDRSS_CTL_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308104 0x01010000  //DDRSS_CTL_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308108 0x03191919  //DDRSS_CTL_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30810C 0x0B0B0B0B  //DDRSS_CTL_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308110 0x00000B0B  //DDRSS_CTL_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308114 0x00000101  //DDRSS_CTL_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308118 0x00000000  //DDRSS_CTL_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30811C 0x01000000  //DDRSS_CTL_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308120 0x00D00803  //DDRSS_CTL_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308124 0x00001860  //DDRSS_CTL_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308128 0x000000D0  //DDRSS_CTL_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30812C 0x00001860  //DDRSS_CTL_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308130 0x000000D0  //DDRSS_CTL_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308134 0x00001860  //DDRSS_CTL_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308138 0x00000005  //DDRSS_CTL_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30813C 0x00000000  //DDRSS_CTL_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308140 0x00000000  //DDRSS_CTL_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308144 0x00000000  //DDRSS_CTL_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308148 0x00000000  //DDRSS_CTL_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30814C 0x00000000  //DDRSS_CTL_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308150 0x00000000  //DDRSS_CTL_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308154 0x00000000  //DDRSS_CTL_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308158 0x00000000  //DDRSS_CTL_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30815C 0x00090009  //DDRSS_CTL_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308160 0x00000009  //DDRSS_CTL_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308164 0x00000000  //DDRSS_CTL_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308168 0x00000000  //DDRSS_CTL_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30816C 0x00000000  //DDRSS_CTL_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308170 0x00000000  //DDRSS_CTL_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308174 0x00000000  //DDRSS_CTL_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308178 0x00010001  //DDRSS_CTL_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30817C 0x00025501  //DDRSS_CTL_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308180 0x025500D8  //DDRSS_CTL_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308184 0x025500D8  //DDRSS_CTL_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308188 0x00D800D8  //DDRSS_CTL_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30818C 0x00D800D8  //DDRSS_CTL_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308190 0x00000000  //DDRSS_CTL_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308194 0x00000000  //DDRSS_CTL_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308198 0x00000000  //DDRSS_CTL_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30819C 0x00000000  //DDRSS_CTL_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A0 0x00000000  //DDRSS_CTL_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A4 0x00000000  //DDRSS_CTL_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A8 0x03010000  //DDRSS_CTL_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081AC 0x00010000  //DDRSS_CTL_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B0 0x00000000  //DDRSS_CTL_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B4 0x01000000  //DDRSS_CTL_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B8 0x80104002  //DDRSS_CTL_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081BC 0x00040003  //DDRSS_CTL_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C0 0x00040005  //DDRSS_CTL_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C4 0x00030000  //DDRSS_CTL_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C8 0x00050004  //DDRSS_CTL_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081CC 0x00000004  //DDRSS_CTL_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D0 0x00040003  //DDRSS_CTL_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D4 0x00040005  //DDRSS_CTL_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D8 0x00000000  //DDRSS_CTL_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081DC 0x00061800  //DDRSS_CTL_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E0 0x00061800  //DDRSS_CTL_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E4 0x00061800  //DDRSS_CTL_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E8 0x00061800  //DDRSS_CTL_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081EC 0x00061800  //DDRSS_CTL_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F0 0x00000000  //DDRSS_CTL_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F4 0x0000AAA0  //DDRSS_CTL_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F8 0x00061800  //DDRSS_CTL_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081FC 0x00061800  //DDRSS_CTL_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308200 0x00061800  //DDRSS_CTL_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308204 0x00061800  //DDRSS_CTL_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308208 0x00061800  //DDRSS_CTL_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30820C 0x00000000  //DDRSS_CTL_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308210 0x0000AAA0  //DDRSS_CTL_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308214 0x00061800  //DDRSS_CTL_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308218 0x00061800  //DDRSS_CTL_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30821C 0x00061800  //DDRSS_CTL_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308220 0x00061800  //DDRSS_CTL_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308224 0x00061800  //DDRSS_CTL_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308228 0x00000000  //DDRSS_CTL_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30822C 0x0000AAA0  //DDRSS_CTL_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308230 0x00000000  //DDRSS_CTL_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308234 0x00000000  //DDRSS_CTL_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308238 0x00000000  //DDRSS_CTL_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30823C 0x00000000  //DDRSS_CTL_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308240 0x00000000  //DDRSS_CTL_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308244 0x00000000  //DDRSS_CTL_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308248 0x00000000  //DDRSS_CTL_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30824C 0x00000000  //DDRSS_CTL_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308250 0x00000000  //DDRSS_CTL_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308254 0x00000000  //DDRSS_CTL_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308258 0x00000000  //DDRSS_CTL_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30825C 0x00000000  //DDRSS_CTL_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308260 0x00000000  //DDRSS_CTL_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308264 0x00000000  //DDRSS_CTL_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308268 0x00000000  //DDRSS_CTL_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30826C 0x00000000  //DDRSS_CTL_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308270 0x080C0000  //DDRSS_CTL_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308274 0x080C080C  //DDRSS_CTL_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308278 0x00000000  //DDRSS_CTL_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30827C 0x07010A09  //DDRSS_CTL_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308280 0x000E0A09  //DDRSS_CTL_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308284 0x010A0900  //DDRSS_CTL_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308288 0x0E0A0907  //DDRSS_CTL_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30828C 0x0A090000  //DDRSS_CTL_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308290 0x0A090701  //DDRSS_CTL_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308294 0x0000080E  //DDRSS_CTL_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308298 0x00040003  //DDRSS_CTL_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30829C 0x00004007  //DDRSS_CTL_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A0 0x00000000  //DDRSS_CTL_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A4 0x00000000  //DDRSS_CTL_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A8 0x00000000  //DDRSS_CTL_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082AC 0x00000000  //DDRSS_CTL_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B0 0x00000000  //DDRSS_CTL_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B4 0x00000000  //DDRSS_CTL_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B8 0x01000000  //DDRSS_CTL_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082BC 0x00000000  //DDRSS_CTL_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C0 0x00001500  //DDRSS_CTL_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C4 0x0000100E  //DDRSS_CTL_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C8 0x00000000  //DDRSS_CTL_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082CC 0x00000000  //DDRSS_CTL_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D0 0x00000001  //DDRSS_CTL_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D4 0x00000002  //DDRSS_CTL_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D8 0x00000C00  //DDRSS_CTL_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082DC 0x00001000  //DDRSS_CTL_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E0 0x00000C00  //DDRSS_CTL_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E4 0x00001000  //DDRSS_CTL_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E8 0x00000C00  //DDRSS_CTL_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082EC 0x00001000  //DDRSS_CTL_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F0 0x00000000  //DDRSS_CTL_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F4 0x00000000  //DDRSS_CTL_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F8 0x00000000  //DDRSS_CTL_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082FC 0x00000000  //DDRSS_CTL_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308300 0x00000000  //DDRSS_CTL_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308304 0x00000000  //DDRSS_CTL_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308308 0x00000000  //DDRSS_CTL_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30830C 0x00000000  //DDRSS_CTL_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308310 0x00000000  //DDRSS_CTL_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308314 0x00000000  //DDRSS_CTL_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308318 0x00000000  //DDRSS_CTL_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30831C 0x00000000  //DDRSS_CTL_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308320 0x00000000  //DDRSS_CTL_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308324 0x00000000  //DDRSS_CTL_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308328 0x00000000  //DDRSS_CTL_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30832C 0x00000000  //DDRSS_CTL_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308330 0x00041000  //DDRSS_CTL_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308334 0x00000503  //DDRSS_CTL_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308338 0x00000010  //DDRSS_CTL_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30833C 0x00000410  //DDRSS_CTL_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308340 0x00000503  //DDRSS_CTL_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308344 0x00000010  //DDRSS_CTL_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308348 0x00000410  //DDRSS_CTL_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30834C 0x00000503  //DDRSS_CTL_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308350 0x00000010  //DDRSS_CTL_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308354 0x00000410  //DDRSS_CTL_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308358 0x00000503  //DDRSS_CTL_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30835C 0x00000010  //DDRSS_CTL_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308360 0x00000410  //DDRSS_CTL_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308364 0x00000503  //DDRSS_CTL_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308368 0x00000010  //DDRSS_CTL_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30836C 0x00000410  //DDRSS_CTL_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308370 0x00000503  //DDRSS_CTL_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308374 0x00000010  //DDRSS_CTL_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308378 0x00000000  //DDRSS_CTL_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30837C 0x00000000  //DDRSS_CTL_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308380 0x00000000  //DDRSS_CTL_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308384 0x00000000  //DDRSS_CTL_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308388 0x00000000  //DDRSS_CTL_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30838C 0x00000000  //DDRSS_CTL_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308390 0x00000000  //DDRSS_CTL_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308394 0x00000000  //DDRSS_CTL_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308398 0x00000000  //DDRSS_CTL_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30839C 0x00000000  //DDRSS_CTL_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A0 0x00000000  //DDRSS_CTL_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A4 0x00000000  //DDRSS_CTL_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A8 0x00000000  //DDRSS_CTL_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083AC 0x00000000  //DDRSS_CTL_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B0 0x00001401  //DDRSS_CTL_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B4 0x00001401  //DDRSS_CTL_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B8 0x00001401  //DDRSS_CTL_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083BC 0x00001401  //DDRSS_CTL_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C0 0x00001401  //DDRSS_CTL_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C4 0x00001401  //DDRSS_CTL_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C8 0x00000493  //DDRSS_CTL_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083CC 0x00000493  //DDRSS_CTL_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D0 0x00000493  //DDRSS_CTL_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D4 0x00000493  //DDRSS_CTL_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D8 0x00000493  //DDRSS_CTL_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083DC 0x00000493  //DDRSS_CTL_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E0 0x00000000  //DDRSS_CTL_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E4 0x00000000  //DDRSS_CTL_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E8 0x00000000  //DDRSS_CTL_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083EC 0x00000000  //DDRSS_CTL_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F0 0x00000000  //DDRSS_CTL_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F4 0x00000000  //DDRSS_CTL_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F8 0x00000000  //DDRSS_CTL_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083FC 0x00000000  //DDRSS_CTL_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308400 0x00000000  //DDRSS_CTL_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308404 0x00000000  //DDRSS_CTL_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308408 0x00000000  //DDRSS_CTL_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30840C 0x00000000  //DDRSS_CTL_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308410 0x00000000  //DDRSS_CTL_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308414 0x00000000  //DDRSS_CTL_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308418 0x00000000  //DDRSS_CTL_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30841C 0x00000000  //DDRSS_CTL_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308420 0x00000000  //DDRSS_CTL_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308424 0x00000000  //DDRSS_CTL_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308428 0x00000000  //DDRSS_CTL_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30842C 0x00000000  //DDRSS_CTL_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308430 0x00000000  //DDRSS_CTL_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308434 0x00000000  //DDRSS_CTL_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308438 0x00000000  //DDRSS_CTL_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30843C 0x00000000  //DDRSS_CTL_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308440 0x00000000  //DDRSS_CTL_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308444 0x00000000  //DDRSS_CTL_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308448 0x00000000  //DDRSS_CTL_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30844C 0x00000000  //DDRSS_CTL_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308450 0x00000000  //DDRSS_CTL_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308454 0x00010000  //DDRSS_CTL_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308458 0x00000000  //DDRSS_CTL_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30845C 0x00000100  //DDRSS_CTL_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308460 0x00000000  //DDRSS_CTL_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308464 0x00000101  //DDRSS_CTL_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308468 0x00000000  //DDRSS_CTL_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30846C 0x00000000  //DDRSS_CTL_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308470 0x00000000  //DDRSS_CTL_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308474 0x00000000  //DDRSS_CTL_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308478 0x00000000  //DDRSS_CTL_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30847C 0x00000000  //DDRSS_CTL_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308480 0x00000000  //DDRSS_CTL_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308484 0x00000FFF  //DDRSS_CTL_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308488 0x0C181511  //DDRSS_CTL_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30848C 0x00000304  //DDRSS_CTL_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308490 0x00000000  //DDRSS_CTL_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308494 0x00000000  //DDRSS_CTL_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308498 0x00000000  //DDRSS_CTL_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30849C 0x00000000  //DDRSS_CTL_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A0 0x00000000  //DDRSS_CTL_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A4 0x00000000  //DDRSS_CTL_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A8 0x00000000  //DDRSS_CTL_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084AC 0x00000000  //DDRSS_CTL_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B0 0x00000000  //DDRSS_CTL_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B4 0x00000000  //DDRSS_CTL_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B8 0x00000000  //DDRSS_CTL_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084BC 0x00000000  //DDRSS_CTL_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C0 0x00000000  //DDRSS_CTL_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C4 0x00040000  //DDRSS_CTL_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C8 0x00800200  //DDRSS_CTL_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084CC 0x00000000  //DDRSS_CTL_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D0 0x02000400  //DDRSS_CTL_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D4 0x00000080  //DDRSS_CTL_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D8 0x00040000  //DDRSS_CTL_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084DC 0x00800200  //DDRSS_CTL_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E0 0x00000000  //DDRSS_CTL_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E4 0x00000000  //DDRSS_CTL_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E8 0x00000000  //DDRSS_CTL_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084EC 0x00000100  //DDRSS_CTL_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F0 0x01010000  //DDRSS_CTL_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F4 0x00000202  //DDRSS_CTL_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F8 0x0FFF0000  //DDRSS_CTL_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084FC 0x000FFF00  //DDRSS_CTL_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308500 0xFFFFFFFF  //DDRSS_CTL_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308504 0x00FFFF00  //DDRSS_CTL_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308508 0x0A000000  //DDRSS_CTL_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30850C 0x0001FFFF  //DDRSS_CTL_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308510 0x01010101  //DDRSS_CTL_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308514 0x01010101  //DDRSS_CTL_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308518 0x00000118  //DDRSS_CTL_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30851C 0x00000C01  //DDRSS_CTL_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308520 0x00000000  //DDRSS_CTL_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308524 0x00000000  //DDRSS_CTL_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308528 0x00000000  //DDRSS_CTL_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30852C 0x01000000  //DDRSS_CTL_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308530 0x00000100  //DDRSS_CTL_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308534 0x00010000  //DDRSS_CTL_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308538 0x00000000  //DDRSS_CTL_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30853C 0x00000000  //DDRSS_CTL_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308540 0x00000000  //DDRSS_CTL_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308544 0x00000000  //DDRSS_CTL_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308548 0x00000000  //DDRSS_CTL_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30854C 0x00000000  //DDRSS_CTL_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308550 0x00000000  //DDRSS_CTL_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308554 0x00000000  //DDRSS_CTL_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308558 0x00000000  //DDRSS_CTL_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30855C 0x00000000  //DDRSS_CTL_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308560 0x00000000  //DDRSS_CTL_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308564 0x00000000  //DDRSS_CTL_345_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308568 0x00000000  //DDRSS_CTL_346_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30856C 0x00000000  //DDRSS_CTL_347_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308570 0x00000000  //DDRSS_CTL_348_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308574 0x00000000  //DDRSS_CTL_349_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308578 0x00000000  //DDRSS_CTL_350_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30857C 0x00000000  //DDRSS_CTL_351_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308580 0x00000000  //DDRSS_CTL_352_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308584 0x00000000  //DDRSS_CTL_353_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308588 0x00000000  //DDRSS_CTL_354_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30858C 0x00000000  //DDRSS_CTL_355_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308590 0x00000000  //DDRSS_CTL_356_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308594 0x00000000  //DDRSS_CTL_357_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308598 0x00000000  //DDRSS_CTL_358_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30859C 0x00000000  //DDRSS_CTL_359_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A0 0x00000000  //DDRSS_CTL_360_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A4 0x00000000  //DDRSS_CTL_361_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A8 0x00000000  //DDRSS_CTL_362_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085AC 0x00000000  //DDRSS_CTL_363_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B0 0x00000000  //DDRSS_CTL_364_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B4 0xDAF890C0  //DDRSS_CTL_365_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B8 0xE3F4435A  //DDRSS_CTL_366_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085BC 0x03E7AFF0  //DDRSS_CTL_367_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C0 0x00000000  //DDRSS_CTL_368_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C4 0x00000000  //DDRSS_CTL_369_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C8 0x0E000000  //DDRSS_CTL_370_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085CC 0x060E0606  //DDRSS_CTL_371_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D0 0x06060E06  //DDRSS_CTL_372_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D4 0x00010101  //DDRSS_CTL_373_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D8 0x02000000  //DDRSS_CTL_374_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085DC 0x00020101  //DDRSS_CTL_375_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E0 0x00000000  //DDRSS_CTL_376_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E4 0x02020200  //DDRSS_CTL_377_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E8 0x02020202  //DDRSS_CTL_378_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085EC 0x02020202  //DDRSS_CTL_379_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F0 0x02020202  //DDRSS_CTL_380_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F4 0x00000000  //DDRSS_CTL_381_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F8 0x00000000  //DDRSS_CTL_382_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085FC 0x04000100  //DDRSS_CTL_383_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308600 0x1E000304  //DDRSS_CTL_384_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308604 0x000030C0  //DDRSS_CTL_385_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308608 0x00000200  //DDRSS_CTL_386_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30860C 0x00000200  //DDRSS_CTL_387_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308610 0x00000200  //DDRSS_CTL_388_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308614 0x00000200  //DDRSS_CTL_389_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308618 0x0000DB60  //DDRSS_CTL_390_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30861C 0x0001E780  //DDRSS_CTL_391_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308620 0x090A0302  //DDRSS_CTL_392_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308624 0x001E0B0C  //DDRSS_CTL_393_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308628 0x000030C0  //DDRSS_CTL_394_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30862C 0x00000200  //DDRSS_CTL_395_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308630 0x00000200  //DDRSS_CTL_396_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308634 0x00000200  //DDRSS_CTL_397_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308638 0x00000200  //DDRSS_CTL_398_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30863C 0x0000DB60  //DDRSS_CTL_399_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308640 0x0001E780  //DDRSS_CTL_400_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308644 0x090A0302  //DDRSS_CTL_401_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308648 0x001E0B0C  //DDRSS_CTL_402_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30864C 0x000030C0  //DDRSS_CTL_403_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308650 0x00000200  //DDRSS_CTL_404_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308654 0x00000200  //DDRSS_CTL_405_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308658 0x00000200  //DDRSS_CTL_406_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30865C 0x00000200  //DDRSS_CTL_407_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308660 0x0000DB60  //DDRSS_CTL_408_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308664 0x0001E780  //DDRSS_CTL_409_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308668 0x090A0302  //DDRSS_CTL_410_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30866C 0x00000B0C  //DDRSS_CTL_411_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308670 0x00000000  //DDRSS_CTL_412_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308674 0x0302000A  //DDRSS_CTL_413_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308678 0x01000500  //DDRSS_CTL_414_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30867C 0x01010001  //DDRSS_CTL_415_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308680 0x00010001  //DDRSS_CTL_416_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308684 0x01010001  //DDRSS_CTL_417_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308688 0x02010000  //DDRSS_CTL_418_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30868C 0x00000200  //DDRSS_CTL_419_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308690 0x02000201  //DDRSS_CTL_420_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308694 0x00000000  //DDRSS_CTL_421_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308698 0x00202020  //DDRSS_CTL_422_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A000 0x00000A01  //DDRSS_PI_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A004 0xAE8D79E2  //DDRSS_PI_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A008 0x0714B570  //DDRSS_PI_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A00C 0x01011387  //DDRSS_PI_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A010 0x00000001  //DDRSS_PI_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A014 0x00010064  //DDRSS_PI_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A018 0x00000000  //DDRSS_PI_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A01C 0x00000000  //DDRSS_PI_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A020 0x00000000  //DDRSS_PI_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A024 0x00000003  //DDRSS_PI_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A028 0x0000000F  //DDRSS_PI_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A02C 0x00000000  //DDRSS_PI_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A030 0x00000000  //DDRSS_PI_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A034 0x00010001  //DDRSS_PI_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A038 0x00000000  //DDRSS_PI_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A03C 0x00010001  //DDRSS_PI_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A040 0x00000005  //DDRSS_PI_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A044 0x00010000  //DDRSS_PI_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A048 0x00000000  //DDRSS_PI_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A04C 0x00000000  //DDRSS_PI_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A050 0x00000000  //DDRSS_PI_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A054 0x00000000  //DDRSS_PI_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A058 0x00000000  //DDRSS_PI_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A05C 0x00000000  //DDRSS_PI_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A060 0x280D0001  //DDRSS_PI_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A064 0x00000000  //DDRSS_PI_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A068 0x00010000  //DDRSS_PI_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A06C 0x00003200  //DDRSS_PI_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A070 0x00000000  //DDRSS_PI_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A074 0x00000000  //DDRSS_PI_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A078 0x00060602  //DDRSS_PI_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A07C 0x00000000  //DDRSS_PI_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A080 0x00000000  //DDRSS_PI_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A084 0x00000000  //DDRSS_PI_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A088 0x00000001  //DDRSS_PI_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A08C 0x00000055  //DDRSS_PI_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A090 0x000000AA  //DDRSS_PI_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A094 0x000000AD  //DDRSS_PI_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A098 0x00000052  //DDRSS_PI_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A09C 0x0000006A  //DDRSS_PI_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A0 0x00000095  //DDRSS_PI_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A4 0x00000095  //DDRSS_PI_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A8 0x000000AD  //DDRSS_PI_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0AC 0x00000000  //DDRSS_PI_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B0 0x00000000  //DDRSS_PI_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B4 0x00010100  //DDRSS_PI_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B8 0x00000014  //DDRSS_PI_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0BC 0x000007D0  //DDRSS_PI_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C0 0x00000300  //DDRSS_PI_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C4 0x00000000  //DDRSS_PI_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C8 0x00000000  //DDRSS_PI_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0CC 0x01000000  //DDRSS_PI_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D0 0x00010101  //DDRSS_PI_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D4 0x01000B09  //DDRSS_PI_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D8 0x00000000  //DDRSS_PI_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0DC 0x00010000  //DDRSS_PI_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E0 0x00000000  //DDRSS_PI_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E4 0x00000000  //DDRSS_PI_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E8 0x00000000  //DDRSS_PI_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0EC 0x00000000  //DDRSS_PI_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F0 0x00001400  //DDRSS_PI_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F4 0x00000000  //DDRSS_PI_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F8 0x01000000  //DDRSS_PI_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0FC 0x00000404  //DDRSS_PI_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A100 0x00000001  //DDRSS_PI_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A104 0x0001010E  //DDRSS_PI_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A108 0x02040100  //DDRSS_PI_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A10C 0x00010000  //DDRSS_PI_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A110 0x00000034  //DDRSS_PI_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A114 0x00000000  //DDRSS_PI_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A118 0x00000000  //DDRSS_PI_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A11C 0x00000000  //DDRSS_PI_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A120 0x00000000  //DDRSS_PI_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A124 0x00000000  //DDRSS_PI_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A128 0x00000000  //DDRSS_PI_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A12C 0x00000005  //DDRSS_PI_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A130 0x01000000  //DDRSS_PI_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A134 0x04020100  //DDRSS_PI_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A138 0x00020000  //DDRSS_PI_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A13C 0x00010002  //DDRSS_PI_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A140 0x00000001  //DDRSS_PI_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A144 0x00020001  //DDRSS_PI_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A148 0x00020002  //DDRSS_PI_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A14C 0x29C02000  //DDRSS_PI_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A150 0x00000000  //DDRSS_PI_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A154 0x00000000  //DDRSS_PI_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A158 0x00000000  //DDRSS_PI_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A15C 0x00000000  //DDRSS_PI_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A160 0x00000000  //DDRSS_PI_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A164 0x00000000  //DDRSS_PI_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A168 0x00000000  //DDRSS_PI_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A16C 0x00000300  //DDRSS_PI_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A170 0x0A090B0C  //DDRSS_PI_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A174 0x04060708  //DDRSS_PI_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A178 0x01000005  //DDRSS_PI_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A17C 0x00000800  //DDRSS_PI_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A180 0x00000000  //DDRSS_PI_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A184 0x00010008  //DDRSS_PI_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A188 0x00000000  //DDRSS_PI_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A18C 0x0000AA00  //DDRSS_PI_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A190 0x00000000  //DDRSS_PI_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A194 0x00010000  //DDRSS_PI_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A198 0x00000000  //DDRSS_PI_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A19C 0x00000000  //DDRSS_PI_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A0 0x00000000  //DDRSS_PI_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A4 0x00000000  //DDRSS_PI_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A8 0x00000000  //DDRSS_PI_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1AC 0x00000000  //DDRSS_PI_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B0 0x00000000  //DDRSS_PI_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B4 0x00000000  //DDRSS_PI_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B8 0x00000000  //DDRSS_PI_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1BC 0x00000000  //DDRSS_PI_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C0 0x00000000  //DDRSS_PI_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C4 0x00000000  //DDRSS_PI_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C8 0x00000000  //DDRSS_PI_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1CC 0x00000000  //DDRSS_PI_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D0 0x00000000  //DDRSS_PI_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D4 0x00000000  //DDRSS_PI_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D8 0x00000000  //DDRSS_PI_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1DC 0x00000000  //DDRSS_PI_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E0 0x00000000  //DDRSS_PI_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E4 0x00000000  //DDRSS_PI_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E8 0x00000000  //DDRSS_PI_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1EC 0x00000000  //DDRSS_PI_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F0 0x00000008  //DDRSS_PI_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F4 0x00000000  //DDRSS_PI_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F8 0x00000000  //DDRSS_PI_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1FC 0x00000000  //DDRSS_PI_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A200 0x00000000  //DDRSS_PI_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A204 0x00000000  //DDRSS_PI_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A208 0x00000000  //DDRSS_PI_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A20C 0x00000000  //DDRSS_PI_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A210 0x00000000  //DDRSS_PI_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A214 0x00010100  //DDRSS_PI_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A218 0x00000000  //DDRSS_PI_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A21C 0x00000000  //DDRSS_PI_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A220 0x00027100  //DDRSS_PI_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A224 0x00061A80  //DDRSS_PI_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A228 0x00000100  //DDRSS_PI_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A22C 0x00000000  //DDRSS_PI_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A230 0x00000000  //DDRSS_PI_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A234 0x00000000  //DDRSS_PI_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A238 0x00000000  //DDRSS_PI_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A23C 0x00000000  //DDRSS_PI_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A240 0x01000000  //DDRSS_PI_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A244 0xC1010003  //DDRSS_PI_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A248 0x02000101  //DDRSS_PI_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A24C 0x01030101  //DDRSS_PI_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A250 0x00010400  //DDRSS_PI_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A254 0x06000105  //DDRSS_PI_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A258 0x01070001  //DDRSS_PI_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A25C 0x00000000  //DDRSS_PI_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A260 0x00000000  //DDRSS_PI_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A264 0x00000001  //DDRSS_PI_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A268 0x00010000  //DDRSS_PI_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A26C 0x00000000  //DDRSS_PI_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A270 0x00000000  //DDRSS_PI_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A274 0x00000000  //DDRSS_PI_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A278 0x00000000  //DDRSS_PI_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A27C 0x00010000  //DDRSS_PI_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A280 0x00000004  //DDRSS_PI_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A284 0x00000000  //DDRSS_PI_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A288 0x00000000  //DDRSS_PI_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A28C 0x00000000  //DDRSS_PI_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A290 0x00007800  //DDRSS_PI_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A294 0x00780078  //DDRSS_PI_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A298 0x00141414  //DDRSS_PI_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A29C 0x00000037  //DDRSS_PI_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A0 0x00000037  //DDRSS_PI_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A4 0x00040037  //DDRSS_PI_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A8 0x04000400  //DDRSS_PI_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2AC 0x6804000B  //DDRSS_PI_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B0 0x04000B16  //DDRSS_PI_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B4 0x000B1668  //DDRSS_PI_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B8 0x00166804  //DDRSS_PI_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2BC 0x000000D0  //DDRSS_PI_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C0 0x00001860  //DDRSS_PI_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C4 0x000000D0  //DDRSS_PI_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C8 0x00001860  //DDRSS_PI_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2CC 0x000000D0  //DDRSS_PI_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D0 0x04001860  //DDRSS_PI_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D4 0x01010404  //DDRSS_PI_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D8 0x00001901  //DDRSS_PI_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2DC 0x00190019  //DDRSS_PI_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E0 0x010E010E  //DDRSS_PI_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E4 0x0000010E  //DDRSS_PI_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E8 0x00000000  //DDRSS_PI_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2EC 0x00000000  //DDRSS_PI_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F0 0x01010000  //DDRSS_PI_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F4 0x01010101  //DDRSS_PI_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F8 0x00181818  //DDRSS_PI_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2FC 0x00000000  //DDRSS_PI_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A300 0x00000000  //DDRSS_PI_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A304 0x0A000000  //DDRSS_PI_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A308 0x0C0C0A0A  //DDRSS_PI_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A30C 0x0303030C  //DDRSS_PI_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A310 0x00000000  //DDRSS_PI_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A314 0x00000000  //DDRSS_PI_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A318 0x00000000  //DDRSS_PI_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A31C 0x00000000  //DDRSS_PI_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A320 0x00000000  //DDRSS_PI_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A324 0x00000000  //DDRSS_PI_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A328 0x00000000  //DDRSS_PI_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A32C 0x00000000  //DDRSS_PI_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A330 0x00000000  //DDRSS_PI_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A334 0x00000000  //DDRSS_PI_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A338 0x00000000  //DDRSS_PI_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A33C 0x00000000  //DDRSS_PI_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A340 0x00000000  //DDRSS_PI_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A344 0x0D090000  //DDRSS_PI_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A348 0x0D09000D  //DDRSS_PI_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A34C 0x0D09000D  //DDRSS_PI_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A350 0x0000000D  //DDRSS_PI_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A354 0x00000000  //DDRSS_PI_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A358 0x00000000  //DDRSS_PI_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A35C 0x00000000  //DDRSS_PI_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A360 0x00000000  //DDRSS_PI_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A364 0x16000000  //DDRSS_PI_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A368 0x001600C8  //DDRSS_PI_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A36C 0x001600C8  //DDRSS_PI_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A370 0x010100C8  //DDRSS_PI_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A374 0x00001D01  //DDRSS_PI_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A378 0x1F0F004E  //DDRSS_PI_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A37C 0x02000001  //DDRSS_PI_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A380 0x001D0A0A  //DDRSS_PI_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A384 0x1F0F004E  //DDRSS_PI_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A388 0x02000001  //DDRSS_PI_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A38C 0x001D0A0A  //DDRSS_PI_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A390 0x1F0F004E  //DDRSS_PI_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A394 0x02000001  //DDRSS_PI_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A398 0x00010A0A  //DDRSS_PI_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A39C 0x0C0B0700  //DDRSS_PI_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A0 0x000D0605  //DDRSS_PI_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A4 0x0000C570  //DDRSS_PI_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A8 0x0000001D  //DDRSS_PI_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3AC 0x180A0800  //DDRSS_PI_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B0 0x0B071C1C  //DDRSS_PI_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B4 0x0D06050C  //DDRSS_PI_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B8 0x0000C570  //DDRSS_PI_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3BC 0x0000001D  //DDRSS_PI_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C0 0x180A0800  //DDRSS_PI_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C4 0x0B071C1C  //DDRSS_PI_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C8 0x0D06050C  //DDRSS_PI_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3CC 0x0000C570  //DDRSS_PI_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D0 0x0000001D  //DDRSS_PI_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D4 0x180A0800  //DDRSS_PI_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D8 0x00001C1C  //DDRSS_PI_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3DC 0x000030C0  //DDRSS_PI_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E0 0x0001E780  //DDRSS_PI_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E4 0x000030C0  //DDRSS_PI_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E8 0x0001E780  //DDRSS_PI_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3EC 0x000030C0  //DDRSS_PI_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F0 0x0001E780  //DDRSS_PI_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F4 0x02550255  //DDRSS_PI_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F8 0x03030255  //DDRSS_PI_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3FC 0x00025503  //DDRSS_PI_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A400 0x02550255  //DDRSS_PI_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A404 0x0C080C08  //DDRSS_PI_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A408 0x00000C08  //DDRSS_PI_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A40C 0x00089070  //DDRSS_PI_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A410 0x00000000  //DDRSS_PI_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A414 0x00000000  //DDRSS_PI_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A418 0x00000000  //DDRSS_PI_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A41C 0x000000D8  //DDRSS_PI_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A420 0x00089070  //DDRSS_PI_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A424 0x00000000  //DDRSS_PI_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A428 0x00000000  //DDRSS_PI_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A42C 0x00000000  //DDRSS_PI_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A430 0x000000D8  //DDRSS_PI_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A434 0x00089070  //DDRSS_PI_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A438 0x00000000  //DDRSS_PI_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A43C 0x00000000  //DDRSS_PI_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A440 0x00000000  //DDRSS_PI_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A444 0x020000D8  //DDRSS_PI_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A448 0x00000080  //DDRSS_PI_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A44C 0x00020000  //DDRSS_PI_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A450 0x00000080  //DDRSS_PI_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A454 0x00020000  //DDRSS_PI_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A458 0x00000080  //DDRSS_PI_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A45C 0x00000000  //DDRSS_PI_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A460 0x00000000  //DDRSS_PI_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A464 0x00040404  //DDRSS_PI_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A468 0x00000000  //DDRSS_PI_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A46C 0x02010102  //DDRSS_PI_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A470 0x67676767  //DDRSS_PI_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A474 0x00000202  //DDRSS_PI_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A478 0x00000000  //DDRSS_PI_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A47C 0x00000000  //DDRSS_PI_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A480 0x00000000  //DDRSS_PI_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A484 0x00000000  //DDRSS_PI_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A488 0x00000000  //DDRSS_PI_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A48C 0x0D100F00  //DDRSS_PI_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A490 0x0003020E  //DDRSS_PI_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A494 0x00000001  //DDRSS_PI_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A498 0x01000000  //DDRSS_PI_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A49C 0x00020201  //DDRSS_PI_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A0 0x00000000  //DDRSS_PI_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A4 0x00000410  //DDRSS_PI_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A8 0x00000503  //DDRSS_PI_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4AC 0x00000010  //DDRSS_PI_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B0 0x00000000  //DDRSS_PI_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B4 0x00000000  //DDRSS_PI_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B8 0x00001401  //DDRSS_PI_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4BC 0x00000493  //DDRSS_PI_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C0 0x00000000  //DDRSS_PI_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C4 0x00000410  //DDRSS_PI_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C8 0x00000503  //DDRSS_PI_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4CC 0x00000010  //DDRSS_PI_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D0 0x00000000  //DDRSS_PI_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D4 0x00000000  //DDRSS_PI_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D8 0x00001401  //DDRSS_PI_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4DC 0x00000493  //DDRSS_PI_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E0 0x00000000  //DDRSS_PI_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E4 0x00000410  //DDRSS_PI_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E8 0x00000503  //DDRSS_PI_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4EC 0x00000010  //DDRSS_PI_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F0 0x00000000  //DDRSS_PI_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F4 0x00000000  //DDRSS_PI_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F8 0x00001401  //DDRSS_PI_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4FC 0x00000493  //DDRSS_PI_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A500 0x00000000  //DDRSS_PI_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A504 0x00000410  //DDRSS_PI_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A508 0x00000503  //DDRSS_PI_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A50C 0x00000010  //DDRSS_PI_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A510 0x00000000  //DDRSS_PI_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A514 0x00000000  //DDRSS_PI_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A518 0x00001401  //DDRSS_PI_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A51C 0x00000493  //DDRSS_PI_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A520 0x00000000  //DDRSS_PI_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A524 0x00000410  //DDRSS_PI_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A528 0x00000503  //DDRSS_PI_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A52C 0x00000010  //DDRSS_PI_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A530 0x00000000  //DDRSS_PI_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A534 0x00000000  //DDRSS_PI_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A538 0x00001401  //DDRSS_PI_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A53C 0x00000493  //DDRSS_PI_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A540 0x00000000  //DDRSS_PI_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A544 0x00000410  //DDRSS_PI_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A548 0x00000503  //DDRSS_PI_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A54C 0x00000010  //DDRSS_PI_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A550 0x00000000  //DDRSS_PI_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A554 0x00000000  //DDRSS_PI_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A558 0x00001401  //DDRSS_PI_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A55C 0x00000493  //DDRSS_PI_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A560 0x00000000  //DDRSS_PI_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C000 0x04C00000  //DDRSS_PHY_0_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C004 0x00000000  //DDRSS_PHY_1_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C008 0x00000200  //DDRSS_PHY_2_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C00C 0x00000000  //DDRSS_PHY_3_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C010 0x00000000  //DDRSS_PHY_4_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C014 0x00000000  //DDRSS_PHY_5_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C018 0x00000000  //DDRSS_PHY_6_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C01C 0x00000000  //DDRSS_PHY_7_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C020 0x00000001  //DDRSS_PHY_8_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C024 0x00000000  //DDRSS_PHY_9_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C028 0x0A0C0000  //DDRSS_PHY_10_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C02C 0x010101FF  //DDRSS_PHY_11_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C030 0x00010000  //DDRSS_PHY_12_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C034 0x00C04004  //DDRSS_PHY_13_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C038 0x00CC0008  //DDRSS_PHY_14_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C03C 0x00660201  //DDRSS_PHY_15_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C040 0x00000000  //DDRSS_PHY_16_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C044 0x00000000  //DDRSS_PHY_17_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C048 0x00000000  //DDRSS_PHY_18_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C04C 0x0000AAAA  //DDRSS_PHY_19_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C050 0x00005555  //DDRSS_PHY_20_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C054 0x0000B5B5  //DDRSS_PHY_21_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C058 0x00004A4A  //DDRSS_PHY_22_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C05C 0x00005656  //DDRSS_PHY_23_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C060 0x0000A9A9  //DDRSS_PHY_24_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C064 0x0000B7B7  //DDRSS_PHY_25_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C068 0x00004848  //DDRSS_PHY_26_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C06C 0x00000000  //DDRSS_PHY_27_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C070 0x00000000  //DDRSS_PHY_28_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C074 0x08000000  //DDRSS_PHY_29_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C078 0x0F000008  //DDRSS_PHY_30_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C07C 0x00000F0F  //DDRSS_PHY_31_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C080 0x00E4E400  //DDRSS_PHY_32_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C084 0x00070820  //DDRSS_PHY_33_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C088 0x000C0020  //DDRSS_PHY_34_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C08C 0x00062000  //DDRSS_PHY_35_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C090 0x00000000  //DDRSS_PHY_36_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C094 0x55555555  //DDRSS_PHY_37_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C098 0xAAAAAAAA  //DDRSS_PHY_38_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C09C 0x55555555  //DDRSS_PHY_39_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A0 0xAAAAAAAA  //DDRSS_PHY_40_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A4 0x00005555  //DDRSS_PHY_41_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A8 0x01000100  //DDRSS_PHY_42_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0AC 0x00800180  //DDRSS_PHY_43_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B0 0x00000000  //DDRSS_PHY_44_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B4 0x00100000  //DDRSS_PHY_45_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B8 0x00000000  //DDRSS_PHY_46_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0BC 0x05070010  //DDRSS_PHY_47_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C0 0x0000000C  //DDRSS_PHY_48_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C4 0x00000000  //DDRSS_PHY_49_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C8 0x003C0024  //DDRSS_PHY_50_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0CC 0x00000FFF  //DDRSS_PHY_51_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D0 0x00000000  //DDRSS_PHY_52_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D4 0x02B802AC  //DDRSS_PHY_53_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D8 0x00000030  //DDRSS_PHY_54_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0DC 0x0114003C  //DDRSS_PHY_55_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E0 0x00000000  //DDRSS_PHY_56_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E4 0x0C000000  //DDRSS_PHY_57_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E8 0x07FF0000  //DDRSS_PHY_58_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0EC 0x00000000  //DDRSS_PHY_59_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F0 0x00000000  //DDRSS_PHY_60_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F4 0x00000000  //DDRSS_PHY_61_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F8 0x00000000  //DDRSS_PHY_62_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0FC 0x00000000  //DDRSS_PHY_63_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C100 0x00000000  //DDRSS_PHY_64_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C104 0x00000004  //DDRSS_PHY_65_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C108 0x00000000  //DDRSS_PHY_66_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C10C 0x00000000  //DDRSS_PHY_67_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C110 0x00000000  //DDRSS_PHY_68_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C114 0x00000000  //DDRSS_PHY_69_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C118 0x00000000  //DDRSS_PHY_70_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C11C 0x00000000  //DDRSS_PHY_71_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C120 0x041F07FF  //DDRSS_PHY_72_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C124 0x00000000  //DDRSS_PHY_73_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C128 0x01CCB001  //DDRSS_PHY_74_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C12C 0x2000CCB0  //DDRSS_PHY_75_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C130 0x20000140  //DDRSS_PHY_76_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C134 0x07FF0200  //DDRSS_PHY_77_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C138 0x0000DD01  //DDRSS_PHY_78_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C13C 0x10100303  //DDRSS_PHY_79_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C140 0x10101010  //DDRSS_PHY_80_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C144 0x10101010  //DDRSS_PHY_81_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C148 0x00021010  //DDRSS_PHY_82_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C14C 0x00100010  //DDRSS_PHY_83_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C150 0x00100010  //DDRSS_PHY_84_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C154 0x00100010  //DDRSS_PHY_85_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C158 0x00100010  //DDRSS_PHY_86_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C15C 0x02020010  //DDRSS_PHY_87_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C160 0x51515041  //DDRSS_PHY_88_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C164 0x31804000  //DDRSS_PHY_89_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C168 0x04C00340  //DDRSS_PHY_90_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C16C 0x01008080  //DDRSS_PHY_91_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C170 0x04050001  //DDRSS_PHY_92_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C174 0x00000504  //DDRSS_PHY_93_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C178 0x42100010  //DDRSS_PHY_94_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C17C 0x010C053E  //DDRSS_PHY_95_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C180 0x000F0C14  //DDRSS_PHY_96_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C184 0x01000140  //DDRSS_PHY_97_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C188 0x007A0120  //DDRSS_PHY_98_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C18C 0x00000C00  //DDRSS_PHY_99_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C190 0x000001CC  //DDRSS_PHY_100_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C194 0x20100200  //DDRSS_PHY_101_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C198 0x00000005  //DDRSS_PHY_102_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C19C 0x76543210  //DDRSS_PHY_103_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A0 0x00000008  //DDRSS_PHY_104_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A4 0x02800280  //DDRSS_PHY_105_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A8 0x02800280  //DDRSS_PHY_106_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1AC 0x02800280  //DDRSS_PHY_107_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B0 0x02800280  //DDRSS_PHY_108_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B4 0x00300280  //DDRSS_PHY_109_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B8 0x0000A800  //DDRSS_PHY_110_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1BC 0x00A800AE  //DDRSS_PHY_111_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C0 0x00A800B4  //DDRSS_PHY_112_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C4 0x00B400AE  //DDRSS_PHY_113_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C8 0x00B400BA  //DDRSS_PHY_114_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1CC 0x00A800B4  //DDRSS_PHY_115_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D0 0x00A800AE  //DDRSS_PHY_116_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D4 0x00A800AE  //DDRSS_PHY_117_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D8 0x00A800AE  //DDRSS_PHY_118_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1DC 0x01B200AE  //DDRSS_PHY_119_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E0 0x01000000  //DDRSS_PHY_120_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E4 0x00000000  //DDRSS_PHY_121_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E8 0x00000000  //DDRSS_PHY_122_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1EC 0x00080200  //DDRSS_PHY_123_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F0 0x00000000  //DDRSS_PHY_124_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F4 0x00000000  //DDRSS_PHY_125_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C400 0x04C00000  //DDRSS_PHY_256_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C404 0x00000000  //DDRSS_PHY_257_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C408 0x00000200  //DDRSS_PHY_258_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C40C 0x00000000  //DDRSS_PHY_259_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C410 0x00000000  //DDRSS_PHY_260_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C414 0x00000000  //DDRSS_PHY_261_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C418 0x00000000  //DDRSS_PHY_262_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C41C 0x00000000  //DDRSS_PHY_263_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C420 0x00000001  //DDRSS_PHY_264_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C424 0x00000000  //DDRSS_PHY_265_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C428 0x0A0C0000  //DDRSS_PHY_266_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C42C 0x010101FF  //DDRSS_PHY_267_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C430 0x00010000  //DDRSS_PHY_268_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C434 0x00C04004  //DDRSS_PHY_269_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C438 0x00CC0008  //DDRSS_PHY_270_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C43C 0x00660201  //DDRSS_PHY_271_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C440 0x00000000  //DDRSS_PHY_272_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C444 0x00000000  //DDRSS_PHY_273_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C448 0x00000000  //DDRSS_PHY_274_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C44C 0x0000AAAA  //DDRSS_PHY_275_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C450 0x00005555  //DDRSS_PHY_276_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C454 0x0000B5B5  //DDRSS_PHY_277_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C458 0x00004A4A  //DDRSS_PHY_278_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C45C 0x00005656  //DDRSS_PHY_279_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C460 0x0000A9A9  //DDRSS_PHY_280_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C464 0x0000B7B7  //DDRSS_PHY_281_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C468 0x00004848  //DDRSS_PHY_282_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C46C 0x00000000  //DDRSS_PHY_283_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C470 0x00000000  //DDRSS_PHY_284_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C474 0x08000000  //DDRSS_PHY_285_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C478 0x0F000008  //DDRSS_PHY_286_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C47C 0x00000F0F  //DDRSS_PHY_287_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C480 0x00E4E400  //DDRSS_PHY_288_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C484 0x00070820  //DDRSS_PHY_289_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C488 0x000C0020  //DDRSS_PHY_290_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C48C 0x00062000  //DDRSS_PHY_291_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C490 0x00000000  //DDRSS_PHY_292_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C494 0x55555555  //DDRSS_PHY_293_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C498 0xAAAAAAAA  //DDRSS_PHY_294_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C49C 0x55555555  //DDRSS_PHY_295_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A0 0xAAAAAAAA  //DDRSS_PHY_296_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A4 0x00005555  //DDRSS_PHY_297_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A8 0x01000100  //DDRSS_PHY_298_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4AC 0x00800180  //DDRSS_PHY_299_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B0 0x00000000  //DDRSS_PHY_300_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B4 0x00100000  //DDRSS_PHY_301_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B8 0x00000000  //DDRSS_PHY_302_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4BC 0x14070010  //DDRSS_PHY_303_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C0 0x00000014  //DDRSS_PHY_304_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C4 0x00010600  //DDRSS_PHY_305_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C8 0x0048003C  //DDRSS_PHY_306_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4CC 0x00000FFF  //DDRSS_PHY_307_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D0 0x00000000  //DDRSS_PHY_308_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D4 0x02AC02A0  //DDRSS_PHY_309_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D8 0x00000030  //DDRSS_PHY_310_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4DC 0x01200048  //DDRSS_PHY_311_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E0 0x00000000  //DDRSS_PHY_312_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E4 0x0C000000  //DDRSS_PHY_313_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E8 0x07FF0000  //DDRSS_PHY_314_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4EC 0x00000000  //DDRSS_PHY_315_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F0 0x00000000  //DDRSS_PHY_316_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F4 0x00000000  //DDRSS_PHY_317_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F8 0x00000000  //DDRSS_PHY_318_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4FC 0x00000000  //DDRSS_PHY_319_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C500 0x00000000  //DDRSS_PHY_320_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C504 0x00000004  //DDRSS_PHY_321_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C508 0x00000000  //DDRSS_PHY_322_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C50C 0x00000000  //DDRSS_PHY_323_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C510 0x00000000  //DDRSS_PHY_324_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C514 0x00000000  //DDRSS_PHY_325_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C518 0x00000000  //DDRSS_PHY_326_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C51C 0x00000000  //DDRSS_PHY_327_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C520 0x041F07FF  //DDRSS_PHY_328_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C524 0x00000000  //DDRSS_PHY_329_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C528 0x01CCB001  //DDRSS_PHY_330_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C52C 0x2000CCB0  //DDRSS_PHY_331_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C530 0x20000140  //DDRSS_PHY_332_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C534 0x07FF0200  //DDRSS_PHY_333_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C538 0x0000DD01  //DDRSS_PHY_334_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C53C 0x10100303  //DDRSS_PHY_335_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C540 0x10101010  //DDRSS_PHY_336_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C544 0x10101010  //DDRSS_PHY_337_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C548 0x00021010  //DDRSS_PHY_338_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C54C 0x00100010  //DDRSS_PHY_339_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C550 0x00100010  //DDRSS_PHY_340_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C554 0x00100010  //DDRSS_PHY_341_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C558 0x00100010  //DDRSS_PHY_342_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C55C 0x02020010  //DDRSS_PHY_343_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C560 0x51515041  //DDRSS_PHY_344_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C564 0x31804000  //DDRSS_PHY_345_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C568 0x04C00340  //DDRSS_PHY_346_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C56C 0x01008080  //DDRSS_PHY_347_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C570 0x04050001  //DDRSS_PHY_348_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C574 0x00000504  //DDRSS_PHY_349_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C578 0x42100010  //DDRSS_PHY_350_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C57C 0x010C053E  //DDRSS_PHY_351_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C580 0x000F0C14  //DDRSS_PHY_352_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C584 0x01000140  //DDRSS_PHY_353_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C588 0x007A0120  //DDRSS_PHY_354_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C58C 0x00000C00  //DDRSS_PHY_355_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C590 0x000001CC  //DDRSS_PHY_356_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C594 0x20100200  //DDRSS_PHY_357_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C598 0x00000005  //DDRSS_PHY_358_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C59C 0x76543210  //DDRSS_PHY_359_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A0 0x00000008  //DDRSS_PHY_360_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A4 0x02800280  //DDRSS_PHY_361_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A8 0x02800280  //DDRSS_PHY_362_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5AC 0x02800280  //DDRSS_PHY_363_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B0 0x02800280  //DDRSS_PHY_364_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B4 0x00420280  //DDRSS_PHY_365_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B8 0x0000B400  //DDRSS_PHY_366_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5BC 0x00A800B4  //DDRSS_PHY_367_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C0 0x00A800AE  //DDRSS_PHY_368_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C4 0x00B400A8  //DDRSS_PHY_369_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C8 0x00B400B4  //DDRSS_PHY_370_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5CC 0x00B400B4  //DDRSS_PHY_371_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D0 0x00B400B4  //DDRSS_PHY_372_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D4 0x00AE00B4  //DDRSS_PHY_373_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D8 0x00B400AE  //DDRSS_PHY_374_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5DC 0x01A600B4  //DDRSS_PHY_375_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E0 0x01000000  //DDRSS_PHY_376_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E4 0x00000000  //DDRSS_PHY_377_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E8 0x00000000  //DDRSS_PHY_378_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5EC 0x00080200  //DDRSS_PHY_379_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F0 0x00000000  //DDRSS_PHY_380_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F4 0x00000000  //DDRSS_PHY_381_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C800 0x00000100  //DDRSS_PHY_512_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C804 0x00001000  //DDRSS_PHY_513_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C808 0x00070000  //DDRSS_PHY_514_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C80C 0x00000000  //DDRSS_PHY_515_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C810 0x00000000  //DDRSS_PHY_516_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C814 0x00000100  //DDRSS_PHY_517_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C818 0x00000000  //DDRSS_PHY_518_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C81C 0x00000000  //DDRSS_PHY_519_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C820 0x00000000  //DDRSS_PHY_520_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C824 0x00000000  //DDRSS_PHY_521_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C828 0x00000000  //DDRSS_PHY_522_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C82C 0x00000000  //DDRSS_PHY_523_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C830 0x00000000  //DDRSS_PHY_524_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C834 0x00DCBA98  //DDRSS_PHY_525_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C838 0x00000000  //DDRSS_PHY_526_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C83C 0x00000000  //DDRSS_PHY_527_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C840 0x00000000  //DDRSS_PHY_528_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C844 0x00000000  //DDRSS_PHY_529_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C848 0x00000000  //DDRSS_PHY_530_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C84C 0x00000100  //DDRSS_PHY_531_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C850 0x00000000  //DDRSS_PHY_532_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C854 0x00000000  //DDRSS_PHY_533_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C858 0x00000000  //DDRSS_PHY_534_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C85C 0x00000000  //DDRSS_PHY_535_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C860 0x00000000  //DDRSS_PHY_536_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C864 0x00000000  //DDRSS_PHY_537_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C868 0x00000000  //DDRSS_PHY_538_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C86C 0x00000000  //DDRSS_PHY_539_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C870 0x0A418820  //DDRSS_PHY_540_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C874 0x103F0000  //DDRSS_PHY_541_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C878 0x000F0100  //DDRSS_PHY_542_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C87C 0x0000000F  //DDRSS_PHY_543_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C880 0x020002FF  //DDRSS_PHY_544_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C884 0x00030000  //DDRSS_PHY_545_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C888 0x00000300  //DDRSS_PHY_546_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C88C 0x00000300  //DDRSS_PHY_547_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C890 0x00000300  //DDRSS_PHY_548_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C894 0x00000300  //DDRSS_PHY_549_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C898 0x00000300  //DDRSS_PHY_550_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C89C 0x42080010  //DDRSS_PHY_551_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A0 0x0000003E  //DDRSS_PHY_552_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A4 0x00000000  //DDRSS_PHY_553_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A8 0x00000000  //DDRSS_PHY_554_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC00 0x00000100  //DDRSS_PHY_768_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC04 0x00001000  //DDRSS_PHY_769_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC08 0x00070000  //DDRSS_PHY_770_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC0C 0x00000000  //DDRSS_PHY_771_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC10 0x00000000  //DDRSS_PHY_772_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC14 0x00000100  //DDRSS_PHY_773_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC18 0x00000000  //DDRSS_PHY_774_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC1C 0x00000000  //DDRSS_PHY_775_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC20 0x00000000  //DDRSS_PHY_776_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC24 0x00000000  //DDRSS_PHY_777_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC28 0x00000000  //DDRSS_PHY_778_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC2C 0x00000000  //DDRSS_PHY_779_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC30 0x00000000  //DDRSS_PHY_780_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC34 0x00DCBA98  //DDRSS_PHY_781_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC38 0x00000000  //DDRSS_PHY_782_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC3C 0x00000000  //DDRSS_PHY_783_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC40 0x00000000  //DDRSS_PHY_784_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC44 0x00000000  //DDRSS_PHY_785_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC48 0x00000000  //DDRSS_PHY_786_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC4C 0x00000100  //DDRSS_PHY_787_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC50 0x00000000  //DDRSS_PHY_788_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC54 0x00000000  //DDRSS_PHY_789_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC58 0x00000000  //DDRSS_PHY_790_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC5C 0x00000000  //DDRSS_PHY_791_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC60 0x00000000  //DDRSS_PHY_792_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC64 0x00000000  //DDRSS_PHY_793_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC68 0x00000000  //DDRSS_PHY_794_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC6C 0x00000000  //DDRSS_PHY_795_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC70 0x16A4A0E6  //DDRSS_PHY_796_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC74 0x103F0000  //DDRSS_PHY_797_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC78 0x000F0000  //DDRSS_PHY_798_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC7C 0x0000000F  //DDRSS_PHY_799_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC80 0x020002FF  //DDRSS_PHY_800_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC84 0x00030000  //DDRSS_PHY_801_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC88 0x00000300  //DDRSS_PHY_802_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC8C 0x00000300  //DDRSS_PHY_803_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC90 0x00000300  //DDRSS_PHY_804_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC94 0x00000300  //DDRSS_PHY_805_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC98 0x00000300  //DDRSS_PHY_806_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC9C 0x42080010  //DDRSS_PHY_807_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA0 0x0000003E  //DDRSS_PHY_808_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA4 0x00000000  //DDRSS_PHY_809_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA8 0x00000000  //DDRSS_PHY_810_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D000 0x00000100  //DDRSS_PHY_1024_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D004 0x00001000  //DDRSS_PHY_1025_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D008 0x00070000  //DDRSS_PHY_1026_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D00C 0x00000000  //DDRSS_PHY_1027_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D010 0x00000000  //DDRSS_PHY_1028_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D014 0x00000100  //DDRSS_PHY_1029_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D018 0x00000000  //DDRSS_PHY_1030_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D01C 0x00000000  //DDRSS_PHY_1031_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D020 0x00000000  //DDRSS_PHY_1032_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D024 0x00000000  //DDRSS_PHY_1033_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D028 0x00000000  //DDRSS_PHY_1034_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D02C 0x00000000  //DDRSS_PHY_1035_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D030 0x00000000  //DDRSS_PHY_1036_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D034 0x00DCBA98  //DDRSS_PHY_1037_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D038 0x00000000  //DDRSS_PHY_1038_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D03C 0x00000000  //DDRSS_PHY_1039_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D040 0x00000000  //DDRSS_PHY_1040_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D044 0x00000000  //DDRSS_PHY_1041_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D048 0x00000000  //DDRSS_PHY_1042_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D04C 0x00000100  //DDRSS_PHY_1043_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D050 0x00000000  //DDRSS_PHY_1044_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D054 0x00000000  //DDRSS_PHY_1045_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D058 0x00000000  //DDRSS_PHY_1046_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D05C 0x00000000  //DDRSS_PHY_1047_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D060 0x00000000  //DDRSS_PHY_1048_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D064 0x00000000  //DDRSS_PHY_1049_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D068 0x00000000  //DDRSS_PHY_1050_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D06C 0x00000000  //DDRSS_PHY_1051_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D070 0x2307B9AC  //DDRSS_PHY_1052_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D074 0x10030000  //DDRSS_PHY_1053_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D078 0x000F0000  //DDRSS_PHY_1054_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D07C 0x0000000F  //DDRSS_PHY_1055_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D080 0x020002FF  //DDRSS_PHY_1056_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D084 0x00030000  //DDRSS_PHY_1057_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D088 0x00000300  //DDRSS_PHY_1058_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D08C 0x00000300  //DDRSS_PHY_1059_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D090 0x00000300  //DDRSS_PHY_1060_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D094 0x00000300  //DDRSS_PHY_1061_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D098 0x00000300  //DDRSS_PHY_1062_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D09C 0x42080010  //DDRSS_PHY_1063_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A0 0x0000003E  //DDRSS_PHY_1064_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A4 0x00000000  //DDRSS_PHY_1065_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A8 0x00000000  //DDRSS_PHY_1066_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D400 0x00000000  //DDRSS_PHY_1280_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D404 0x00000000  //DDRSS_PHY_1281_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D408 0x00000000  //DDRSS_PHY_1282_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D40C 0x00000000  //DDRSS_PHY_1283_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D410 0x00000000  //DDRSS_PHY_1284_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D414 0x00000000  //DDRSS_PHY_1285_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D418 0x00050000  //DDRSS_PHY_1286_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D41C 0x04000100  //DDRSS_PHY_1287_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D420 0x00000055  //DDRSS_PHY_1288_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D424 0x00000000  //DDRSS_PHY_1289_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D428 0x06800000  //DDRSS_PHY_1290_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D42C 0x00000000  //DDRSS_PHY_1291_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D430 0x00000000  //DDRSS_PHY_1292_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D434 0x01002000  //DDRSS_PHY_1293_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D438 0x00004001  //DDRSS_PHY_1294_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D43C 0x00020028  //DDRSS_PHY_1295_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D440 0x00010100  //DDRSS_PHY_1296_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D444 0x00000001  //DDRSS_PHY_1297_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D448 0x00000000  //DDRSS_PHY_1298_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D44C 0x0F0F0E06  //DDRSS_PHY_1299_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D450 0x00010101  //DDRSS_PHY_1300_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D454 0x010F0004  //DDRSS_PHY_1301_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D458 0x00000000  //DDRSS_PHY_1302_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D45C 0x20125770  //DDRSS_PHY_1303_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D460 0x00000064  //DDRSS_PHY_1304_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D464 0x00000000  //DDRSS_PHY_1305_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D468 0x00000000  //DDRSS_PHY_1306_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D46C 0x01020103  //DDRSS_PHY_1307_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D470 0x03020102  //DDRSS_PHY_1308_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D474 0x03030303  //DDRSS_PHY_1309_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D478 0x03030303  //DDRSS_PHY_1310_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D47C 0x00040000  //DDRSS_PHY_1311_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D480 0x00005201  //DDRSS_PHY_1312_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D484 0x00000003  //DDRSS_PHY_1313_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D488 0x00010000  //DDRSS_PHY_1314_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D48C 0x00000000  //DDRSS_PHY_1315_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D490 0x00000003  //DDRSS_PHY_1316_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D494 0x00010000  //DDRSS_PHY_1317_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D498 0x00000000  //DDRSS_PHY_1318_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D49C 0x07070001  //DDRSS_PHY_1319_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A0 0x00005400  //DDRSS_PHY_1320_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A4 0x000040A2  //DDRSS_PHY_1321_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A8 0x00034890  //DDRSS_PHY_1322_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4AC 0x00014890  //DDRSS_PHY_1323_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B0 0x00014890  //DDRSS_PHY_1324_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B4 0x00014890  //DDRSS_PHY_1325_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B8 0x0001488F  //DDRSS_PHY_1326_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4BC 0x00014890  //DDRSS_PHY_1327_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C0 0x0001491E  //DDRSS_PHY_1328_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C4 0x0001491E  //DDRSS_PHY_1329_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C8 0x00014890  //DDRSS_PHY_1330_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4CC 0x00014890  //DDRSS_PHY_1331_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D0 0x00000000  //DDRSS_PHY_1332_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D4 0x00000046  //DDRSS_PHY_1333_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D8 0x00000400  //DDRSS_PHY_1334_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4DC 0x00000008  //DDRSS_PHY_1335_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E0 0x00814890  //DDRSS_PHY_1336_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E4 0x0081491E  //DDRSS_PHY_1337_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E8 0x00148900  //DDRSS_PHY_1338_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4EC 0x001491E8  //DDRSS_PHY_1339_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F0 0x00F4890F  //DDRSS_PHY_1340_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F4 0x03F491EF  //DDRSS_PHY_1341_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F8 0x00000000  //DDRSS_PHY_1342_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4FC 0x00000000  //DDRSS_PHY_1343_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D500 0xB3000000  //DDRSS_PHY_1344_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D504 0x04102006  //DDRSS_PHY_1345_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D508 0x00041020  //DDRSS_PHY_1346_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D50C 0x01C98C98  //DDRSS_PHY_1347_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D510 0x3F400000  //DDRSS_PHY_1348_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D514 0x3F3F1F3F  //DDRSS_PHY_1349_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D518 0x0000001F  //DDRSS_PHY_1350_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D51C 0x00000000  //DDRSS_PHY_1351_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D520 0x00000000  //DDRSS_PHY_1352_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D524 0x00000000  //DDRSS_PHY_1353_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D528 0x00000001  //DDRSS_PHY_1354_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D52C 0x00000000  //DDRSS_PHY_1355_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D530 0x00000000  //DDRSS_PHY_1356_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D534 0x00000000  //DDRSS_PHY_1357_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D538 0x00000000  //DDRSS_PHY_1358_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D53C 0x76543210  //DDRSS_PHY_1359_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D540 0x00000098  //DDRSS_PHY_1360_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D544 0x00000000  //DDRSS_PHY_1361_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D548 0x00000000  //DDRSS_PHY_1362_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D54C 0x00000000  //DDRSS_PHY_1363_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D550 0x00040700  //DDRSS_PHY_1364_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D554 0x00000000  //DDRSS_PHY_1365_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D558 0x00000000  //DDRSS_PHY_1366_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D55C 0x00000000  //DDRSS_PHY_1367_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D560 0x030F7102  //DDRSS_PHY_1368_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D564 0x00000100  //DDRSS_PHY_1369_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D568 0x00000000  //DDRSS_PHY_1370_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D56C 0x0001F7C2  //DDRSS_PHY_1371_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D570 0x00020002  //DDRSS_PHY_1372_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D574 0x00000000  //DDRSS_PHY_1373_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D578 0x00001142  //DDRSS_PHY_1374_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D57C 0x03020400  //DDRSS_PHY_1375_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D580 0x00000080  //DDRSS_PHY_1376_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D584 0x03900390  //DDRSS_PHY_1377_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D588 0x03900390  //DDRSS_PHY_1378_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D58C 0x03900390  //DDRSS_PHY_1379_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D590 0x03900390  //DDRSS_PHY_1380_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D594 0x03900390  //DDRSS_PHY_1381_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D598 0x03900390  //DDRSS_PHY_1382_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D59C 0x00000300  //DDRSS_PHY_1383_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A0 0x00000300  //DDRSS_PHY_1384_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A4 0x00000300  //DDRSS_PHY_1385_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A8 0x00000300  //DDRSS_PHY_1386_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5AC 0x31823FF7  //DDRSS_PHY_1387_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B0 0x00000000  //DDRSS_PHY_1388_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B4 0x0C000D3F  //DDRSS_PHY_1389_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B8 0x30000D3F  //DDRSS_PHY_1390_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5BC 0x300D3F11  //DDRSS_PHY_1391_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C0 0x01FF0000  //DDRSS_PHY_1392_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C4 0x000D3FFF  //DDRSS_PHY_1393_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C8 0x00000C11  //DDRSS_PHY_1394_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5CC 0x300D3F11  //DDRSS_PHY_1395_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D0 0x01FF0000  //DDRSS_PHY_1396_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D4 0x300C3F11  //DDRSS_PHY_1397_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D8 0x01FF0000  //DDRSS_PHY_1398_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5DC 0x300C3F11  //DDRSS_PHY_1399_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E0 0x01FF0000  //DDRSS_PHY_1400_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E4 0x300D3F11  //DDRSS_PHY_1401_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E8 0x01FF0000  //DDRSS_PHY_1402_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5EC 0x300D3F11  //DDRSS_PHY_1403_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F0 0x01FF0000  //DDRSS_PHY_1404_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F4 0x20040004  //DDRSS_PHY_1405_DATA_F0

after several cycles of DDR write & read:

MAIN_Cortex_R5_0_0: GEL Output: 0x0F308000 0x10460A01  //DDRSS_CTL_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308004 0x5D1AF3C3  //DDRSS_CTL_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308008 0x0171A610  //DDRSS_CTL_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30800C 0x40020A11  //DDRSS_CTL_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308010 0x00052006  //DDRSS_CTL_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308014 0x02050020  //DDRSS_CTL_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308018 0x03070101  //DDRSS_CTL_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30801C 0x00089070  //DDRSS_CTL_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308020 0x00000000  //DDRSS_CTL_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308024 0x00000000  //DDRSS_CTL_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308028 0x00000000  //DDRSS_CTL_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30802C 0x00089070  //DDRSS_CTL_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308030 0x00000000  //DDRSS_CTL_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308034 0x00000000  //DDRSS_CTL_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308038 0x00000000  //DDRSS_CTL_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30803C 0x00089070  //DDRSS_CTL_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308040 0x00000000  //DDRSS_CTL_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308044 0x00000000  //DDRSS_CTL_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308048 0x00000000  //DDRSS_CTL_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30804C 0x01010100  //DDRSS_CTL_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308050 0x01000101  //DDRSS_CTL_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308054 0x01000110  //DDRSS_CTL_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308058 0x02010002  //DDRSS_CTL_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30805C 0x00027100  //DDRSS_CTL_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308060 0x00061A80  //DDRSS_CTL_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308064 0x02550255  //DDRSS_CTL_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308068 0x00000255  //DDRSS_CTL_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30806C 0x00000000  //DDRSS_CTL_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308070 0x00000000  //DDRSS_CTL_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308074 0x00000000  //DDRSS_CTL_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308078 0x00000000  //DDRSS_CTL_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30807C 0x00000000  //DDRSS_CTL_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308080 0x00000000  //DDRSS_CTL_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308084 0x00000000  //DDRSS_CTL_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308088 0x00000000  //DDRSS_CTL_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30808C 0x00000000  //DDRSS_CTL_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308090 0x00000000  //DDRSS_CTL_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308094 0x00000000  //DDRSS_CTL_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308098 0x04000B16  //DDRSS_CTL_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30809C 0x1C1C1C1C  //DDRSS_CTL_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A0 0x04000B16  //DDRSS_CTL_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A4 0x1C1C1C1C  //DDRSS_CTL_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A8 0x04000B16  //DDRSS_CTL_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080AC 0x1C1C1C1C  //DDRSS_CTL_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B0 0x05050404  //DDRSS_CTL_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B4 0x00002706  //DDRSS_CTL_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B8 0x0602001D  //DDRSS_CTL_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080BC 0x05001D0B  //DDRSS_CTL_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C0 0x00270605  //DDRSS_CTL_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C4 0x0602001D  //DDRSS_CTL_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C8 0x05001D0B  //DDRSS_CTL_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080CC 0x00270605  //DDRSS_CTL_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D0 0x0602001D  //DDRSS_CTL_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D4 0x07001D0B  //DDRSS_CTL_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D8 0x00180807  //DDRSS_CTL_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080DC 0x0400DB60  //DDRSS_CTL_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E0 0x07070009  //DDRSS_CTL_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E4 0x00001808  //DDRSS_CTL_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E8 0x0400DB60  //DDRSS_CTL_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080EC 0x07070009  //DDRSS_CTL_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F0 0x00001808  //DDRSS_CTL_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F4 0x0400DB60  //DDRSS_CTL_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F8 0x03000009  //DDRSS_CTL_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080FC 0x0D0C0002  //DDRSS_CTL_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308100 0x0D0C0D0C  //DDRSS_CTL_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308104 0x01010000  //DDRSS_CTL_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308108 0x03191919  //DDRSS_CTL_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30810C 0x0B0B0B0B  //DDRSS_CTL_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308110 0x00000B0B  //DDRSS_CTL_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308114 0x00000101  //DDRSS_CTL_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308118 0x00000000  //DDRSS_CTL_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30811C 0x01000000  //DDRSS_CTL_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308120 0x00D00803  //DDRSS_CTL_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308124 0x00001860  //DDRSS_CTL_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308128 0x000000D0  //DDRSS_CTL_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30812C 0x00001860  //DDRSS_CTL_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308130 0x000000D0  //DDRSS_CTL_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308134 0x00001860  //DDRSS_CTL_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308138 0x00000005  //DDRSS_CTL_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30813C 0x00000000  //DDRSS_CTL_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308140 0x00000000  //DDRSS_CTL_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308144 0x00000000  //DDRSS_CTL_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308148 0x00000000  //DDRSS_CTL_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30814C 0x00000000  //DDRSS_CTL_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308150 0x00000000  //DDRSS_CTL_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308154 0x00000000  //DDRSS_CTL_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308158 0x00000000  //DDRSS_CTL_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30815C 0x00090009  //DDRSS_CTL_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308160 0x00000009  //DDRSS_CTL_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308164 0x00000000  //DDRSS_CTL_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308168 0x00000000  //DDRSS_CTL_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30816C 0x00000000  //DDRSS_CTL_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308170 0x00000000  //DDRSS_CTL_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308174 0x00000000  //DDRSS_CTL_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308178 0x00010001  //DDRSS_CTL_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30817C 0x00025501  //DDRSS_CTL_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308180 0x025500D8  //DDRSS_CTL_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308184 0x025500D8  //DDRSS_CTL_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308188 0x00D800D8  //DDRSS_CTL_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30818C 0x00D800D8  //DDRSS_CTL_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308190 0x00000000  //DDRSS_CTL_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308194 0x00000000  //DDRSS_CTL_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308198 0x00000000  //DDRSS_CTL_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30819C 0x00000000  //DDRSS_CTL_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A0 0x00000000  //DDRSS_CTL_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A4 0x00000000  //DDRSS_CTL_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A8 0x03010000  //DDRSS_CTL_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081AC 0x00010000  //DDRSS_CTL_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B0 0x00000000  //DDRSS_CTL_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B4 0x01000000  //DDRSS_CTL_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B8 0x80104002  //DDRSS_CTL_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081BC 0x00040003  //DDRSS_CTL_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C0 0x00040005  //DDRSS_CTL_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C4 0x00030000  //DDRSS_CTL_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C8 0x00050004  //DDRSS_CTL_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081CC 0x00000004  //DDRSS_CTL_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D0 0x00040003  //DDRSS_CTL_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D4 0x00040005  //DDRSS_CTL_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D8 0x00000000  //DDRSS_CTL_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081DC 0x00061800  //DDRSS_CTL_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E0 0x00061800  //DDRSS_CTL_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E4 0x00061800  //DDRSS_CTL_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E8 0x00061800  //DDRSS_CTL_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081EC 0x00061800  //DDRSS_CTL_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F0 0x00000000  //DDRSS_CTL_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F4 0x0000AAA0  //DDRSS_CTL_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F8 0x00061800  //DDRSS_CTL_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081FC 0x00061800  //DDRSS_CTL_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308200 0x00061800  //DDRSS_CTL_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308204 0x00061800  //DDRSS_CTL_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308208 0x00061800  //DDRSS_CTL_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30820C 0x00000000  //DDRSS_CTL_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308210 0x0000AAA0  //DDRSS_CTL_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308214 0x00061800  //DDRSS_CTL_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308218 0x00061800  //DDRSS_CTL_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30821C 0x00061800  //DDRSS_CTL_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308220 0x00061800  //DDRSS_CTL_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308224 0x00061800  //DDRSS_CTL_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308228 0x00000000  //DDRSS_CTL_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30822C 0x0000AAA0  //DDRSS_CTL_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308230 0x00000000  //DDRSS_CTL_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308234 0x00000000  //DDRSS_CTL_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308238 0x00000000  //DDRSS_CTL_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30823C 0x00000000  //DDRSS_CTL_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308240 0x00000000  //DDRSS_CTL_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308244 0x00000000  //DDRSS_CTL_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308248 0x00000000  //DDRSS_CTL_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30824C 0x00000000  //DDRSS_CTL_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308250 0x00000000  //DDRSS_CTL_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308254 0x00000000  //DDRSS_CTL_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308258 0x00000000  //DDRSS_CTL_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30825C 0x00000000  //DDRSS_CTL_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308260 0x00000000  //DDRSS_CTL_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308264 0x00000000  //DDRSS_CTL_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308268 0x00000000  //DDRSS_CTL_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30826C 0x00000000  //DDRSS_CTL_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308270 0x080C0000  //DDRSS_CTL_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308274 0x080C080C  //DDRSS_CTL_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308278 0x00000000  //DDRSS_CTL_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30827C 0x07010A09  //DDRSS_CTL_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308280 0x000E0A09  //DDRSS_CTL_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308284 0x010A0900  //DDRSS_CTL_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308288 0x0E0A0907  //DDRSS_CTL_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30828C 0x0A090000  //DDRSS_CTL_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308290 0x0A090701  //DDRSS_CTL_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308294 0x0000080E  //DDRSS_CTL_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308298 0x00040003  //DDRSS_CTL_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30829C 0x00004007  //DDRSS_CTL_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A0 0x00000000  //DDRSS_CTL_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A4 0x00000000  //DDRSS_CTL_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A8 0x00000000  //DDRSS_CTL_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082AC 0x00000000  //DDRSS_CTL_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B0 0x00000000  //DDRSS_CTL_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B4 0x00000000  //DDRSS_CTL_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B8 0x01000000  //DDRSS_CTL_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082BC 0x00000000  //DDRSS_CTL_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C0 0x00001500  //DDRSS_CTL_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C4 0x0000100E  //DDRSS_CTL_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C8 0x00000000  //DDRSS_CTL_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082CC 0x00000000  //DDRSS_CTL_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D0 0x00000001  //DDRSS_CTL_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D4 0x00000002  //DDRSS_CTL_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D8 0x00000C00  //DDRSS_CTL_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082DC 0x00001000  //DDRSS_CTL_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E0 0x00000C00  //DDRSS_CTL_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E4 0x00001000  //DDRSS_CTL_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E8 0x00000C00  //DDRSS_CTL_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082EC 0x00001000  //DDRSS_CTL_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F0 0x00000000  //DDRSS_CTL_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F4 0x00000000  //DDRSS_CTL_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F8 0x00000000  //DDRSS_CTL_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082FC 0x00000000  //DDRSS_CTL_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308300 0x00000000  //DDRSS_CTL_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308304 0x00000000  //DDRSS_CTL_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308308 0x00000000  //DDRSS_CTL_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30830C 0x00000000  //DDRSS_CTL_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308310 0x00000000  //DDRSS_CTL_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308314 0x00000000  //DDRSS_CTL_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308318 0x00000000  //DDRSS_CTL_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30831C 0x00000000  //DDRSS_CTL_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308320 0x00000000  //DDRSS_CTL_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308324 0x00000000  //DDRSS_CTL_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308328 0x00000000  //DDRSS_CTL_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30832C 0x00000000  //DDRSS_CTL_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308330 0x00041000  //DDRSS_CTL_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308334 0x00000503  //DDRSS_CTL_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308338 0x00000010  //DDRSS_CTL_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30833C 0x00000410  //DDRSS_CTL_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308340 0x00000503  //DDRSS_CTL_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308344 0x00000010  //DDRSS_CTL_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308348 0x00000410  //DDRSS_CTL_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30834C 0x00000503  //DDRSS_CTL_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308350 0x00000010  //DDRSS_CTL_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308354 0x00000410  //DDRSS_CTL_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308358 0x00000503  //DDRSS_CTL_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30835C 0x00000010  //DDRSS_CTL_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308360 0x00000410  //DDRSS_CTL_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308364 0x00000503  //DDRSS_CTL_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308368 0x00000010  //DDRSS_CTL_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30836C 0x00000410  //DDRSS_CTL_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308370 0x00000503  //DDRSS_CTL_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308374 0x00000010  //DDRSS_CTL_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308378 0x00000000  //DDRSS_CTL_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30837C 0x00000000  //DDRSS_CTL_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308380 0x00000000  //DDRSS_CTL_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308384 0x00000000  //DDRSS_CTL_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308388 0x00000000  //DDRSS_CTL_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30838C 0x00000000  //DDRSS_CTL_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308390 0x00000000  //DDRSS_CTL_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308394 0x00000000  //DDRSS_CTL_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308398 0x00000000  //DDRSS_CTL_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30839C 0x00000000  //DDRSS_CTL_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A0 0x00000000  //DDRSS_CTL_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A4 0x00000000  //DDRSS_CTL_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A8 0x00000000  //DDRSS_CTL_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083AC 0x00000000  //DDRSS_CTL_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B0 0x00001401  //DDRSS_CTL_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B4 0x00001401  //DDRSS_CTL_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B8 0x00001401  //DDRSS_CTL_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083BC 0x00001401  //DDRSS_CTL_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C0 0x00001401  //DDRSS_CTL_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C4 0x00001401  //DDRSS_CTL_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C8 0x00000493  //DDRSS_CTL_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083CC 0x00000493  //DDRSS_CTL_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D0 0x00000493  //DDRSS_CTL_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D4 0x00000493  //DDRSS_CTL_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D8 0x00000493  //DDRSS_CTL_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083DC 0x00000493  //DDRSS_CTL_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E0 0x00000000  //DDRSS_CTL_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E4 0x00000000  //DDRSS_CTL_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E8 0x00000000  //DDRSS_CTL_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083EC 0x00000000  //DDRSS_CTL_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F0 0x00000000  //DDRSS_CTL_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F4 0x00000000  //DDRSS_CTL_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F8 0x00000000  //DDRSS_CTL_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083FC 0x00000000  //DDRSS_CTL_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308400 0x00000000  //DDRSS_CTL_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308404 0x00000000  //DDRSS_CTL_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308408 0x00000000  //DDRSS_CTL_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30840C 0x00000000  //DDRSS_CTL_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308410 0x00000000  //DDRSS_CTL_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308414 0x00000000  //DDRSS_CTL_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308418 0x00000000  //DDRSS_CTL_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30841C 0x00000000  //DDRSS_CTL_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308420 0x00000000  //DDRSS_CTL_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308424 0x00000000  //DDRSS_CTL_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308428 0x00000000  //DDRSS_CTL_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30842C 0x00000000  //DDRSS_CTL_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308430 0x00000000  //DDRSS_CTL_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308434 0x00000000  //DDRSS_CTL_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308438 0x00000000  //DDRSS_CTL_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30843C 0x00000000  //DDRSS_CTL_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308440 0x00000000  //DDRSS_CTL_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308444 0x00000000  //DDRSS_CTL_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308448 0x00000000  //DDRSS_CTL_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30844C 0x00000000  //DDRSS_CTL_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308450 0x00000000  //DDRSS_CTL_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308454 0x00010000  //DDRSS_CTL_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308458 0x00000000  //DDRSS_CTL_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30845C 0x00000100  //DDRSS_CTL_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308460 0x00000000  //DDRSS_CTL_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308464 0x00000101  //DDRSS_CTL_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308468 0x00000000  //DDRSS_CTL_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30846C 0x00000000  //DDRSS_CTL_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308470 0x00000000  //DDRSS_CTL_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308474 0x00000000  //DDRSS_CTL_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308478 0x00000000  //DDRSS_CTL_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30847C 0x00000000  //DDRSS_CTL_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308480 0x00000000  //DDRSS_CTL_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308484 0x00000FFF  //DDRSS_CTL_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308488 0x0C181511  //DDRSS_CTL_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30848C 0x00000304  //DDRSS_CTL_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308490 0x00000000  //DDRSS_CTL_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308494 0x00000000  //DDRSS_CTL_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308498 0x00000000  //DDRSS_CTL_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30849C 0x00000000  //DDRSS_CTL_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A0 0x00000000  //DDRSS_CTL_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A4 0x00000000  //DDRSS_CTL_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A8 0x00000000  //DDRSS_CTL_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084AC 0x00000000  //DDRSS_CTL_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B0 0x00000000  //DDRSS_CTL_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B4 0x00000000  //DDRSS_CTL_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B8 0x00000000  //DDRSS_CTL_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084BC 0x00000000  //DDRSS_CTL_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C0 0x00000000  //DDRSS_CTL_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C4 0x00040000  //DDRSS_CTL_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C8 0x00800200  //DDRSS_CTL_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084CC 0x00000000  //DDRSS_CTL_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D0 0x02000400  //DDRSS_CTL_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D4 0x00000080  //DDRSS_CTL_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D8 0x00040000  //DDRSS_CTL_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084DC 0x00800200  //DDRSS_CTL_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E0 0x00000000  //DDRSS_CTL_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E4 0x00000000  //DDRSS_CTL_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E8 0x00000000  //DDRSS_CTL_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084EC 0x00000100  //DDRSS_CTL_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F0 0x01010000  //DDRSS_CTL_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F4 0x00000202  //DDRSS_CTL_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F8 0x0FFF0000  //DDRSS_CTL_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084FC 0x000FFF00  //DDRSS_CTL_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308500 0xFFFFFFFF  //DDRSS_CTL_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308504 0x00FFFF00  //DDRSS_CTL_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308508 0x0A000000  //DDRSS_CTL_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30850C 0x0001FFFF  //DDRSS_CTL_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308510 0x01010101  //DDRSS_CTL_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308514 0x01010101  //DDRSS_CTL_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308518 0x00000118  //DDRSS_CTL_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30851C 0x00000C01  //DDRSS_CTL_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308520 0x00000000  //DDRSS_CTL_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308524 0x00000000  //DDRSS_CTL_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308528 0x00000000  //DDRSS_CTL_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30852C 0x01000000  //DDRSS_CTL_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308530 0x00000100  //DDRSS_CTL_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308534 0x00010000  //DDRSS_CTL_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308538 0x00000000  //DDRSS_CTL_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30853C 0x00000000  //DDRSS_CTL_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308540 0x00000000  //DDRSS_CTL_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308544 0x00000000  //DDRSS_CTL_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308548 0x00000000  //DDRSS_CTL_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30854C 0x00000000  //DDRSS_CTL_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308550 0x00000000  //DDRSS_CTL_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308554 0x00000000  //DDRSS_CTL_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308558 0x00000000  //DDRSS_CTL_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30855C 0x00000000  //DDRSS_CTL_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308560 0x00000000  //DDRSS_CTL_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308564 0x00000000  //DDRSS_CTL_345_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308568 0x00000000  //DDRSS_CTL_346_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30856C 0x00000000  //DDRSS_CTL_347_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308570 0x00000000  //DDRSS_CTL_348_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308574 0x00000000  //DDRSS_CTL_349_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308578 0x00000000  //DDRSS_CTL_350_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30857C 0x00000000  //DDRSS_CTL_351_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308580 0x00000000  //DDRSS_CTL_352_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308584 0x00000000  //DDRSS_CTL_353_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308588 0x00000000  //DDRSS_CTL_354_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30858C 0x00000000  //DDRSS_CTL_355_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308590 0x00000000  //DDRSS_CTL_356_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308594 0x00000000  //DDRSS_CTL_357_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308598 0x00000000  //DDRSS_CTL_358_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30859C 0x00000000  //DDRSS_CTL_359_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A0 0x00000000  //DDRSS_CTL_360_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A4 0x00000000  //DDRSS_CTL_361_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A8 0x00000000  //DDRSS_CTL_362_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085AC 0x00000000  //DDRSS_CTL_363_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B0 0x00000000  //DDRSS_CTL_364_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B4 0x00000001  //DDRSS_CTL_365_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B8 0x00000001  //DDRSS_CTL_366_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085BC 0x000F13D0  //DDRSS_CTL_367_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C0 0x00000000  //DDRSS_CTL_368_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C4 0x00000000  //DDRSS_CTL_369_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C8 0x0E000000  //DDRSS_CTL_370_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085CC 0x060E0606  //DDRSS_CTL_371_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D0 0x06060E06  //DDRSS_CTL_372_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D4 0x00010101  //DDRSS_CTL_373_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D8 0x02000000  //DDRSS_CTL_374_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085DC 0x00020101  //DDRSS_CTL_375_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E0 0x00000000  //DDRSS_CTL_376_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E4 0x02020200  //DDRSS_CTL_377_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E8 0x02020202  //DDRSS_CTL_378_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085EC 0x02020202  //DDRSS_CTL_379_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F0 0x02020202  //DDRSS_CTL_380_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F4 0x00000000  //DDRSS_CTL_381_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F8 0x00000000  //DDRSS_CTL_382_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085FC 0x04000100  //DDRSS_CTL_383_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308600 0x1E000304  //DDRSS_CTL_384_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308604 0x000030C0  //DDRSS_CTL_385_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308608 0x00000200  //DDRSS_CTL_386_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30860C 0x00000200  //DDRSS_CTL_387_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308610 0x00000200  //DDRSS_CTL_388_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308614 0x00000200  //DDRSS_CTL_389_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308618 0x0000DB60  //DDRSS_CTL_390_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30861C 0x0001E780  //DDRSS_CTL_391_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308620 0x090A0302  //DDRSS_CTL_392_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308624 0x001E0B0C  //DDRSS_CTL_393_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308628 0x000030C0  //DDRSS_CTL_394_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30862C 0x00000200  //DDRSS_CTL_395_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308630 0x00000200  //DDRSS_CTL_396_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308634 0x00000200  //DDRSS_CTL_397_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308638 0x00000200  //DDRSS_CTL_398_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30863C 0x0000DB60  //DDRSS_CTL_399_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308640 0x0001E780  //DDRSS_CTL_400_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308644 0x090A0302  //DDRSS_CTL_401_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308648 0x001E0B0C  //DDRSS_CTL_402_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30864C 0x000030C0  //DDRSS_CTL_403_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308650 0x00000200  //DDRSS_CTL_404_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308654 0x00000200  //DDRSS_CTL_405_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308658 0x00000200  //DDRSS_CTL_406_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30865C 0x00000200  //DDRSS_CTL_407_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308660 0x0000DB60  //DDRSS_CTL_408_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308664 0x0001E780  //DDRSS_CTL_409_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308668 0x090A0302  //DDRSS_CTL_410_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30866C 0x00000B0C  //DDRSS_CTL_411_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308670 0x00000000  //DDRSS_CTL_412_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308674 0x0302000A  //DDRSS_CTL_413_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308678 0x01000500  //DDRSS_CTL_414_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30867C 0x01010001  //DDRSS_CTL_415_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308680 0x00010001  //DDRSS_CTL_416_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308684 0x01010001  //DDRSS_CTL_417_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308688 0x02010000  //DDRSS_CTL_418_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30868C 0x00000200  //DDRSS_CTL_419_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308690 0x02000201  //DDRSS_CTL_420_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308694 0x00000000  //DDRSS_CTL_421_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308698 0x00202020  //DDRSS_CTL_422_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A000 0x00000A01  //DDRSS_PI_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A004 0xAE8D79E2  //DDRSS_PI_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A008 0x0714B570  //DDRSS_PI_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A00C 0x01011387  //DDRSS_PI_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A010 0x00000001  //DDRSS_PI_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A014 0x00010064  //DDRSS_PI_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A018 0x00000000  //DDRSS_PI_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A01C 0x00000000  //DDRSS_PI_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A020 0x00000000  //DDRSS_PI_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A024 0x00000003  //DDRSS_PI_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A028 0x0000000F  //DDRSS_PI_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A02C 0x00000000  //DDRSS_PI_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A030 0x00000000  //DDRSS_PI_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A034 0x00010001  //DDRSS_PI_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A038 0x00000000  //DDRSS_PI_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A03C 0x00010001  //DDRSS_PI_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A040 0x00000005  //DDRSS_PI_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A044 0x00010000  //DDRSS_PI_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A048 0x00000000  //DDRSS_PI_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A04C 0x00000000  //DDRSS_PI_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A050 0x00000000  //DDRSS_PI_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A054 0x00000000  //DDRSS_PI_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A058 0x00000000  //DDRSS_PI_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A05C 0x00000000  //DDRSS_PI_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A060 0x280D0001  //DDRSS_PI_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A064 0x00000000  //DDRSS_PI_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A068 0x00010000  //DDRSS_PI_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A06C 0x00003200  //DDRSS_PI_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A070 0x00000000  //DDRSS_PI_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A074 0x00000000  //DDRSS_PI_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A078 0x00060602  //DDRSS_PI_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A07C 0x00000000  //DDRSS_PI_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A080 0x00000000  //DDRSS_PI_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A084 0x00000000  //DDRSS_PI_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A088 0x00000001  //DDRSS_PI_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A08C 0x00000055  //DDRSS_PI_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A090 0x000000AA  //DDRSS_PI_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A094 0x000000AD  //DDRSS_PI_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A098 0x00000052  //DDRSS_PI_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A09C 0x0000006A  //DDRSS_PI_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A0 0x00000095  //DDRSS_PI_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A4 0x00000095  //DDRSS_PI_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A8 0x000000AD  //DDRSS_PI_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0AC 0x00000000  //DDRSS_PI_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B0 0x00000000  //DDRSS_PI_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B4 0x00010100  //DDRSS_PI_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B8 0x00000014  //DDRSS_PI_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0BC 0x000007D0  //DDRSS_PI_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C0 0x00000300  //DDRSS_PI_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C4 0x00000000  //DDRSS_PI_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C8 0x00000000  //DDRSS_PI_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0CC 0x01000000  //DDRSS_PI_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D0 0x00010101  //DDRSS_PI_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D4 0x01000B09  //DDRSS_PI_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D8 0x00000000  //DDRSS_PI_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0DC 0x00010000  //DDRSS_PI_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E0 0x00000000  //DDRSS_PI_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E4 0x00000000  //DDRSS_PI_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E8 0x00000000  //DDRSS_PI_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0EC 0x00000000  //DDRSS_PI_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F0 0x00001400  //DDRSS_PI_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F4 0x00000000  //DDRSS_PI_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F8 0x01000000  //DDRSS_PI_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0FC 0x00000404  //DDRSS_PI_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A100 0x00000001  //DDRSS_PI_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A104 0x0001010E  //DDRSS_PI_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A108 0x02040100  //DDRSS_PI_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A10C 0x00010000  //DDRSS_PI_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A110 0x00000034  //DDRSS_PI_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A114 0x00000000  //DDRSS_PI_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A118 0x00000000  //DDRSS_PI_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A11C 0x00000000  //DDRSS_PI_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A120 0x00000000  //DDRSS_PI_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A124 0x00000000  //DDRSS_PI_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A128 0x00000000  //DDRSS_PI_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A12C 0x00000005  //DDRSS_PI_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A130 0x01000000  //DDRSS_PI_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A134 0x04020100  //DDRSS_PI_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A138 0x00020000  //DDRSS_PI_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A13C 0x00010002  //DDRSS_PI_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A140 0x00000001  //DDRSS_PI_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A144 0x00020001  //DDRSS_PI_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A148 0x00020002  //DDRSS_PI_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A14C 0x29C02000  //DDRSS_PI_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A150 0x00000000  //DDRSS_PI_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A154 0x00000000  //DDRSS_PI_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A158 0x00000000  //DDRSS_PI_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A15C 0x00000000  //DDRSS_PI_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A160 0x00000000  //DDRSS_PI_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A164 0x00000000  //DDRSS_PI_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A168 0x00000000  //DDRSS_PI_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A16C 0x00000300  //DDRSS_PI_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A170 0x0A090B0C  //DDRSS_PI_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A174 0x04060708  //DDRSS_PI_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A178 0x01000005  //DDRSS_PI_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A17C 0x00000800  //DDRSS_PI_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A180 0x00000000  //DDRSS_PI_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A184 0x00010008  //DDRSS_PI_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A188 0x00000000  //DDRSS_PI_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A18C 0x0000AA00  //DDRSS_PI_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A190 0x00000000  //DDRSS_PI_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A194 0x00010000  //DDRSS_PI_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A198 0x00000000  //DDRSS_PI_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A19C 0x00000000  //DDRSS_PI_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A0 0x00000000  //DDRSS_PI_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A4 0x00000000  //DDRSS_PI_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A8 0x00000000  //DDRSS_PI_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1AC 0x00000000  //DDRSS_PI_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B0 0x00000000  //DDRSS_PI_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B4 0x00000000  //DDRSS_PI_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B8 0x00000000  //DDRSS_PI_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1BC 0x00000000  //DDRSS_PI_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C0 0x00000000  //DDRSS_PI_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C4 0x00000000  //DDRSS_PI_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C8 0x00000000  //DDRSS_PI_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1CC 0x00000000  //DDRSS_PI_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D0 0x00000000  //DDRSS_PI_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D4 0x00000000  //DDRSS_PI_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D8 0x00000000  //DDRSS_PI_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1DC 0x00000000  //DDRSS_PI_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E0 0x00000000  //DDRSS_PI_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E4 0x00000000  //DDRSS_PI_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E8 0x00000000  //DDRSS_PI_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1EC 0x00000000  //DDRSS_PI_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F0 0x00000008  //DDRSS_PI_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F4 0x00000000  //DDRSS_PI_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F8 0x00000000  //DDRSS_PI_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1FC 0x00000000  //DDRSS_PI_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A200 0x00000000  //DDRSS_PI_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A204 0x00000000  //DDRSS_PI_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A208 0x00000000  //DDRSS_PI_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A20C 0x00000000  //DDRSS_PI_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A210 0x00000000  //DDRSS_PI_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A214 0x00010100  //DDRSS_PI_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A218 0x00000000  //DDRSS_PI_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A21C 0x00000000  //DDRSS_PI_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A220 0x00027100  //DDRSS_PI_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A224 0x00061A80  //DDRSS_PI_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A228 0x00000100  //DDRSS_PI_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A22C 0x00000000  //DDRSS_PI_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A230 0x00000000  //DDRSS_PI_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A234 0x00000000  //DDRSS_PI_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A238 0x00000000  //DDRSS_PI_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A23C 0x00000000  //DDRSS_PI_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A240 0x01000000  //DDRSS_PI_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A244 0xC1010003  //DDRSS_PI_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A248 0x02000101  //DDRSS_PI_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A24C 0x01030101  //DDRSS_PI_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A250 0x00010400  //DDRSS_PI_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A254 0x06000105  //DDRSS_PI_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A258 0x01070001  //DDRSS_PI_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A25C 0x00000000  //DDRSS_PI_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A260 0x00000000  //DDRSS_PI_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A264 0x00000001  //DDRSS_PI_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A268 0x00010000  //DDRSS_PI_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A26C 0x00000000  //DDRSS_PI_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A270 0x00000000  //DDRSS_PI_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A274 0x00000000  //DDRSS_PI_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A278 0x00000000  //DDRSS_PI_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A27C 0x00010000  //DDRSS_PI_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A280 0x00000004  //DDRSS_PI_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A284 0x00000000  //DDRSS_PI_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A288 0x00000000  //DDRSS_PI_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A28C 0x00000000  //DDRSS_PI_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A290 0x00007800  //DDRSS_PI_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A294 0x00780078  //DDRSS_PI_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A298 0x00141414  //DDRSS_PI_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A29C 0x00000037  //DDRSS_PI_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A0 0x00000037  //DDRSS_PI_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A4 0x00040037  //DDRSS_PI_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A8 0x04000400  //DDRSS_PI_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2AC 0x6804000B  //DDRSS_PI_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B0 0x04000B16  //DDRSS_PI_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B4 0x000B1668  //DDRSS_PI_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B8 0x00166804  //DDRSS_PI_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2BC 0x000000D0  //DDRSS_PI_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C0 0x00001860  //DDRSS_PI_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C4 0x000000D0  //DDRSS_PI_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C8 0x00001860  //DDRSS_PI_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2CC 0x000000D0  //DDRSS_PI_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D0 0x04001860  //DDRSS_PI_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D4 0x01010404  //DDRSS_PI_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D8 0x00001901  //DDRSS_PI_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2DC 0x00190019  //DDRSS_PI_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E0 0x010E010E  //DDRSS_PI_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E4 0x0000010E  //DDRSS_PI_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E8 0x00000000  //DDRSS_PI_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2EC 0x00000000  //DDRSS_PI_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F0 0x01010000  //DDRSS_PI_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F4 0x01010101  //DDRSS_PI_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F8 0x00181818  //DDRSS_PI_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2FC 0x00000000  //DDRSS_PI_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A300 0x00000000  //DDRSS_PI_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A304 0x0A000000  //DDRSS_PI_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A308 0x0C0C0A0A  //DDRSS_PI_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A30C 0x0303030C  //DDRSS_PI_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A310 0x00000000  //DDRSS_PI_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A314 0x00000000  //DDRSS_PI_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A318 0x00000000  //DDRSS_PI_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A31C 0x00000000  //DDRSS_PI_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A320 0x00000000  //DDRSS_PI_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A324 0x00000000  //DDRSS_PI_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A328 0x00000000  //DDRSS_PI_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A32C 0x00000000  //DDRSS_PI_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A330 0x00000000  //DDRSS_PI_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A334 0x00000000  //DDRSS_PI_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A338 0x00000000  //DDRSS_PI_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A33C 0x00000000  //DDRSS_PI_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A340 0x00000000  //DDRSS_PI_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A344 0x0D090000  //DDRSS_PI_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A348 0x0D09000D  //DDRSS_PI_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A34C 0x0D09000D  //DDRSS_PI_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A350 0x0000000D  //DDRSS_PI_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A354 0x00000000  //DDRSS_PI_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A358 0x00000000  //DDRSS_PI_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A35C 0x00000000  //DDRSS_PI_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A360 0x00000000  //DDRSS_PI_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A364 0x16000000  //DDRSS_PI_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A368 0x001600C8  //DDRSS_PI_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A36C 0x001600C8  //DDRSS_PI_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A370 0x010100C8  //DDRSS_PI_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A374 0x00001D01  //DDRSS_PI_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A378 0x1F0F004E  //DDRSS_PI_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A37C 0x02000001  //DDRSS_PI_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A380 0x001D0A0A  //DDRSS_PI_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A384 0x1F0F004E  //DDRSS_PI_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A388 0x02000001  //DDRSS_PI_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A38C 0x001D0A0A  //DDRSS_PI_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A390 0x1F0F004E  //DDRSS_PI_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A394 0x02000001  //DDRSS_PI_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A398 0x00010A0A  //DDRSS_PI_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A39C 0x0C0B0700  //DDRSS_PI_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A0 0x000D0605  //DDRSS_PI_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A4 0x0000C570  //DDRSS_PI_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A8 0x0000001D  //DDRSS_PI_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3AC 0x180A0800  //DDRSS_PI_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B0 0x0B071C1C  //DDRSS_PI_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B4 0x0D06050C  //DDRSS_PI_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B8 0x0000C570  //DDRSS_PI_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3BC 0x0000001D  //DDRSS_PI_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C0 0x180A0800  //DDRSS_PI_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C4 0x0B071C1C  //DDRSS_PI_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C8 0x0D06050C  //DDRSS_PI_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3CC 0x0000C570  //DDRSS_PI_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D0 0x0000001D  //DDRSS_PI_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D4 0x180A0800  //DDRSS_PI_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D8 0x00001C1C  //DDRSS_PI_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3DC 0x000030C0  //DDRSS_PI_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E0 0x0001E780  //DDRSS_PI_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E4 0x000030C0  //DDRSS_PI_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E8 0x0001E780  //DDRSS_PI_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3EC 0x000030C0  //DDRSS_PI_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F0 0x0001E780  //DDRSS_PI_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F4 0x02550255  //DDRSS_PI_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F8 0x03030255  //DDRSS_PI_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3FC 0x00025503  //DDRSS_PI_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A400 0x02550255  //DDRSS_PI_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A404 0x0C080C08  //DDRSS_PI_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A408 0x00000C08  //DDRSS_PI_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A40C 0x00089070  //DDRSS_PI_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A410 0x00000000  //DDRSS_PI_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A414 0x00000000  //DDRSS_PI_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A418 0x00000000  //DDRSS_PI_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A41C 0x000000D8  //DDRSS_PI_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A420 0x00089070  //DDRSS_PI_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A424 0x00000000  //DDRSS_PI_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A428 0x00000000  //DDRSS_PI_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A42C 0x00000000  //DDRSS_PI_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A430 0x000000D8  //DDRSS_PI_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A434 0x00089070  //DDRSS_PI_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A438 0x00000000  //DDRSS_PI_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A43C 0x00000000  //DDRSS_PI_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A440 0x00000000  //DDRSS_PI_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A444 0x020000D8  //DDRSS_PI_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A448 0x00000080  //DDRSS_PI_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A44C 0x00020000  //DDRSS_PI_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A450 0x00000080  //DDRSS_PI_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A454 0x00020000  //DDRSS_PI_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A458 0x00000080  //DDRSS_PI_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A45C 0x00000000  //DDRSS_PI_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A460 0x00000000  //DDRSS_PI_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A464 0x00040404  //DDRSS_PI_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A468 0x00000000  //DDRSS_PI_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A46C 0x02010102  //DDRSS_PI_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A470 0x67676767  //DDRSS_PI_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A474 0x00000202  //DDRSS_PI_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A478 0x00000000  //DDRSS_PI_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A47C 0x00000000  //DDRSS_PI_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A480 0x00000000  //DDRSS_PI_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A484 0x00000000  //DDRSS_PI_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A488 0x00000000  //DDRSS_PI_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A48C 0x0D100F00  //DDRSS_PI_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A490 0x0003020E  //DDRSS_PI_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A494 0x00000001  //DDRSS_PI_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A498 0x01000000  //DDRSS_PI_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A49C 0x00020201  //DDRSS_PI_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A0 0x00000000  //DDRSS_PI_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A4 0x00000410  //DDRSS_PI_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A8 0x00000503  //DDRSS_PI_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4AC 0x00000010  //DDRSS_PI_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B0 0x00000000  //DDRSS_PI_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B4 0x00000000  //DDRSS_PI_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B8 0x00001401  //DDRSS_PI_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4BC 0x00000493  //DDRSS_PI_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C0 0x00000000  //DDRSS_PI_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C4 0x00000410  //DDRSS_PI_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C8 0x00000503  //DDRSS_PI_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4CC 0x00000010  //DDRSS_PI_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D0 0x00000000  //DDRSS_PI_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D4 0x00000000  //DDRSS_PI_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D8 0x00001401  //DDRSS_PI_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4DC 0x00000493  //DDRSS_PI_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E0 0x00000000  //DDRSS_PI_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E4 0x00000410  //DDRSS_PI_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E8 0x00000503  //DDRSS_PI_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4EC 0x00000010  //DDRSS_PI_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F0 0x00000000  //DDRSS_PI_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F4 0x00000000  //DDRSS_PI_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F8 0x00001401  //DDRSS_PI_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4FC 0x00000493  //DDRSS_PI_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A500 0x00000000  //DDRSS_PI_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A504 0x00000410  //DDRSS_PI_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A508 0x00000503  //DDRSS_PI_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A50C 0x00000010  //DDRSS_PI_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A510 0x00000000  //DDRSS_PI_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A514 0x00000000  //DDRSS_PI_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A518 0x00001401  //DDRSS_PI_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A51C 0x00000493  //DDRSS_PI_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A520 0x00000000  //DDRSS_PI_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A524 0x00000410  //DDRSS_PI_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A528 0x00000503  //DDRSS_PI_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A52C 0x00000010  //DDRSS_PI_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A530 0x00000000  //DDRSS_PI_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A534 0x00000000  //DDRSS_PI_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A538 0x00001401  //DDRSS_PI_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A53C 0x00000493  //DDRSS_PI_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A540 0x00000000  //DDRSS_PI_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A544 0x00000410  //DDRSS_PI_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A548 0x00000503  //DDRSS_PI_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A54C 0x00000010  //DDRSS_PI_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A550 0x00000000  //DDRSS_PI_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A554 0x00000000  //DDRSS_PI_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A558 0x00001401  //DDRSS_PI_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A55C 0x00000493  //DDRSS_PI_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A560 0x00000000  //DDRSS_PI_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C000 0x04C00000  //DDRSS_PHY_0_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C004 0x00000000  //DDRSS_PHY_1_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C008 0x00000200  //DDRSS_PHY_2_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C00C 0x00000000  //DDRSS_PHY_3_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C010 0x00000000  //DDRSS_PHY_4_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C014 0x00000000  //DDRSS_PHY_5_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C018 0x00000000  //DDRSS_PHY_6_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C01C 0x00000000  //DDRSS_PHY_7_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C020 0x00000001  //DDRSS_PHY_8_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C024 0x00000000  //DDRSS_PHY_9_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C028 0x0A0C0000  //DDRSS_PHY_10_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C02C 0x010101FF  //DDRSS_PHY_11_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C030 0x00010000  //DDRSS_PHY_12_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C034 0x00C04004  //DDRSS_PHY_13_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C038 0x00CC0008  //DDRSS_PHY_14_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C03C 0x00660201  //DDRSS_PHY_15_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C040 0x00000000  //DDRSS_PHY_16_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C044 0x00000000  //DDRSS_PHY_17_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C048 0x00000000  //DDRSS_PHY_18_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C04C 0x0000AAAA  //DDRSS_PHY_19_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C050 0x00005555  //DDRSS_PHY_20_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C054 0x0000B5B5  //DDRSS_PHY_21_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C058 0x00004A4A  //DDRSS_PHY_22_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C05C 0x00005656  //DDRSS_PHY_23_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C060 0x0000A9A9  //DDRSS_PHY_24_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C064 0x0000B7B7  //DDRSS_PHY_25_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C068 0x00004848  //DDRSS_PHY_26_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C06C 0x00000000  //DDRSS_PHY_27_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C070 0x00000000  //DDRSS_PHY_28_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C074 0x08000000  //DDRSS_PHY_29_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C078 0x0F000008  //DDRSS_PHY_30_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C07C 0x00000F0F  //DDRSS_PHY_31_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C080 0x00E4E400  //DDRSS_PHY_32_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C084 0x00070820  //DDRSS_PHY_33_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C088 0x000C0020  //DDRSS_PHY_34_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C08C 0x00062000  //DDRSS_PHY_35_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C090 0x00000000  //DDRSS_PHY_36_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C094 0x55555555  //DDRSS_PHY_37_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C098 0xAAAAAAAA  //DDRSS_PHY_38_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C09C 0x55555555  //DDRSS_PHY_39_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A0 0xAAAAAAAA  //DDRSS_PHY_40_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A4 0x00005555  //DDRSS_PHY_41_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A8 0x01000100  //DDRSS_PHY_42_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0AC 0x00800180  //DDRSS_PHY_43_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B0 0x00000000  //DDRSS_PHY_44_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B4 0x00100000  //DDRSS_PHY_45_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B8 0x00000000  //DDRSS_PHY_46_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0BC 0x05070010  //DDRSS_PHY_47_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C0 0x0000000C  //DDRSS_PHY_48_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C4 0x00000700  //DDRSS_PHY_49_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C8 0x003C0024  //DDRSS_PHY_50_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0CC 0x00000FFF  //DDRSS_PHY_51_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D0 0x00000000  //DDRSS_PHY_52_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D4 0x02B802AC  //DDRSS_PHY_53_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D8 0x00000030  //DDRSS_PHY_54_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0DC 0x0114003C  //DDRSS_PHY_55_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E0 0x00000000  //DDRSS_PHY_56_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E4 0x0C000000  //DDRSS_PHY_57_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E8 0x07FF0000  //DDRSS_PHY_58_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0EC 0x00000000  //DDRSS_PHY_59_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F0 0x00000000  //DDRSS_PHY_60_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F4 0x00000000  //DDRSS_PHY_61_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F8 0x00000000  //DDRSS_PHY_62_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0FC 0x00000000  //DDRSS_PHY_63_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C100 0x00000000  //DDRSS_PHY_64_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C104 0x00000004  //DDRSS_PHY_65_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C108 0x00000000  //DDRSS_PHY_66_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C10C 0x00000000  //DDRSS_PHY_67_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C110 0x00000000  //DDRSS_PHY_68_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C114 0x00000000  //DDRSS_PHY_69_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C118 0x00000000  //DDRSS_PHY_70_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C11C 0x00000000  //DDRSS_PHY_71_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C120 0x041F07FF  //DDRSS_PHY_72_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C124 0x00000000  //DDRSS_PHY_73_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C128 0x01CCB001  //DDRSS_PHY_74_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C12C 0x2000CCB0  //DDRSS_PHY_75_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C130 0x20000140  //DDRSS_PHY_76_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C134 0x07FF0200  //DDRSS_PHY_77_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C138 0x0000DD01  //DDRSS_PHY_78_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C13C 0x10100303  //DDRSS_PHY_79_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C140 0x10101010  //DDRSS_PHY_80_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C144 0x10101010  //DDRSS_PHY_81_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C148 0x00021010  //DDRSS_PHY_82_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C14C 0x00100010  //DDRSS_PHY_83_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C150 0x00100010  //DDRSS_PHY_84_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C154 0x00100010  //DDRSS_PHY_85_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C158 0x00100010  //DDRSS_PHY_86_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C15C 0x02020010  //DDRSS_PHY_87_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C160 0x51515041  //DDRSS_PHY_88_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C164 0x31804000  //DDRSS_PHY_89_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C168 0x04C00340  //DDRSS_PHY_90_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C16C 0x01008080  //DDRSS_PHY_91_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C170 0x04050001  //DDRSS_PHY_92_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C174 0x00000504  //DDRSS_PHY_93_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C178 0x42100010  //DDRSS_PHY_94_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C17C 0x010C053E  //DDRSS_PHY_95_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C180 0x000F0C14  //DDRSS_PHY_96_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C184 0x01000140  //DDRSS_PHY_97_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C188 0x007A0120  //DDRSS_PHY_98_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C18C 0x00000C00  //DDRSS_PHY_99_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C190 0x000001CC  //DDRSS_PHY_100_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C194 0x20100200  //DDRSS_PHY_101_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C198 0x00000005  //DDRSS_PHY_102_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C19C 0x76543210  //DDRSS_PHY_103_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A0 0x00000008  //DDRSS_PHY_104_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A4 0x02800280  //DDRSS_PHY_105_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A8 0x02800280  //DDRSS_PHY_106_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1AC 0x02800280  //DDRSS_PHY_107_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B0 0x02800280  //DDRSS_PHY_108_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B4 0x00300280  //DDRSS_PHY_109_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B8 0x0000A800  //DDRSS_PHY_110_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1BC 0x00A800AE  //DDRSS_PHY_111_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C0 0x00A800B4  //DDRSS_PHY_112_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C4 0x00B400AE  //DDRSS_PHY_113_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C8 0x00B400BA  //DDRSS_PHY_114_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1CC 0x00A800B4  //DDRSS_PHY_115_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D0 0x00A800AE  //DDRSS_PHY_116_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D4 0x00A800AE  //DDRSS_PHY_117_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D8 0x00A800AE  //DDRSS_PHY_118_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1DC 0x01B200AE  //DDRSS_PHY_119_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E0 0x01000000  //DDRSS_PHY_120_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E4 0x00000000  //DDRSS_PHY_121_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E8 0x00000000  //DDRSS_PHY_122_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1EC 0x00080200  //DDRSS_PHY_123_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F0 0x00000000  //DDRSS_PHY_124_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F4 0x00000000  //DDRSS_PHY_125_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C400 0x04C00000  //DDRSS_PHY_256_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C404 0x00000000  //DDRSS_PHY_257_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C408 0x00000200  //DDRSS_PHY_258_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C40C 0x00000000  //DDRSS_PHY_259_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C410 0x00000000  //DDRSS_PHY_260_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C414 0x00000000  //DDRSS_PHY_261_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C418 0x00000000  //DDRSS_PHY_262_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C41C 0x00000000  //DDRSS_PHY_263_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C420 0x00000001  //DDRSS_PHY_264_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C424 0x00000000  //DDRSS_PHY_265_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C428 0x0A0C0000  //DDRSS_PHY_266_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C42C 0x010101FF  //DDRSS_PHY_267_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C430 0x00010000  //DDRSS_PHY_268_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C434 0x00C04004  //DDRSS_PHY_269_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C438 0x00CC0008  //DDRSS_PHY_270_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C43C 0x00660201  //DDRSS_PHY_271_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C440 0x00000000  //DDRSS_PHY_272_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C444 0x00000000  //DDRSS_PHY_273_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C448 0x00000000  //DDRSS_PHY_274_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C44C 0x0000AAAA  //DDRSS_PHY_275_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C450 0x00005555  //DDRSS_PHY_276_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C454 0x0000B5B5  //DDRSS_PHY_277_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C458 0x00004A4A  //DDRSS_PHY_278_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C45C 0x00005656  //DDRSS_PHY_279_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C460 0x0000A9A9  //DDRSS_PHY_280_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C464 0x0000B7B7  //DDRSS_PHY_281_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C468 0x00004848  //DDRSS_PHY_282_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C46C 0x00000000  //DDRSS_PHY_283_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C470 0x00000000  //DDRSS_PHY_284_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C474 0x08000000  //DDRSS_PHY_285_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C478 0x0F000008  //DDRSS_PHY_286_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C47C 0x00000F0F  //DDRSS_PHY_287_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C480 0x00E4E400  //DDRSS_PHY_288_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C484 0x00070820  //DDRSS_PHY_289_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C488 0x000C0020  //DDRSS_PHY_290_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C48C 0x00062000  //DDRSS_PHY_291_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C490 0x00000000  //DDRSS_PHY_292_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C494 0x55555555  //DDRSS_PHY_293_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C498 0xAAAAAAAA  //DDRSS_PHY_294_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C49C 0x55555555  //DDRSS_PHY_295_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A0 0xAAAAAAAA  //DDRSS_PHY_296_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A4 0x00005555  //DDRSS_PHY_297_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A8 0x01000100  //DDRSS_PHY_298_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4AC 0x00800180  //DDRSS_PHY_299_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B0 0x00000000  //DDRSS_PHY_300_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B4 0x00100000  //DDRSS_PHY_301_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B8 0x00000000  //DDRSS_PHY_302_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4BC 0x14070010  //DDRSS_PHY_303_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C0 0x00000014  //DDRSS_PHY_304_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C4 0x00010600  //DDRSS_PHY_305_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C8 0x0048003C  //DDRSS_PHY_306_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4CC 0x00000FFF  //DDRSS_PHY_307_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D0 0x00000000  //DDRSS_PHY_308_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D4 0x02AC02A0  //DDRSS_PHY_309_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D8 0x00000030  //DDRSS_PHY_310_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4DC 0x01200048  //DDRSS_PHY_311_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E0 0x00000000  //DDRSS_PHY_312_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E4 0x0C000000  //DDRSS_PHY_313_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E8 0x07FF0000  //DDRSS_PHY_314_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4EC 0x00000000  //DDRSS_PHY_315_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F0 0x00000000  //DDRSS_PHY_316_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F4 0x00000000  //DDRSS_PHY_317_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F8 0x00000000  //DDRSS_PHY_318_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4FC 0x00000000  //DDRSS_PHY_319_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C500 0x00000000  //DDRSS_PHY_320_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C504 0x00000004  //DDRSS_PHY_321_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C508 0x00000000  //DDRSS_PHY_322_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C50C 0x00000000  //DDRSS_PHY_323_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C510 0x00000000  //DDRSS_PHY_324_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C514 0x00000000  //DDRSS_PHY_325_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C518 0x00000000  //DDRSS_PHY_326_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C51C 0x00000000  //DDRSS_PHY_327_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C520 0x041F07FF  //DDRSS_PHY_328_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C524 0x00000000  //DDRSS_PHY_329_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C528 0x01CCB001  //DDRSS_PHY_330_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C52C 0x2000CCB0  //DDRSS_PHY_331_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C530 0x20000140  //DDRSS_PHY_332_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C534 0x07FF0200  //DDRSS_PHY_333_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C538 0x0000DD01  //DDRSS_PHY_334_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C53C 0x10100303  //DDRSS_PHY_335_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C540 0x10101010  //DDRSS_PHY_336_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C544 0x10101010  //DDRSS_PHY_337_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C548 0x00021010  //DDRSS_PHY_338_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C54C 0x00100010  //DDRSS_PHY_339_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C550 0x00100010  //DDRSS_PHY_340_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C554 0x00100010  //DDRSS_PHY_341_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C558 0x00100010  //DDRSS_PHY_342_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C55C 0x02020010  //DDRSS_PHY_343_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C560 0x51515041  //DDRSS_PHY_344_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C564 0x31804000  //DDRSS_PHY_345_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C568 0x04C00340  //DDRSS_PHY_346_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C56C 0x01008080  //DDRSS_PHY_347_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C570 0x04050001  //DDRSS_PHY_348_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C574 0x00000504  //DDRSS_PHY_349_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C578 0x42100010  //DDRSS_PHY_350_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C57C 0x010C053E  //DDRSS_PHY_351_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C580 0x000F0C14  //DDRSS_PHY_352_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C584 0x01000140  //DDRSS_PHY_353_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C588 0x007A0120  //DDRSS_PHY_354_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C58C 0x00000C00  //DDRSS_PHY_355_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C590 0x000001CC  //DDRSS_PHY_356_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C594 0x20100200  //DDRSS_PHY_357_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C598 0x00000005  //DDRSS_PHY_358_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C59C 0x76543210  //DDRSS_PHY_359_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A0 0x00000008  //DDRSS_PHY_360_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A4 0x02800280  //DDRSS_PHY_361_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A8 0x02800280  //DDRSS_PHY_362_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5AC 0x02800280  //DDRSS_PHY_363_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B0 0x02800280  //DDRSS_PHY_364_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B4 0x00420280  //DDRSS_PHY_365_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B8 0x0000B400  //DDRSS_PHY_366_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5BC 0x00A800B4  //DDRSS_PHY_367_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C0 0x00A800AE  //DDRSS_PHY_368_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C4 0x00B400A8  //DDRSS_PHY_369_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C8 0x00B400B4  //DDRSS_PHY_370_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5CC 0x00B400B4  //DDRSS_PHY_371_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D0 0x00B400B4  //DDRSS_PHY_372_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D4 0x00AE00B4  //DDRSS_PHY_373_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D8 0x00B400AE  //DDRSS_PHY_374_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5DC 0x01A600B4  //DDRSS_PHY_375_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E0 0x01000000  //DDRSS_PHY_376_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E4 0x00000000  //DDRSS_PHY_377_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E8 0x00000000  //DDRSS_PHY_378_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5EC 0x00080200  //DDRSS_PHY_379_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F0 0x00000000  //DDRSS_PHY_380_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F4 0x00000000  //DDRSS_PHY_381_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C800 0x00000100  //DDRSS_PHY_512_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C804 0x00001000  //DDRSS_PHY_513_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C808 0x00070000  //DDRSS_PHY_514_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C80C 0x00000000  //DDRSS_PHY_515_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C810 0x00000000  //DDRSS_PHY_516_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C814 0x00000100  //DDRSS_PHY_517_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C818 0x00000000  //DDRSS_PHY_518_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C81C 0x00000000  //DDRSS_PHY_519_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C820 0x00000000  //DDRSS_PHY_520_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C824 0x00000000  //DDRSS_PHY_521_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C828 0x00000000  //DDRSS_PHY_522_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C82C 0x00000000  //DDRSS_PHY_523_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C830 0x00000000  //DDRSS_PHY_524_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C834 0x00DCBA98  //DDRSS_PHY_525_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C838 0x00000000  //DDRSS_PHY_526_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C83C 0x00000000  //DDRSS_PHY_527_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C840 0x00000000  //DDRSS_PHY_528_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C844 0x00000000  //DDRSS_PHY_529_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C848 0x00000000  //DDRSS_PHY_530_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C84C 0x00000100  //DDRSS_PHY_531_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C850 0x00000000  //DDRSS_PHY_532_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C854 0x00000000  //DDRSS_PHY_533_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C858 0x00000000  //DDRSS_PHY_534_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C85C 0x00000000  //DDRSS_PHY_535_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C860 0x00000000  //DDRSS_PHY_536_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C864 0x00000000  //DDRSS_PHY_537_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C868 0x00000000  //DDRSS_PHY_538_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C86C 0x00000000  //DDRSS_PHY_539_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C870 0x0A418820  //DDRSS_PHY_540_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C874 0x103F0000  //DDRSS_PHY_541_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C878 0x000F0100  //DDRSS_PHY_542_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C87C 0x0000000F  //DDRSS_PHY_543_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C880 0x020002FF  //DDRSS_PHY_544_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C884 0x00030000  //DDRSS_PHY_545_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C888 0x00000300  //DDRSS_PHY_546_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C88C 0x00000300  //DDRSS_PHY_547_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C890 0x00000300  //DDRSS_PHY_548_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C894 0x00000300  //DDRSS_PHY_549_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C898 0x00000300  //DDRSS_PHY_550_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C89C 0x42080010  //DDRSS_PHY_551_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A0 0x0000003E  //DDRSS_PHY_552_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A4 0x00000000  //DDRSS_PHY_553_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A8 0x00000000  //DDRSS_PHY_554_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC00 0x00000100  //DDRSS_PHY_768_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC04 0x00001000  //DDRSS_PHY_769_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC08 0x00070000  //DDRSS_PHY_770_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC0C 0x00000000  //DDRSS_PHY_771_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC10 0x00000000  //DDRSS_PHY_772_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC14 0x00000100  //DDRSS_PHY_773_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC18 0x00000000  //DDRSS_PHY_774_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC1C 0x00000000  //DDRSS_PHY_775_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC20 0x00000000  //DDRSS_PHY_776_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC24 0x00000000  //DDRSS_PHY_777_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC28 0x00000000  //DDRSS_PHY_778_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC2C 0x00000000  //DDRSS_PHY_779_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC30 0x00000000  //DDRSS_PHY_780_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC34 0x00DCBA98  //DDRSS_PHY_781_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC38 0x00000000  //DDRSS_PHY_782_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC3C 0x00000000  //DDRSS_PHY_783_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC40 0x00000000  //DDRSS_PHY_784_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC44 0x00000000  //DDRSS_PHY_785_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC48 0x00000000  //DDRSS_PHY_786_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC4C 0x00000100  //DDRSS_PHY_787_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC50 0x00000000  //DDRSS_PHY_788_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC54 0x00000000  //DDRSS_PHY_789_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC58 0x00000000  //DDRSS_PHY_790_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC5C 0x00000000  //DDRSS_PHY_791_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC60 0x00000000  //DDRSS_PHY_792_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC64 0x00000000  //DDRSS_PHY_793_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC68 0x00000000  //DDRSS_PHY_794_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC6C 0x00000000  //DDRSS_PHY_795_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC70 0x16A4A0E6  //DDRSS_PHY_796_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC74 0x103F0000  //DDRSS_PHY_797_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC78 0x000F0000  //DDRSS_PHY_798_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC7C 0x0000000F  //DDRSS_PHY_799_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC80 0x020002FF  //DDRSS_PHY_800_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC84 0x00030000  //DDRSS_PHY_801_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC88 0x00000300  //DDRSS_PHY_802_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC8C 0x00000300  //DDRSS_PHY_803_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC90 0x00000300  //DDRSS_PHY_804_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC94 0x00000300  //DDRSS_PHY_805_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC98 0x00000300  //DDRSS_PHY_806_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC9C 0x42080010  //DDRSS_PHY_807_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA0 0x0000003E  //DDRSS_PHY_808_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA4 0x00000000  //DDRSS_PHY_809_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA8 0x00000000  //DDRSS_PHY_810_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D000 0x00000100  //DDRSS_PHY_1024_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D004 0x00001000  //DDRSS_PHY_1025_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D008 0x00070000  //DDRSS_PHY_1026_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D00C 0x00000000  //DDRSS_PHY_1027_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D010 0x00000000  //DDRSS_PHY_1028_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D014 0x00000100  //DDRSS_PHY_1029_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D018 0x00000000  //DDRSS_PHY_1030_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D01C 0x00000000  //DDRSS_PHY_1031_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D020 0x00000000  //DDRSS_PHY_1032_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D024 0x00000000  //DDRSS_PHY_1033_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D028 0x00000000  //DDRSS_PHY_1034_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D02C 0x00000000  //DDRSS_PHY_1035_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D030 0x00000000  //DDRSS_PHY_1036_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D034 0x00DCBA98  //DDRSS_PHY_1037_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D038 0x00000000  //DDRSS_PHY_1038_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D03C 0x00000000  //DDRSS_PHY_1039_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D040 0x00000000  //DDRSS_PHY_1040_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D044 0x00000000  //DDRSS_PHY_1041_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D048 0x00000000  //DDRSS_PHY_1042_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D04C 0x00000100  //DDRSS_PHY_1043_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D050 0x00000000  //DDRSS_PHY_1044_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D054 0x00000000  //DDRSS_PHY_1045_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D058 0x00000000  //DDRSS_PHY_1046_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D05C 0x00000000  //DDRSS_PHY_1047_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D060 0x00000000  //DDRSS_PHY_1048_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D064 0x00000000  //DDRSS_PHY_1049_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D068 0x00000000  //DDRSS_PHY_1050_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D06C 0x00000000  //DDRSS_PHY_1051_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D070 0x2307B9AC  //DDRSS_PHY_1052_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D074 0x10030000  //DDRSS_PHY_1053_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D078 0x000F0000  //DDRSS_PHY_1054_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D07C 0x0000000F  //DDRSS_PHY_1055_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D080 0x020002FF  //DDRSS_PHY_1056_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D084 0x00030000  //DDRSS_PHY_1057_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D088 0x00000300  //DDRSS_PHY_1058_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D08C 0x00000300  //DDRSS_PHY_1059_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D090 0x00000300  //DDRSS_PHY_1060_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D094 0x00000300  //DDRSS_PHY_1061_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D098 0x00000300  //DDRSS_PHY_1062_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D09C 0x42080010  //DDRSS_PHY_1063_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A0 0x0000003E  //DDRSS_PHY_1064_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A4 0x00000000  //DDRSS_PHY_1065_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A8 0x00000000  //DDRSS_PHY_1066_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D400 0x00000000  //DDRSS_PHY_1280_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D404 0x00000000  //DDRSS_PHY_1281_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D408 0x00000000  //DDRSS_PHY_1282_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D40C 0x00000000  //DDRSS_PHY_1283_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D410 0x00000000  //DDRSS_PHY_1284_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D414 0x00000000  //DDRSS_PHY_1285_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D418 0x00050000  //DDRSS_PHY_1286_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D41C 0x04000100  //DDRSS_PHY_1287_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D420 0x00000055  //DDRSS_PHY_1288_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D424 0x00000000  //DDRSS_PHY_1289_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D428 0x06800000  //DDRSS_PHY_1290_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D42C 0x00000000  //DDRSS_PHY_1291_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D430 0x00000000  //DDRSS_PHY_1292_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D434 0x01002000  //DDRSS_PHY_1293_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D438 0x00004001  //DDRSS_PHY_1294_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D43C 0x00020028  //DDRSS_PHY_1295_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D440 0x00010100  //DDRSS_PHY_1296_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D444 0x00000001  //DDRSS_PHY_1297_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D448 0x00000000  //DDRSS_PHY_1298_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D44C 0x0F0F0E06  //DDRSS_PHY_1299_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D450 0x00010101  //DDRSS_PHY_1300_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D454 0x010F0004  //DDRSS_PHY_1301_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D458 0x00000000  //DDRSS_PHY_1302_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D45C 0x20125770  //DDRSS_PHY_1303_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D460 0x00000064  //DDRSS_PHY_1304_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D464 0x00000000  //DDRSS_PHY_1305_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D468 0x00000000  //DDRSS_PHY_1306_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D46C 0x01020103  //DDRSS_PHY_1307_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D470 0x03020102  //DDRSS_PHY_1308_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D474 0x03030303  //DDRSS_PHY_1309_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D478 0x03030303  //DDRSS_PHY_1310_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D47C 0x00040000  //DDRSS_PHY_1311_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D480 0x00005201  //DDRSS_PHY_1312_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D484 0x00000003  //DDRSS_PHY_1313_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D488 0x00010000  //DDRSS_PHY_1314_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D48C 0x00000000  //DDRSS_PHY_1315_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D490 0x00000003  //DDRSS_PHY_1316_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D494 0x00010000  //DDRSS_PHY_1317_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D498 0x00000000  //DDRSS_PHY_1318_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D49C 0x07070001  //DDRSS_PHY_1319_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A0 0x00005400  //DDRSS_PHY_1320_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A4 0x000040A2  //DDRSS_PHY_1321_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A8 0x00034890  //DDRSS_PHY_1322_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4AC 0x00014890  //DDRSS_PHY_1323_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B0 0x00014890  //DDRSS_PHY_1324_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B4 0x00014890  //DDRSS_PHY_1325_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B8 0x0001488F  //DDRSS_PHY_1326_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4BC 0x00014890  //DDRSS_PHY_1327_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C0 0x0001491E  //DDRSS_PHY_1328_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C4 0x0001491E  //DDRSS_PHY_1329_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C8 0x00014890  //DDRSS_PHY_1330_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4CC 0x00014890  //DDRSS_PHY_1331_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D0 0x00000000  //DDRSS_PHY_1332_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D4 0x00000046  //DDRSS_PHY_1333_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D8 0x00000400  //DDRSS_PHY_1334_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4DC 0x00000008  //DDRSS_PHY_1335_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E0 0x00814890  //DDRSS_PHY_1336_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E4 0x0081491E  //DDRSS_PHY_1337_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E8 0x00148900  //DDRSS_PHY_1338_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4EC 0x001491E8  //DDRSS_PHY_1339_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F0 0x00F4890F  //DDRSS_PHY_1340_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F4 0x03F491EF  //DDRSS_PHY_1341_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F8 0x00000000  //DDRSS_PHY_1342_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4FC 0x00000000  //DDRSS_PHY_1343_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D500 0xB3000000  //DDRSS_PHY_1344_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D504 0x04102006  //DDRSS_PHY_1345_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D508 0x00041020  //DDRSS_PHY_1346_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D50C 0x01C98C98  //DDRSS_PHY_1347_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D510 0x3F400000  //DDRSS_PHY_1348_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D514 0x3F3F1F3F  //DDRSS_PHY_1349_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D518 0x0000001F  //DDRSS_PHY_1350_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D51C 0x00000000  //DDRSS_PHY_1351_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D520 0x00000000  //DDRSS_PHY_1352_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D524 0x00000000  //DDRSS_PHY_1353_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D528 0x00000001  //DDRSS_PHY_1354_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D52C 0x00000000  //DDRSS_PHY_1355_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D530 0x00000000  //DDRSS_PHY_1356_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D534 0x00000000  //DDRSS_PHY_1357_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D538 0x00000000  //DDRSS_PHY_1358_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D53C 0x76543210  //DDRSS_PHY_1359_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D540 0x00000098  //DDRSS_PHY_1360_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D544 0x00000000  //DDRSS_PHY_1361_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D548 0x00000000  //DDRSS_PHY_1362_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D54C 0x00000000  //DDRSS_PHY_1363_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D550 0x00040700  //DDRSS_PHY_1364_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D554 0x00000000  //DDRSS_PHY_1365_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D558 0x00000000  //DDRSS_PHY_1366_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D55C 0x00000000  //DDRSS_PHY_1367_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D560 0x030F7102  //DDRSS_PHY_1368_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D564 0x00000100  //DDRSS_PHY_1369_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D568 0x00000000  //DDRSS_PHY_1370_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D56C 0x0001F7C2  //DDRSS_PHY_1371_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D570 0x00020002  //DDRSS_PHY_1372_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D574 0x00000000  //DDRSS_PHY_1373_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D578 0x00001142  //DDRSS_PHY_1374_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D57C 0x03020400  //DDRSS_PHY_1375_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D580 0x00000080  //DDRSS_PHY_1376_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D584 0x03900390  //DDRSS_PHY_1377_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D588 0x03900390  //DDRSS_PHY_1378_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D58C 0x03900390  //DDRSS_PHY_1379_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D590 0x03900390  //DDRSS_PHY_1380_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D594 0x03900390  //DDRSS_PHY_1381_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D598 0x03900390  //DDRSS_PHY_1382_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D59C 0x00000300  //DDRSS_PHY_1383_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A0 0x00000300  //DDRSS_PHY_1384_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A4 0x00000300  //DDRSS_PHY_1385_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A8 0x00000300  //DDRSS_PHY_1386_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5AC 0x31823FF7  //DDRSS_PHY_1387_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B0 0x00000000  //DDRSS_PHY_1388_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B4 0x0C000D3F  //DDRSS_PHY_1389_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B8 0x30000D3F  //DDRSS_PHY_1390_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5BC 0x300D3F11  //DDRSS_PHY_1391_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C0 0x01FF0000  //DDRSS_PHY_1392_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C4 0x000D3FFF  //DDRSS_PHY_1393_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C8 0x00000C11  //DDRSS_PHY_1394_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5CC 0x300D3F11  //DDRSS_PHY_1395_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D0 0x01FF0000  //DDRSS_PHY_1396_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D4 0x300C3F11  //DDRSS_PHY_1397_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D8 0x01FF0000  //DDRSS_PHY_1398_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5DC 0x300C3F11  //DDRSS_PHY_1399_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E0 0x01FF0000  //DDRSS_PHY_1400_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E4 0x300D3F11  //DDRSS_PHY_1401_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E8 0x01FF0000  //DDRSS_PHY_1402_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5EC 0x300D3F11  //DDRSS_PHY_1403_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F0 0x01FF0000  //DDRSS_PHY_1404_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F4 0x20040004  //DDRSS_PHY_1405_DATA_F0

1)  Could you pls provide some guidance?

2)  Could you pls let me know which training item is not completed?  

We also tried increasing the VDDS_DDR/VDDS_DDR_C (VDDQ/VDD on DDR chip side)  to 1.25V.   Run the same memory test program but got the similar failure:

VDDQ/VDD = 1.25V
Date: 2024-10-12
File: RTTnom40/DDR4-1600_800MHz_CL14_CWL11_RPRCD1375_XPR5_DQODT40_ODI48_board_ddrReginit.h
Delay: No
preamble: No
size: 4096
start addr: 0x80000000
.....
Fail DDR addr 0x8000655C failed. Write value: 0x00000001, read value: 0x00DB0001
.
Fail DDR addr 0x8000783C failed. Write value: 0x00000001, read value: 0x00090001
......
Fail DDR addr 0x8000D3BC failed. Write value: 0x00000001, read value: 0x00080001
....
Fail DDR addr 0x8001139C failed. Write value: 0x00000001, read value: 0x00080001
...
Fail DDR addr 0x800145BC failed. Write value: 0x00000001, read value: 0x00190001
..............
Fail DDR addr 0x8002211C failed. Write value: 0x00000001, read value: 0x00DB0001
.
Fail DDR addr 0x800232FC failed. Write value: 0x00000001, read value: 0x00080001
.....
Fail DDR addr 0x8002843C failed. Write value: 0x00000001, read value: 0x00080001
..
Fail DDR addr 0x8002A09C failed. Write value: 0x00000001, read value: 0x00DB0001
..
Fail DDR addr 0x8002C03C failed. Write value: 0x00000001, read value: 0x00080001
...............
Fail DDR addr 0x8003B59C failed. Write value: 0x0000000F, read value: 0x0008000F
.................................

By the way, could you pls let me know whether AM243x DDRSS supports the skew calibration between:

3) CLK and each lane ?

4) DQS and each DQ signal for Write operation ?

5) DQS and each DQ signal for Read operation: 

     -- each DQ can be individually delayed to optimize it with respect to the DQS ?   

     -- or Only the DQS signal can be adjusted to optimize it to all the DQ signals ?

6) And does AM243x DDRSS train a Single Vref for all DQ signals,  or Single Vref per data lane, or seperate Vref for each DQ pin ?

Looking forward to your comments. 

Thanks & regards,

Larry

Hi James,

May I know any clue you could find from the register dump?

Many Thanks!

Kevin

Hi James,

Customer followed your link below, but the downloaded file name is "board_ddrReginit.h", not the "board_5F00_ddrReginit.h".

/cfs-file/__key/communityserver-discussions-components-files/908/board_5F00_ddrReginit.h

The corresponding register dump is provided above, customer project will SOP by the end of this year, so it is quite urgent for them to debug this DDR problem, could you please provide some clue for them to move on please?

Thanks,

Kevin

Hi Kevin, it doesn't appear that you are building in the DDR configuration file correctly.  For example, the file i provided shows this:

0x020002CCU, // DDRSS_PHY_544_VAL

While the regdumps show this:

MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C880 0x020002FF  //DDRSS_PHY_544_DATA_F0

The highlighted values should not be changing since this is associated with the address driver impedance.  

How are you building your test code?  Can you confirm the board_ddrReginit.h file is getting built into the code?  Check the register above to ensure that it shows 0xCC in PHY_544

Regards,

James

Hi James,

I'm pretty sure the board_ddrReginit.h file got built into the code.  

The weird thing is most of the time the register DDRSS_PHY_544_VAL value is  0xFF in the dump with the DDR header file you provided (actually same thing happens with other header file) . 

Occasionally we got the 0xCC (as the header file) for  DDRSS_PHY_544_VAL in the dump and then the DDR write&read tests pass with no failure.

The process to get the 0xCC register dump is: 

1. In debug mode with JTAG connected,  when there is a program runaway,  in CCS reset (NOT power cycle the board)and reload the program

2. run the register dump immediately, typically the CCS responds with the error message:

DDRSS_CTL_PI_PHY_RegDump() cannot be evaluated.
Could not read 0x0F308000: execution state prevented access
   at GEL_TextOut("%x %x  //DDRSS_CTL_%d_DATA\n", 0, 0, 0, 0, (0x0F308000+(i*4)), *((unsigned int*) (0x0F308000+(i*4))), i) [AM64x_AM62x_DDRSS_RegDump.gel:75]
   at DDRSS_CTL_PI_PHY_RegDump()

3. add a breakpoint  in the program in any place, then run the program

4. once the program runs to the breakpoint, run the register dump, now we get the 0xCC for DDRSS_PHY_544_VAL in the dump

5. then remove the breakpoint and continue running the program,  the DDR write&read pass with NO failure.

6.  It seems in this case,  if the board is NOT powercycled,  reload the program and run,  we can always get the DDR write&read test passed without failures.

Any comments on this ?  

We forget to save the register dump with 0xCC.  We'll try to repeat the process and get the register dump and post it.

Regards,

Larry

Larry, when you power up the board, are you booting from any boot media (flash, sd card, etc)?  What is BOOTMODE15-0 set to?  If you are booting an image, is that image built with the latest .h file i sent? 

What program are you reloading and running?  Is this some .out file that you built?

Regards,

James

Hi James,

The board is powered up with BOOTMODE set at 1110 0001 0001 0011 (boot from QSPI  flash).  The image in the QSPI flash is built with the .h file you sent.

Then we connect to the board via JTAG in CCS.    The program we reload and run via JTAG (also built with the .h file you sent)  is the same .out file as the image in Flash, or different (Yes, we tried both cases). 

Now we can consistently reproduce the 0xCC for PHY_544 in register dump with the following code changes:

1.  The original test code main() is like this:

int main(void)
{

    System_init();
    Board_init();

    ddr_ecc_test_main(NULL);

    Board_deinit();
    System_deinit();

    return 0;
}

2. Just add System_init() and System_deinit() in the very beginning, then we can get the 0xCC for PHY_544 in the dump,  and the DDR tests pass (concecutive 4096 32bit data write and read) without failures:

int main(void)
{
    System_init();
    System_deinit();  /* can be replaced with PowerClock_deinit(); */

    System_init();
    Board_init();

    ddr_ecc_test_main(NULL);

    Board_deinit();
    System_deinit();

    return 0;
}

The DDR test also can pass with the first System_deinit() replaced by "PowerClock_deinit();".   

The register dump is:

MAIN_Cortex_R5_0_0: GEL Output: 0x0F308000 0x10460A01  //DDRSS_CTL_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308004 0x5D1AF3C3  //DDRSS_CTL_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308008 0x0171A610  //DDRSS_CTL_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30800C 0x40020A11  //DDRSS_CTL_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308010 0x00052006  //DDRSS_CTL_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308014 0x02050020  //DDRSS_CTL_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308018 0x03070101  //DDRSS_CTL_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30801C 0x00089070  //DDRSS_CTL_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308020 0x00000000  //DDRSS_CTL_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308024 0x00000000  //DDRSS_CTL_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308028 0x00000000  //DDRSS_CTL_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30802C 0x00089070  //DDRSS_CTL_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308030 0x00000000  //DDRSS_CTL_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308034 0x00000000  //DDRSS_CTL_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308038 0x00000000  //DDRSS_CTL_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30803C 0x00089070  //DDRSS_CTL_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308040 0x00000000  //DDRSS_CTL_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308044 0x00000000  //DDRSS_CTL_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308048 0x00000000  //DDRSS_CTL_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30804C 0x01010100  //DDRSS_CTL_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308050 0x01000101  //DDRSS_CTL_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308054 0x01000110  //DDRSS_CTL_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308058 0x02010002  //DDRSS_CTL_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30805C 0x00027100  //DDRSS_CTL_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308060 0x00061A80  //DDRSS_CTL_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308064 0x02550255  //DDRSS_CTL_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308068 0x00000255  //DDRSS_CTL_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30806C 0x00000000  //DDRSS_CTL_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308070 0x00000000  //DDRSS_CTL_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308074 0x00000000  //DDRSS_CTL_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308078 0x00000000  //DDRSS_CTL_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30807C 0x00000000  //DDRSS_CTL_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308080 0x00000000  //DDRSS_CTL_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308084 0x00000000  //DDRSS_CTL_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308088 0x00000000  //DDRSS_CTL_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30808C 0x00000000  //DDRSS_CTL_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308090 0x00000000  //DDRSS_CTL_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308094 0x00000000  //DDRSS_CTL_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308098 0x0400091C  //DDRSS_CTL_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30809C 0x1C1C1C1C  //DDRSS_CTL_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A0 0x0400091C  //DDRSS_CTL_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A4 0x1C1C1C1C  //DDRSS_CTL_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A8 0x0400091C  //DDRSS_CTL_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080AC 0x1C1C1C1C  //DDRSS_CTL_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B0 0x05050404  //DDRSS_CTL_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B4 0x00002606  //DDRSS_CTL_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B8 0x0602001B  //DDRSS_CTL_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080BC 0x05001D0C  //DDRSS_CTL_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C0 0x00260605  //DDRSS_CTL_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C4 0x0602001B  //DDRSS_CTL_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C8 0x05001D0C  //DDRSS_CTL_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080CC 0x00260605  //DDRSS_CTL_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D0 0x0602001B  //DDRSS_CTL_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D4 0x07001D0C  //DDRSS_CTL_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D8 0x00180807  //DDRSS_CTL_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080DC 0x0400DB60  //DDRSS_CTL_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E0 0x07070009  //DDRSS_CTL_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E4 0x00001808  //DDRSS_CTL_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E8 0x0400DB60  //DDRSS_CTL_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080EC 0x07070009  //DDRSS_CTL_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F0 0x00001808  //DDRSS_CTL_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F4 0x0400DB60  //DDRSS_CTL_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F8 0x03000009  //DDRSS_CTL_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080FC 0x0D0D0002  //DDRSS_CTL_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308100 0x0D0D0D0D  //DDRSS_CTL_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308104 0x01010000  //DDRSS_CTL_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308108 0x031A1A1A  //DDRSS_CTL_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30810C 0x0C0C0C0C  //DDRSS_CTL_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308110 0x00000C0C  //DDRSS_CTL_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308114 0x00000101  //DDRSS_CTL_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308118 0x00000000  //DDRSS_CTL_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30811C 0x01000000  //DDRSS_CTL_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308120 0x00D00803  //DDRSS_CTL_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308124 0x00001860  //DDRSS_CTL_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308128 0x000000D0  //DDRSS_CTL_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30812C 0x00001860  //DDRSS_CTL_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308130 0x000000D0  //DDRSS_CTL_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308134 0x00001860  //DDRSS_CTL_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308138 0x00000005  //DDRSS_CTL_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30813C 0x00000000  //DDRSS_CTL_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308140 0x00000000  //DDRSS_CTL_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308144 0x00000000  //DDRSS_CTL_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308148 0x00000000  //DDRSS_CTL_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30814C 0x00000000  //DDRSS_CTL_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308150 0x00000000  //DDRSS_CTL_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308154 0x00000000  //DDRSS_CTL_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308158 0x00000000  //DDRSS_CTL_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30815C 0x00090009  //DDRSS_CTL_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308160 0x00000009  //DDRSS_CTL_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308164 0x00000000  //DDRSS_CTL_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308168 0x00000000  //DDRSS_CTL_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30816C 0x00000000  //DDRSS_CTL_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308170 0x00000000  //DDRSS_CTL_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308174 0x00000000  //DDRSS_CTL_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308178 0x00010001  //DDRSS_CTL_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30817C 0x00025501  //DDRSS_CTL_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308180 0x025500D8  //DDRSS_CTL_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308184 0x025500D8  //DDRSS_CTL_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308188 0x00D800D8  //DDRSS_CTL_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30818C 0x00D800D8  //DDRSS_CTL_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308190 0x00000000  //DDRSS_CTL_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308194 0x00000000  //DDRSS_CTL_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308198 0x00000000  //DDRSS_CTL_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30819C 0x00000000  //DDRSS_CTL_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A0 0x00000000  //DDRSS_CTL_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A4 0x00000000  //DDRSS_CTL_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A8 0x03010000  //DDRSS_CTL_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081AC 0x00010000  //DDRSS_CTL_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B0 0x00000000  //DDRSS_CTL_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B4 0x01000000  //DDRSS_CTL_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B8 0x80104002  //DDRSS_CTL_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081BC 0x00040003  //DDRSS_CTL_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C0 0x00040005  //DDRSS_CTL_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C4 0x00030000  //DDRSS_CTL_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C8 0x00050004  //DDRSS_CTL_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081CC 0x00000004  //DDRSS_CTL_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D0 0x00040003  //DDRSS_CTL_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D4 0x00040005  //DDRSS_CTL_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D8 0x00000000  //DDRSS_CTL_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081DC 0x00061800  //DDRSS_CTL_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E0 0x00061800  //DDRSS_CTL_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E4 0x00061800  //DDRSS_CTL_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E8 0x00061800  //DDRSS_CTL_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081EC 0x00061800  //DDRSS_CTL_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F0 0x00000000  //DDRSS_CTL_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F4 0x0000AAA0  //DDRSS_CTL_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F8 0x00061800  //DDRSS_CTL_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081FC 0x00061800  //DDRSS_CTL_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308200 0x00061800  //DDRSS_CTL_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308204 0x00061800  //DDRSS_CTL_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308208 0x00061800  //DDRSS_CTL_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30820C 0x00000000  //DDRSS_CTL_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308210 0x0000AAA0  //DDRSS_CTL_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308214 0x00061800  //DDRSS_CTL_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308218 0x00061800  //DDRSS_CTL_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30821C 0x00061800  //DDRSS_CTL_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308220 0x00061800  //DDRSS_CTL_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308224 0x00061800  //DDRSS_CTL_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308228 0x00000000  //DDRSS_CTL_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30822C 0x0000AAA0  //DDRSS_CTL_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308230 0x00000000  //DDRSS_CTL_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308234 0x00000000  //DDRSS_CTL_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308238 0x00000000  //DDRSS_CTL_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30823C 0x00000000  //DDRSS_CTL_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308240 0x00000000  //DDRSS_CTL_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308244 0x00000000  //DDRSS_CTL_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308248 0x00000000  //DDRSS_CTL_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30824C 0x00000000  //DDRSS_CTL_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308250 0x00000000  //DDRSS_CTL_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308254 0x00000000  //DDRSS_CTL_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308258 0x00000000  //DDRSS_CTL_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30825C 0x00000000  //DDRSS_CTL_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308260 0x00000000  //DDRSS_CTL_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308264 0x00000000  //DDRSS_CTL_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308268 0x00000000  //DDRSS_CTL_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30826C 0x00000000  //DDRSS_CTL_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308270 0x080C0000  //DDRSS_CTL_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308274 0x080C080C  //DDRSS_CTL_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308278 0x00000000  //DDRSS_CTL_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30827C 0x07010A09  //DDRSS_CTL_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308280 0x000E0A09  //DDRSS_CTL_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308284 0x010A0900  //DDRSS_CTL_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308288 0x0E0A0907  //DDRSS_CTL_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30828C 0x0A090000  //DDRSS_CTL_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308290 0x0A090701  //DDRSS_CTL_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308294 0x0000080E  //DDRSS_CTL_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308298 0x00040003  //DDRSS_CTL_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30829C 0x00004007  //DDRSS_CTL_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A0 0x00000000  //DDRSS_CTL_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A4 0x00000000  //DDRSS_CTL_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A8 0x00000000  //DDRSS_CTL_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082AC 0x00000000  //DDRSS_CTL_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B0 0x00000000  //DDRSS_CTL_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B4 0x00000000  //DDRSS_CTL_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B8 0x01000000  //DDRSS_CTL_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082BC 0x00000000  //DDRSS_CTL_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C0 0x00001500  //DDRSS_CTL_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C4 0x0000100E  //DDRSS_CTL_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C8 0x00000000  //DDRSS_CTL_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082CC 0x00000000  //DDRSS_CTL_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D0 0x00000001  //DDRSS_CTL_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D4 0x00000002  //DDRSS_CTL_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D8 0x00000C00  //DDRSS_CTL_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082DC 0x00001000  //DDRSS_CTL_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E0 0x00000C00  //DDRSS_CTL_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E4 0x00001000  //DDRSS_CTL_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E8 0x00000C00  //DDRSS_CTL_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082EC 0x00001000  //DDRSS_CTL_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F0 0x00000000  //DDRSS_CTL_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F4 0x00000000  //DDRSS_CTL_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F8 0x00000000  //DDRSS_CTL_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082FC 0x00000000  //DDRSS_CTL_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308300 0x00000000  //DDRSS_CTL_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308304 0x00000000  //DDRSS_CTL_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308308 0x00000000  //DDRSS_CTL_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30830C 0x00000000  //DDRSS_CTL_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308310 0x00000000  //DDRSS_CTL_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308314 0x00000000  //DDRSS_CTL_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308318 0x00000000  //DDRSS_CTL_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30831C 0x00000000  //DDRSS_CTL_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308320 0x00000000  //DDRSS_CTL_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308324 0x00000000  //DDRSS_CTL_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308328 0x00000000  //DDRSS_CTL_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30832C 0x00000000  //DDRSS_CTL_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308330 0x00042400  //DDRSS_CTL_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308334 0x00000301  //DDRSS_CTL_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308338 0x00000000  //DDRSS_CTL_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30833C 0x00000424  //DDRSS_CTL_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308340 0x00000301  //DDRSS_CTL_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308344 0x00000000  //DDRSS_CTL_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308348 0x00000424  //DDRSS_CTL_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30834C 0x00000301  //DDRSS_CTL_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308350 0x00000000  //DDRSS_CTL_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308354 0x00000424  //DDRSS_CTL_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308358 0x00000301  //DDRSS_CTL_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30835C 0x00000000  //DDRSS_CTL_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308360 0x00000424  //DDRSS_CTL_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308364 0x00000301  //DDRSS_CTL_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308368 0x00000000  //DDRSS_CTL_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30836C 0x00000424  //DDRSS_CTL_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308370 0x00000301  //DDRSS_CTL_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308374 0x00000000  //DDRSS_CTL_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308378 0x00000000  //DDRSS_CTL_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30837C 0x00000000  //DDRSS_CTL_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308380 0x00000000  //DDRSS_CTL_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308384 0x00000000  //DDRSS_CTL_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308388 0x00000000  //DDRSS_CTL_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30838C 0x00000000  //DDRSS_CTL_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308390 0x00000000  //DDRSS_CTL_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308394 0x00000000  //DDRSS_CTL_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308398 0x00000000  //DDRSS_CTL_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30839C 0x00000000  //DDRSS_CTL_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A0 0x00000000  //DDRSS_CTL_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A4 0x00000000  //DDRSS_CTL_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A8 0x00000000  //DDRSS_CTL_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083AC 0x00000000  //DDRSS_CTL_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B0 0x00001401  //DDRSS_CTL_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B4 0x00001401  //DDRSS_CTL_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B8 0x00001401  //DDRSS_CTL_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083BC 0x00001401  //DDRSS_CTL_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C0 0x00001401  //DDRSS_CTL_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C4 0x00001401  //DDRSS_CTL_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C8 0x00000493  //DDRSS_CTL_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083CC 0x00000493  //DDRSS_CTL_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D0 0x00000493  //DDRSS_CTL_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D4 0x00000493  //DDRSS_CTL_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D8 0x00000493  //DDRSS_CTL_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083DC 0x00000493  //DDRSS_CTL_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E0 0x00000000  //DDRSS_CTL_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E4 0x00000000  //DDRSS_CTL_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E8 0x00000000  //DDRSS_CTL_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083EC 0x00000000  //DDRSS_CTL_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F0 0x00000000  //DDRSS_CTL_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F4 0x00000000  //DDRSS_CTL_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F8 0x00000000  //DDRSS_CTL_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083FC 0x00000000  //DDRSS_CTL_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308400 0x00000000  //DDRSS_CTL_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308404 0x00000000  //DDRSS_CTL_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308408 0x00000000  //DDRSS_CTL_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30840C 0x00000000  //DDRSS_CTL_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308410 0x00000000  //DDRSS_CTL_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308414 0x00000000  //DDRSS_CTL_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308418 0x00000000  //DDRSS_CTL_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30841C 0x00000000  //DDRSS_CTL_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308420 0x00000000  //DDRSS_CTL_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308424 0x00000000  //DDRSS_CTL_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308428 0x00000000  //DDRSS_CTL_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30842C 0x00000000  //DDRSS_CTL_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308430 0x00000000  //DDRSS_CTL_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308434 0x00000000  //DDRSS_CTL_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308438 0x00000000  //DDRSS_CTL_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30843C 0x00000000  //DDRSS_CTL_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308440 0x00000000  //DDRSS_CTL_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308444 0x00000000  //DDRSS_CTL_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308448 0x00000000  //DDRSS_CTL_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30844C 0x00000000  //DDRSS_CTL_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308450 0x00000000  //DDRSS_CTL_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308454 0x00010000  //DDRSS_CTL_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308458 0x00000000  //DDRSS_CTL_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30845C 0x00000100  //DDRSS_CTL_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308460 0x00000000  //DDRSS_CTL_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308464 0x00000101  //DDRSS_CTL_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308468 0x00000000  //DDRSS_CTL_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30846C 0x00000000  //DDRSS_CTL_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308470 0x00000000  //DDRSS_CTL_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308474 0x00000000  //DDRSS_CTL_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308478 0x00000000  //DDRSS_CTL_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30847C 0x00000000  //DDRSS_CTL_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308480 0x00000000  //DDRSS_CTL_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308484 0x00000000  //DDRSS_CTL_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308488 0x0C181511  //DDRSS_CTL_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30848C 0x00000304  //DDRSS_CTL_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308490 0x00000000  //DDRSS_CTL_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308494 0x00000000  //DDRSS_CTL_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308498 0x00000000  //DDRSS_CTL_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30849C 0x00000000  //DDRSS_CTL_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A0 0x00000000  //DDRSS_CTL_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A4 0x00000000  //DDRSS_CTL_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A8 0x00000000  //DDRSS_CTL_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084AC 0x00000000  //DDRSS_CTL_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B0 0x00000000  //DDRSS_CTL_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B4 0x00000000  //DDRSS_CTL_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B8 0x00000000  //DDRSS_CTL_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084BC 0x00000000  //DDRSS_CTL_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C0 0x00000000  //DDRSS_CTL_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C4 0x00040000  //DDRSS_CTL_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C8 0x00800200  //DDRSS_CTL_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084CC 0x00000000  //DDRSS_CTL_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D0 0x02000400  //DDRSS_CTL_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D4 0x00000080  //DDRSS_CTL_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D8 0x00040000  //DDRSS_CTL_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084DC 0x00800200  //DDRSS_CTL_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E0 0x00000000  //DDRSS_CTL_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E4 0x00000000  //DDRSS_CTL_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E8 0x00000000  //DDRSS_CTL_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084EC 0x00000100  //DDRSS_CTL_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F0 0x01010000  //DDRSS_CTL_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F4 0x00000202  //DDRSS_CTL_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F8 0x0FFF0000  //DDRSS_CTL_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084FC 0x000FFF00  //DDRSS_CTL_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308500 0xFFFFFFFF  //DDRSS_CTL_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308504 0x00FFFF00  //DDRSS_CTL_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308508 0x0A000000  //DDRSS_CTL_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30850C 0x0001FFFF  //DDRSS_CTL_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308510 0x01010101  //DDRSS_CTL_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308514 0x01010101  //DDRSS_CTL_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308518 0x00000118  //DDRSS_CTL_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30851C 0x00000C01  //DDRSS_CTL_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308520 0x00000000  //DDRSS_CTL_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308524 0x00000000  //DDRSS_CTL_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308528 0x00000000  //DDRSS_CTL_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30852C 0x01000000  //DDRSS_CTL_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308530 0x00000100  //DDRSS_CTL_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308534 0x00010000  //DDRSS_CTL_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308538 0x00000000  //DDRSS_CTL_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30853C 0x00000000  //DDRSS_CTL_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308540 0x00000000  //DDRSS_CTL_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308544 0x00000000  //DDRSS_CTL_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308548 0x00000000  //DDRSS_CTL_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30854C 0x00000000  //DDRSS_CTL_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308550 0x00000000  //DDRSS_CTL_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308554 0x00000000  //DDRSS_CTL_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308558 0x00000000  //DDRSS_CTL_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30855C 0x00000000  //DDRSS_CTL_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308560 0x00000000  //DDRSS_CTL_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308564 0x00000000  //DDRSS_CTL_345_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308568 0x00000000  //DDRSS_CTL_346_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30856C 0x00000000  //DDRSS_CTL_347_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308570 0x00000000  //DDRSS_CTL_348_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308574 0x00000000  //DDRSS_CTL_349_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308578 0x00000000  //DDRSS_CTL_350_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30857C 0x00000000  //DDRSS_CTL_351_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308580 0x00000000  //DDRSS_CTL_352_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308584 0x00000000  //DDRSS_CTL_353_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308588 0x00000000  //DDRSS_CTL_354_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30858C 0x00000000  //DDRSS_CTL_355_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308590 0x00000000  //DDRSS_CTL_356_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308594 0x00000000  //DDRSS_CTL_357_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308598 0x00000000  //DDRSS_CTL_358_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30859C 0x00000000  //DDRSS_CTL_359_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A0 0x00000000  //DDRSS_CTL_360_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A4 0x00000000  //DDRSS_CTL_361_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A8 0x00000000  //DDRSS_CTL_362_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085AC 0x00000000  //DDRSS_CTL_363_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B0 0x00000000  //DDRSS_CTL_364_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B4 0x00000000  //DDRSS_CTL_365_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B8 0x00000000  //DDRSS_CTL_366_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085BC 0x00000000  //DDRSS_CTL_367_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C0 0x00000000  //DDRSS_CTL_368_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C4 0x00000000  //DDRSS_CTL_369_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C8 0x0C000000  //DDRSS_CTL_370_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085CC 0x060C0606  //DDRSS_CTL_371_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D0 0x06060C06  //DDRSS_CTL_372_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D4 0x00010101  //DDRSS_CTL_373_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D8 0x02000000  //DDRSS_CTL_374_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085DC 0x05020101  //DDRSS_CTL_375_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E0 0x00000505  //DDRSS_CTL_376_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E4 0x02020200  //DDRSS_CTL_377_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E8 0x02020202  //DDRSS_CTL_378_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085EC 0x02020202  //DDRSS_CTL_379_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F0 0x02020202  //DDRSS_CTL_380_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F4 0x00000000  //DDRSS_CTL_381_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F8 0x00000000  //DDRSS_CTL_382_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085FC 0x04000100  //DDRSS_CTL_383_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308600 0x1E000304  //DDRSS_CTL_384_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308604 0x000030C0  //DDRSS_CTL_385_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308608 0x00000200  //DDRSS_CTL_386_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30860C 0x00000200  //DDRSS_CTL_387_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308610 0x00000200  //DDRSS_CTL_388_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308614 0x00000200  //DDRSS_CTL_389_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308618 0x0000DB60  //DDRSS_CTL_390_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30861C 0x0001E780  //DDRSS_CTL_391_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308620 0x0C0D0302  //DDRSS_CTL_392_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308624 0x001E090A  //DDRSS_CTL_393_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308628 0x000030C0  //DDRSS_CTL_394_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30862C 0x00000200  //DDRSS_CTL_395_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308630 0x00000200  //DDRSS_CTL_396_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308634 0x00000200  //DDRSS_CTL_397_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308638 0x00000200  //DDRSS_CTL_398_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30863C 0x0000DB60  //DDRSS_CTL_399_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308640 0x0001E780  //DDRSS_CTL_400_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308644 0x0C0D0302  //DDRSS_CTL_401_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308648 0x001E090A  //DDRSS_CTL_402_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30864C 0x000030C0  //DDRSS_CTL_403_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308650 0x00000200  //DDRSS_CTL_404_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308654 0x00000200  //DDRSS_CTL_405_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308658 0x00000200  //DDRSS_CTL_406_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30865C 0x00000200  //DDRSS_CTL_407_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308660 0x0000DB60  //DDRSS_CTL_408_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308664 0x0001E780  //DDRSS_CTL_409_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308668 0x0C0D0302  //DDRSS_CTL_410_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30866C 0x0000090A  //DDRSS_CTL_411_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308670 0x00000000  //DDRSS_CTL_412_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308674 0x0302000A  //DDRSS_CTL_413_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308678 0x01000500  //DDRSS_CTL_414_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30867C 0x01010001  //DDRSS_CTL_415_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308680 0x00010001  //DDRSS_CTL_416_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308684 0x01010001  //DDRSS_CTL_417_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308688 0x02010000  //DDRSS_CTL_418_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30868C 0x00000200  //DDRSS_CTL_419_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308690 0x02000201  //DDRSS_CTL_420_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308694 0x00000000  //DDRSS_CTL_421_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308698 0x00202020  //DDRSS_CTL_422_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A000 0x00000A01  //DDRSS_PI_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A004 0xAE8D79E2  //DDRSS_PI_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A008 0x0714B570  //DDRSS_PI_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A00C 0x01011387  //DDRSS_PI_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A010 0x00000001  //DDRSS_PI_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A014 0x00010064  //DDRSS_PI_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A018 0x00000000  //DDRSS_PI_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A01C 0x00000000  //DDRSS_PI_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A020 0x00000000  //DDRSS_PI_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A024 0x00000003  //DDRSS_PI_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A028 0x0000000F  //DDRSS_PI_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A02C 0x00000000  //DDRSS_PI_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A030 0x00000000  //DDRSS_PI_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A034 0x00010001  //DDRSS_PI_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A038 0x00000000  //DDRSS_PI_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A03C 0x00010001  //DDRSS_PI_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A040 0x00000005  //DDRSS_PI_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A044 0x00010000  //DDRSS_PI_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A048 0x00000000  //DDRSS_PI_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A04C 0x00000000  //DDRSS_PI_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A050 0x00000000  //DDRSS_PI_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A054 0x00000000  //DDRSS_PI_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A058 0x00000000  //DDRSS_PI_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A05C 0x00000000  //DDRSS_PI_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A060 0x280D0001  //DDRSS_PI_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A064 0x00000000  //DDRSS_PI_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A068 0x00010000  //DDRSS_PI_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A06C 0x00003200  //DDRSS_PI_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A070 0x00000000  //DDRSS_PI_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A074 0x00000000  //DDRSS_PI_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A078 0x00060602  //DDRSS_PI_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A07C 0x00000000  //DDRSS_PI_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A080 0x00000000  //DDRSS_PI_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A084 0x00000000  //DDRSS_PI_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A088 0x00000001  //DDRSS_PI_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A08C 0x00000055  //DDRSS_PI_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A090 0x000000AA  //DDRSS_PI_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A094 0x000000AD  //DDRSS_PI_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A098 0x00000052  //DDRSS_PI_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A09C 0x0000006A  //DDRSS_PI_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A0 0x00000095  //DDRSS_PI_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A4 0x00000095  //DDRSS_PI_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A8 0x000000AD  //DDRSS_PI_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0AC 0x00000000  //DDRSS_PI_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B0 0x00000000  //DDRSS_PI_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B4 0x00010100  //DDRSS_PI_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B8 0x00000014  //DDRSS_PI_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0BC 0x000007D0  //DDRSS_PI_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C0 0x00000300  //DDRSS_PI_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C4 0x00000000  //DDRSS_PI_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C8 0x00000000  //DDRSS_PI_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0CC 0x01000000  //DDRSS_PI_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D0 0x00010101  //DDRSS_PI_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D4 0x0100090C  //DDRSS_PI_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D8 0x00000000  //DDRSS_PI_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0DC 0x00010000  //DDRSS_PI_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E0 0x00000000  //DDRSS_PI_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E4 0x00000000  //DDRSS_PI_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E8 0x00000000  //DDRSS_PI_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0EC 0x00000000  //DDRSS_PI_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F0 0x00001400  //DDRSS_PI_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F4 0x00000000  //DDRSS_PI_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F8 0x01000000  //DDRSS_PI_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0FC 0x00000404  //DDRSS_PI_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A100 0x00000001  //DDRSS_PI_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A104 0x0001010E  //DDRSS_PI_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A108 0x02040100  //DDRSS_PI_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A10C 0x00010000  //DDRSS_PI_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A110 0x00000034  //DDRSS_PI_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A114 0x00000000  //DDRSS_PI_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A118 0x00000000  //DDRSS_PI_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A11C 0x00000000  //DDRSS_PI_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A120 0x00000000  //DDRSS_PI_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A124 0x00000000  //DDRSS_PI_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A128 0x00000000  //DDRSS_PI_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A12C 0x00000005  //DDRSS_PI_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A130 0x01000000  //DDRSS_PI_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A134 0x04020100  //DDRSS_PI_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A138 0x00020000  //DDRSS_PI_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A13C 0x00010002  //DDRSS_PI_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A140 0x00000001  //DDRSS_PI_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A144 0x00020001  //DDRSS_PI_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A148 0x00020002  //DDRSS_PI_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A14C 0x29C02000  //DDRSS_PI_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A150 0x00000000  //DDRSS_PI_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A154 0x00000000  //DDRSS_PI_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A158 0x00000000  //DDRSS_PI_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A15C 0x00000000  //DDRSS_PI_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A160 0x00000000  //DDRSS_PI_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A164 0x00000000  //DDRSS_PI_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A168 0x00000000  //DDRSS_PI_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A16C 0x00000300  //DDRSS_PI_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A170 0x0A090B0C  //DDRSS_PI_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A174 0x04060708  //DDRSS_PI_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A178 0x01000005  //DDRSS_PI_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A17C 0x00000800  //DDRSS_PI_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A180 0x00000000  //DDRSS_PI_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A184 0x00010008  //DDRSS_PI_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A188 0x00000000  //DDRSS_PI_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A18C 0x0000AA00  //DDRSS_PI_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A190 0x00000000  //DDRSS_PI_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A194 0x00010000  //DDRSS_PI_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A198 0x00000000  //DDRSS_PI_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A19C 0x00000000  //DDRSS_PI_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A0 0x00000000  //DDRSS_PI_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A4 0x00000000  //DDRSS_PI_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A8 0x00000000  //DDRSS_PI_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1AC 0x00000000  //DDRSS_PI_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B0 0x00000000  //DDRSS_PI_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B4 0x00000000  //DDRSS_PI_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B8 0x00000000  //DDRSS_PI_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1BC 0x00000000  //DDRSS_PI_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C0 0x00000000  //DDRSS_PI_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C4 0x00000000  //DDRSS_PI_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C8 0x00000000  //DDRSS_PI_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1CC 0x00000000  //DDRSS_PI_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D0 0x00000000  //DDRSS_PI_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D4 0x00000000  //DDRSS_PI_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D8 0x00000000  //DDRSS_PI_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1DC 0x00000000  //DDRSS_PI_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E0 0x00000000  //DDRSS_PI_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E4 0x00000000  //DDRSS_PI_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E8 0x00000000  //DDRSS_PI_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1EC 0x00000000  //DDRSS_PI_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F0 0x00000008  //DDRSS_PI_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F4 0x00000000  //DDRSS_PI_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F8 0x00000000  //DDRSS_PI_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1FC 0x00000000  //DDRSS_PI_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A200 0x00000000  //DDRSS_PI_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A204 0x00000000  //DDRSS_PI_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A208 0x00000000  //DDRSS_PI_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A20C 0x00000000  //DDRSS_PI_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A210 0x00000000  //DDRSS_PI_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A214 0x00010100  //DDRSS_PI_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A218 0x00000000  //DDRSS_PI_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A21C 0x00000000  //DDRSS_PI_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A220 0x00027100  //DDRSS_PI_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A224 0x00061A80  //DDRSS_PI_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A228 0x00000100  //DDRSS_PI_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A22C 0x00000000  //DDRSS_PI_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A230 0x00000000  //DDRSS_PI_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A234 0x00000000  //DDRSS_PI_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A238 0x00000000  //DDRSS_PI_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A23C 0x00000000  //DDRSS_PI_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A240 0x01000000  //DDRSS_PI_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A244 0xC1010003  //DDRSS_PI_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A248 0x02000101  //DDRSS_PI_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A24C 0x01030101  //DDRSS_PI_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A250 0x00010400  //DDRSS_PI_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A254 0x06000105  //DDRSS_PI_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A258 0x01070001  //DDRSS_PI_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A25C 0x00000010  //DDRSS_PI_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A260 0x00000000  //DDRSS_PI_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A264 0x00000001  //DDRSS_PI_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A268 0x00010000  //DDRSS_PI_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A26C 0x00000000  //DDRSS_PI_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A270 0x00000000  //DDRSS_PI_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A274 0x00000000  //DDRSS_PI_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A278 0x00000000  //DDRSS_PI_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A27C 0x00010000  //DDRSS_PI_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A280 0x00000004  //DDRSS_PI_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A284 0x00000000  //DDRSS_PI_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A288 0x00000000  //DDRSS_PI_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A28C 0x00000000  //DDRSS_PI_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A290 0x00007800  //DDRSS_PI_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A294 0x00780078  //DDRSS_PI_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A298 0x00141414  //DDRSS_PI_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A29C 0x0000003A  //DDRSS_PI_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A0 0x0000003A  //DDRSS_PI_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A4 0x0004003A  //DDRSS_PI_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A8 0x04000400  //DDRSS_PI_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2AC 0xC8040009  //DDRSS_PI_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B0 0x0400091C  //DDRSS_PI_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B4 0x00091CC8  //DDRSS_PI_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B8 0x001CC804  //DDRSS_PI_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2BC 0x000000D0  //DDRSS_PI_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C0 0x00001860  //DDRSS_PI_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C4 0x000000D0  //DDRSS_PI_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C8 0x00001860  //DDRSS_PI_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2CC 0x000000D0  //DDRSS_PI_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D0 0x04001860  //DDRSS_PI_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D4 0x01010404  //DDRSS_PI_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D8 0x00001901  //DDRSS_PI_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2DC 0x00190019  //DDRSS_PI_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E0 0x010C010C  //DDRSS_PI_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E4 0x0000010C  //DDRSS_PI_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E8 0x00000000  //DDRSS_PI_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2EC 0x05000000  //DDRSS_PI_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F0 0x01010505  //DDRSS_PI_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F4 0x01010101  //DDRSS_PI_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F8 0x00181818  //DDRSS_PI_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2FC 0x00000000  //DDRSS_PI_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A300 0x00000000  //DDRSS_PI_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A304 0x0D000000  //DDRSS_PI_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A308 0x0A0A0D0D  //DDRSS_PI_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A30C 0x0303030A  //DDRSS_PI_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A310 0x00000000  //DDRSS_PI_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A314 0x00000000  //DDRSS_PI_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A318 0x00000000  //DDRSS_PI_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A31C 0x00000000  //DDRSS_PI_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A320 0x00000000  //DDRSS_PI_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A324 0x00000000  //DDRSS_PI_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A328 0x00000000  //DDRSS_PI_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A32C 0x00000000  //DDRSS_PI_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A330 0x00000000  //DDRSS_PI_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A334 0x00000000  //DDRSS_PI_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A338 0x00000000  //DDRSS_PI_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A33C 0x00000000  //DDRSS_PI_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A340 0x00000000  //DDRSS_PI_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A344 0x0D090000  //DDRSS_PI_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A348 0x0D09000D  //DDRSS_PI_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A34C 0x0D09000D  //DDRSS_PI_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A350 0x0000000D  //DDRSS_PI_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A354 0x00000000  //DDRSS_PI_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A358 0x00000000  //DDRSS_PI_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A35C 0x00000000  //DDRSS_PI_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A360 0x00000000  //DDRSS_PI_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A364 0x16000000  //DDRSS_PI_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A368 0x001600C8  //DDRSS_PI_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A36C 0x001600C8  //DDRSS_PI_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A370 0x010100C8  //DDRSS_PI_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A374 0x00001B01  //DDRSS_PI_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A378 0x1F0F0053  //DDRSS_PI_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A37C 0x05000001  //DDRSS_PI_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A380 0x001B0A0D  //DDRSS_PI_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A384 0x1F0F0053  //DDRSS_PI_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A388 0x05000001  //DDRSS_PI_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A38C 0x001B0A0D  //DDRSS_PI_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A390 0x1F0F0053  //DDRSS_PI_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A394 0x05000001  //DDRSS_PI_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A398 0x00010A0D  //DDRSS_PI_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A39C 0x0D0C0700  //DDRSS_PI_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A0 0x000D0605  //DDRSS_PI_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A4 0x0000C570  //DDRSS_PI_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A8 0x0000001B  //DDRSS_PI_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3AC 0x180A0800  //DDRSS_PI_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B0 0x0C071C1C  //DDRSS_PI_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B4 0x0D06050D  //DDRSS_PI_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B8 0x0000C570  //DDRSS_PI_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3BC 0x0000001B  //DDRSS_PI_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C0 0x180A0800  //DDRSS_PI_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C4 0x0C071C1C  //DDRSS_PI_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C8 0x0D06050D  //DDRSS_PI_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3CC 0x0000C570  //DDRSS_PI_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D0 0x0000001B  //DDRSS_PI_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D4 0x180A0800  //DDRSS_PI_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D8 0x00001C1C  //DDRSS_PI_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3DC 0x000030C0  //DDRSS_PI_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E0 0x0001E780  //DDRSS_PI_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E4 0x000030C0  //DDRSS_PI_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E8 0x0001E780  //DDRSS_PI_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3EC 0x000030C0  //DDRSS_PI_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F0 0x0001E780  //DDRSS_PI_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F4 0x02550255  //DDRSS_PI_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F8 0x03030255  //DDRSS_PI_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3FC 0x00025503  //DDRSS_PI_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A400 0x02550255  //DDRSS_PI_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A404 0x0C080C08  //DDRSS_PI_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A408 0x00000C08  //DDRSS_PI_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A40C 0x00089070  //DDRSS_PI_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A410 0x00000000  //DDRSS_PI_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A414 0x00000000  //DDRSS_PI_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A418 0x00000000  //DDRSS_PI_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A41C 0x000000D8  //DDRSS_PI_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A420 0x00089070  //DDRSS_PI_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A424 0x00000000  //DDRSS_PI_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A428 0x00000000  //DDRSS_PI_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A42C 0x00000000  //DDRSS_PI_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A430 0x000000D8  //DDRSS_PI_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A434 0x00089070  //DDRSS_PI_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A438 0x00000000  //DDRSS_PI_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A43C 0x00000000  //DDRSS_PI_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A440 0x00000000  //DDRSS_PI_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A444 0x020000D8  //DDRSS_PI_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A448 0x00000080  //DDRSS_PI_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A44C 0x00020000  //DDRSS_PI_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A450 0x00000080  //DDRSS_PI_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A454 0x00020000  //DDRSS_PI_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A458 0x00000080  //DDRSS_PI_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A45C 0x00000000  //DDRSS_PI_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A460 0x00000000  //DDRSS_PI_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A464 0x00040404  //DDRSS_PI_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A468 0x00000000  //DDRSS_PI_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A46C 0x02010102  //DDRSS_PI_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A470 0x67676767  //DDRSS_PI_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A474 0x00000202  //DDRSS_PI_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A478 0x00000000  //DDRSS_PI_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A47C 0x00000000  //DDRSS_PI_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A480 0x00000000  //DDRSS_PI_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A484 0x00000000  //DDRSS_PI_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A488 0x00000000  //DDRSS_PI_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A48C 0x0D100F00  //DDRSS_PI_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A490 0x0003020E  //DDRSS_PI_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A494 0x00000001  //DDRSS_PI_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A498 0x01000000  //DDRSS_PI_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A49C 0x00020201  //DDRSS_PI_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A0 0x00000000  //DDRSS_PI_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A4 0x00000424  //DDRSS_PI_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A8 0x00000301  //DDRSS_PI_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4AC 0x00000000  //DDRSS_PI_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B0 0x00000000  //DDRSS_PI_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B4 0x00000000  //DDRSS_PI_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B8 0x00001401  //DDRSS_PI_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4BC 0x00000493  //DDRSS_PI_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C0 0x00000000  //DDRSS_PI_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C4 0x00000424  //DDRSS_PI_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C8 0x00000301  //DDRSS_PI_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4CC 0x00000000  //DDRSS_PI_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D0 0x00000000  //DDRSS_PI_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D4 0x00000000  //DDRSS_PI_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D8 0x00001401  //DDRSS_PI_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4DC 0x00000493  //DDRSS_PI_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E0 0x00000000  //DDRSS_PI_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E4 0x00000424  //DDRSS_PI_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E8 0x00000301  //DDRSS_PI_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4EC 0x00000000  //DDRSS_PI_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F0 0x00000000  //DDRSS_PI_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F4 0x00000000  //DDRSS_PI_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F8 0x00001401  //DDRSS_PI_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4FC 0x00000493  //DDRSS_PI_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A500 0x00000000  //DDRSS_PI_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A504 0x00000424  //DDRSS_PI_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A508 0x00000301  //DDRSS_PI_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A50C 0x00000000  //DDRSS_PI_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A510 0x00000000  //DDRSS_PI_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A514 0x00000000  //DDRSS_PI_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A518 0x00001401  //DDRSS_PI_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A51C 0x00000493  //DDRSS_PI_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A520 0x00000000  //DDRSS_PI_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A524 0x00000424  //DDRSS_PI_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A528 0x00000301  //DDRSS_PI_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A52C 0x00000000  //DDRSS_PI_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A530 0x00000000  //DDRSS_PI_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A534 0x00000000  //DDRSS_PI_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A538 0x00001401  //DDRSS_PI_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A53C 0x00000493  //DDRSS_PI_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A540 0x00000000  //DDRSS_PI_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A544 0x00000424  //DDRSS_PI_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A548 0x00000301  //DDRSS_PI_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A54C 0x00000000  //DDRSS_PI_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A550 0x00000000  //DDRSS_PI_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A554 0x00000000  //DDRSS_PI_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A558 0x00001401  //DDRSS_PI_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A55C 0x00000493  //DDRSS_PI_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A560 0x00000000  //DDRSS_PI_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C000 0x04C00000  //DDRSS_PHY_0_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C004 0x00000000  //DDRSS_PHY_1_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C008 0x00000200  //DDRSS_PHY_2_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C00C 0x00000000  //DDRSS_PHY_3_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C010 0x00000000  //DDRSS_PHY_4_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C014 0x00000000  //DDRSS_PHY_5_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C018 0x00000000  //DDRSS_PHY_6_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C01C 0x00000000  //DDRSS_PHY_7_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C020 0x00000001  //DDRSS_PHY_8_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C024 0x00000000  //DDRSS_PHY_9_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C028 0x000C0000  //DDRSS_PHY_10_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C02C 0x010101FF  //DDRSS_PHY_11_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C030 0x00010000  //DDRSS_PHY_12_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C034 0x00C03C04  //DDRSS_PHY_13_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C038 0x00CC0008  //DDRSS_PHY_14_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C03C 0x00660201  //DDRSS_PHY_15_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C040 0x00000000  //DDRSS_PHY_16_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C044 0x00000000  //DDRSS_PHY_17_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C048 0x00000000  //DDRSS_PHY_18_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C04C 0x0000AAAA  //DDRSS_PHY_19_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C050 0x00005555  //DDRSS_PHY_20_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C054 0x0000B5B5  //DDRSS_PHY_21_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C058 0x00004A4A  //DDRSS_PHY_22_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C05C 0x00005656  //DDRSS_PHY_23_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C060 0x0000A9A9  //DDRSS_PHY_24_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C064 0x0000B7B7  //DDRSS_PHY_25_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C068 0x00004848  //DDRSS_PHY_26_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C06C 0x00000000  //DDRSS_PHY_27_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C070 0x00000000  //DDRSS_PHY_28_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C074 0x08000000  //DDRSS_PHY_29_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C078 0x0F000008  //DDRSS_PHY_30_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C07C 0x00000F0F  //DDRSS_PHY_31_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C080 0x00E4E400  //DDRSS_PHY_32_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C084 0x00070820  //DDRSS_PHY_33_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C088 0x000C0020  //DDRSS_PHY_34_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C08C 0x00062000  //DDRSS_PHY_35_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C090 0x00000000  //DDRSS_PHY_36_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C094 0x55555555  //DDRSS_PHY_37_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C098 0xAAAAAAAA  //DDRSS_PHY_38_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C09C 0x55555555  //DDRSS_PHY_39_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A0 0xAAAAAAAA  //DDRSS_PHY_40_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A4 0x00005555  //DDRSS_PHY_41_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A8 0x01000100  //DDRSS_PHY_42_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0AC 0x00800180  //DDRSS_PHY_43_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B0 0x00000000  //DDRSS_PHY_44_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B4 0x00100000  //DDRSS_PHY_45_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B8 0x00000000  //DDRSS_PHY_46_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0BC 0x06070010  //DDRSS_PHY_47_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C0 0x00000006  //DDRSS_PHY_48_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C4 0x00000100  //DDRSS_PHY_49_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C8 0x00300024  //DDRSS_PHY_50_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0CC 0x00000FFF  //DDRSS_PHY_51_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D0 0x00000000  //DDRSS_PHY_52_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D4 0x02B802AC  //DDRSS_PHY_53_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D8 0x00000030  //DDRSS_PHY_54_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0DC 0x01200030  //DDRSS_PHY_55_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E0 0x00000000  //DDRSS_PHY_56_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E4 0x0C000000  //DDRSS_PHY_57_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E8 0x07FF0000  //DDRSS_PHY_58_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0EC 0x00000000  //DDRSS_PHY_59_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F0 0x00000000  //DDRSS_PHY_60_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F4 0x00000000  //DDRSS_PHY_61_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F8 0x00000000  //DDRSS_PHY_62_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0FC 0x00000000  //DDRSS_PHY_63_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C100 0x00000000  //DDRSS_PHY_64_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C104 0x00000004  //DDRSS_PHY_65_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C108 0x00000000  //DDRSS_PHY_66_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C10C 0x00000000  //DDRSS_PHY_67_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C110 0x00000000  //DDRSS_PHY_68_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C114 0x00000000  //DDRSS_PHY_69_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C118 0x00000000  //DDRSS_PHY_70_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C11C 0x00000000  //DDRSS_PHY_71_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C120 0x041F07FF  //DDRSS_PHY_72_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C124 0x00000000  //DDRSS_PHY_73_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C128 0x01CCB001  //DDRSS_PHY_74_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C12C 0x2000CCB0  //DDRSS_PHY_75_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C130 0x20000140  //DDRSS_PHY_76_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C134 0x07FF0200  //DDRSS_PHY_77_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C138 0x0000DD01  //DDRSS_PHY_78_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C13C 0x10100303  //DDRSS_PHY_79_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C140 0x10101010  //DDRSS_PHY_80_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C144 0x10101010  //DDRSS_PHY_81_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C148 0x00021010  //DDRSS_PHY_82_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C14C 0x00100010  //DDRSS_PHY_83_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C150 0x00100010  //DDRSS_PHY_84_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C154 0x00100010  //DDRSS_PHY_85_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C158 0x00100010  //DDRSS_PHY_86_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C15C 0x02020010  //DDRSS_PHY_87_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C160 0x51515041  //DDRSS_PHY_88_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C164 0x31804000  //DDRSS_PHY_89_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C168 0x04BC0340  //DDRSS_PHY_90_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C16C 0x01008080  //DDRSS_PHY_91_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C170 0x04050001  //DDRSS_PHY_92_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C174 0x00000504  //DDRSS_PHY_93_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C178 0x42100010  //DDRSS_PHY_94_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C17C 0x010C053E  //DDRSS_PHY_95_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C180 0x000F0C14  //DDRSS_PHY_96_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C184 0x01000140  //DDRSS_PHY_97_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C188 0x007A0120  //DDRSS_PHY_98_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C18C 0x00000C00  //DDRSS_PHY_99_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C190 0x000001CC  //DDRSS_PHY_100_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C194 0x20100200  //DDRSS_PHY_101_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C198 0x00000005  //DDRSS_PHY_102_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C19C 0x76543210  //DDRSS_PHY_103_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A0 0x00000008  //DDRSS_PHY_104_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A4 0x02800280  //DDRSS_PHY_105_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A8 0x02800280  //DDRSS_PHY_106_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1AC 0x02800280  //DDRSS_PHY_107_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B0 0x02800280  //DDRSS_PHY_108_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B4 0x002A0280  //DDRSS_PHY_109_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B8 0x0000A800  //DDRSS_PHY_110_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1BC 0x00AE00A8  //DDRSS_PHY_111_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C0 0x00A800AE  //DDRSS_PHY_112_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C4 0x00AE00A8  //DDRSS_PHY_113_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C8 0x00AE00B4  //DDRSS_PHY_114_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1CC 0x00A200B4  //DDRSS_PHY_115_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D0 0x00A200A8  //DDRSS_PHY_116_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D4 0x00A200A8  //DDRSS_PHY_117_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D8 0x00A800A8  //DDRSS_PHY_118_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1DC 0x01B200A8  //DDRSS_PHY_119_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E0 0x01000000  //DDRSS_PHY_120_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E4 0x00000000  //DDRSS_PHY_121_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E8 0x00000000  //DDRSS_PHY_122_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1EC 0x00080200  //DDRSS_PHY_123_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F0 0x00000000  //DDRSS_PHY_124_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F4 0x00000000  //DDRSS_PHY_125_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C400 0x04C00000  //DDRSS_PHY_256_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C404 0x00000000  //DDRSS_PHY_257_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C408 0x00000200  //DDRSS_PHY_258_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C40C 0x00000000  //DDRSS_PHY_259_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C410 0x00000000  //DDRSS_PHY_260_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C414 0x00000000  //DDRSS_PHY_261_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C418 0x00000000  //DDRSS_PHY_262_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C41C 0x00000000  //DDRSS_PHY_263_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C420 0x00000001  //DDRSS_PHY_264_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C424 0x00000000  //DDRSS_PHY_265_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C428 0x000C0000  //DDRSS_PHY_266_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C42C 0x010101FF  //DDRSS_PHY_267_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C430 0x00010000  //DDRSS_PHY_268_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C434 0x00C03C04  //DDRSS_PHY_269_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C438 0x00CC0008  //DDRSS_PHY_270_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C43C 0x00660201  //DDRSS_PHY_271_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C440 0x00000000  //DDRSS_PHY_272_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C444 0x00000000  //DDRSS_PHY_273_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C448 0x00000000  //DDRSS_PHY_274_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C44C 0x0000AAAA  //DDRSS_PHY_275_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C450 0x00005555  //DDRSS_PHY_276_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C454 0x0000B5B5  //DDRSS_PHY_277_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C458 0x00004A4A  //DDRSS_PHY_278_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C45C 0x00005656  //DDRSS_PHY_279_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C460 0x0000A9A9  //DDRSS_PHY_280_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C464 0x0000B7B7  //DDRSS_PHY_281_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C468 0x00004848  //DDRSS_PHY_282_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C46C 0x00000000  //DDRSS_PHY_283_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C470 0x00000000  //DDRSS_PHY_284_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C474 0x08000000  //DDRSS_PHY_285_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C478 0x0F000008  //DDRSS_PHY_286_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C47C 0x00000F0F  //DDRSS_PHY_287_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C480 0x00E4E400  //DDRSS_PHY_288_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C484 0x00070820  //DDRSS_PHY_289_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C488 0x000C0020  //DDRSS_PHY_290_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C48C 0x00062000  //DDRSS_PHY_291_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C490 0x00000000  //DDRSS_PHY_292_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C494 0x55555555  //DDRSS_PHY_293_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C498 0xAAAAAAAA  //DDRSS_PHY_294_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C49C 0x55555555  //DDRSS_PHY_295_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A0 0xAAAAAAAA  //DDRSS_PHY_296_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A4 0x00005555  //DDRSS_PHY_297_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A8 0x01000100  //DDRSS_PHY_298_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4AC 0x00800180  //DDRSS_PHY_299_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B0 0x00000000  //DDRSS_PHY_300_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B4 0x00100000  //DDRSS_PHY_301_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B8 0x00000000  //DDRSS_PHY_302_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4BC 0x06070010  //DDRSS_PHY_303_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C0 0x0000000C  //DDRSS_PHY_304_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C4 0x00010700  //DDRSS_PHY_305_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C8 0x0048003C  //DDRSS_PHY_306_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4CC 0x00000FFF  //DDRSS_PHY_307_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D0 0x00000000  //DDRSS_PHY_308_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D4 0x02AC02A0  //DDRSS_PHY_309_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D8 0x00000030  //DDRSS_PHY_310_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4DC 0x0120003C  //DDRSS_PHY_311_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E0 0x00000000  //DDRSS_PHY_312_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E4 0x0C000000  //DDRSS_PHY_313_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E8 0x07FF0000  //DDRSS_PHY_314_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4EC 0x00000000  //DDRSS_PHY_315_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F0 0x00000000  //DDRSS_PHY_316_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F4 0x00000000  //DDRSS_PHY_317_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F8 0x00000000  //DDRSS_PHY_318_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4FC 0x00000000  //DDRSS_PHY_319_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C500 0x00000000  //DDRSS_PHY_320_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C504 0x00000004  //DDRSS_PHY_321_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C508 0x00000000  //DDRSS_PHY_322_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C50C 0x00000000  //DDRSS_PHY_323_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C510 0x00000000  //DDRSS_PHY_324_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C514 0x00000000  //DDRSS_PHY_325_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C518 0x00000000  //DDRSS_PHY_326_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C51C 0x00000000  //DDRSS_PHY_327_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C520 0x041F07FF  //DDRSS_PHY_328_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C524 0x00000000  //DDRSS_PHY_329_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C528 0x01CCB001  //DDRSS_PHY_330_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C52C 0x2000CCB0  //DDRSS_PHY_331_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C530 0x20000140  //DDRSS_PHY_332_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C534 0x07FF0200  //DDRSS_PHY_333_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C538 0x0000DD01  //DDRSS_PHY_334_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C53C 0x10100303  //DDRSS_PHY_335_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C540 0x10101010  //DDRSS_PHY_336_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C544 0x10101010  //DDRSS_PHY_337_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C548 0x00021010  //DDRSS_PHY_338_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C54C 0x00100010  //DDRSS_PHY_339_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C550 0x00100010  //DDRSS_PHY_340_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C554 0x00100010  //DDRSS_PHY_341_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C558 0x00100010  //DDRSS_PHY_342_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C55C 0x02020010  //DDRSS_PHY_343_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C560 0x51515041  //DDRSS_PHY_344_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C564 0x31804000  //DDRSS_PHY_345_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C568 0x04BC0340  //DDRSS_PHY_346_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C56C 0x01008080  //DDRSS_PHY_347_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C570 0x04050001  //DDRSS_PHY_348_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C574 0x00000504  //DDRSS_PHY_349_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C578 0x42100010  //DDRSS_PHY_350_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C57C 0x010C053E  //DDRSS_PHY_351_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C580 0x000F0C14  //DDRSS_PHY_352_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C584 0x01000140  //DDRSS_PHY_353_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C588 0x007A0120  //DDRSS_PHY_354_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C58C 0x00000C00  //DDRSS_PHY_355_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C590 0x000001CC  //DDRSS_PHY_356_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C594 0x20100200  //DDRSS_PHY_357_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C598 0x00000005  //DDRSS_PHY_358_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C59C 0x76543210  //DDRSS_PHY_359_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A0 0x00000008  //DDRSS_PHY_360_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A4 0x02800280  //DDRSS_PHY_361_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A8 0x02800280  //DDRSS_PHY_362_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5AC 0x02800280  //DDRSS_PHY_363_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B0 0x02800280  //DDRSS_PHY_364_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B4 0x00420280  //DDRSS_PHY_365_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B8 0x0000AE00  //DDRSS_PHY_366_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5BC 0x00AE00B4  //DDRSS_PHY_367_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C0 0x00A800AE  //DDRSS_PHY_368_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C4 0x00B400A8  //DDRSS_PHY_369_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C8 0x00AE00B4  //DDRSS_PHY_370_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5CC 0x00AE00AE  //DDRSS_PHY_371_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D0 0x00B400B4  //DDRSS_PHY_372_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D4 0x00AE00AE  //DDRSS_PHY_373_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D8 0x00AE00AE  //DDRSS_PHY_374_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5DC 0x01A600B4  //DDRSS_PHY_375_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E0 0x01000000  //DDRSS_PHY_376_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E4 0x00000000  //DDRSS_PHY_377_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E8 0x00000000  //DDRSS_PHY_378_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5EC 0x00080200  //DDRSS_PHY_379_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F0 0x00000000  //DDRSS_PHY_380_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F4 0x00000000  //DDRSS_PHY_381_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C800 0x00000100  //DDRSS_PHY_512_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C804 0x00001000  //DDRSS_PHY_513_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C808 0x00070000  //DDRSS_PHY_514_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C80C 0x00000000  //DDRSS_PHY_515_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C810 0x00000000  //DDRSS_PHY_516_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C814 0x00000100  //DDRSS_PHY_517_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C818 0x00000000  //DDRSS_PHY_518_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C81C 0x00000000  //DDRSS_PHY_519_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C820 0x00000000  //DDRSS_PHY_520_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C824 0x00000000  //DDRSS_PHY_521_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C828 0x00000000  //DDRSS_PHY_522_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C82C 0x00000000  //DDRSS_PHY_523_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C830 0x00000000  //DDRSS_PHY_524_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C834 0x00DCBA98  //DDRSS_PHY_525_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C838 0x00000000  //DDRSS_PHY_526_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C83C 0x00000000  //DDRSS_PHY_527_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C840 0x00000000  //DDRSS_PHY_528_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C844 0x00000000  //DDRSS_PHY_529_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C848 0x00000000  //DDRSS_PHY_530_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C84C 0x00000100  //DDRSS_PHY_531_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C850 0x00000000  //DDRSS_PHY_532_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C854 0x00000000  //DDRSS_PHY_533_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C858 0x00000000  //DDRSS_PHY_534_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C85C 0x00000000  //DDRSS_PHY_535_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C860 0x00000000  //DDRSS_PHY_536_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C864 0x00000000  //DDRSS_PHY_537_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C868 0x00000000  //DDRSS_PHY_538_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C86C 0x00000000  //DDRSS_PHY_539_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C870 0x0A418820  //DDRSS_PHY_540_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C874 0x103F0000  //DDRSS_PHY_541_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C878 0x000F0100  //DDRSS_PHY_542_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C87C 0x0000000F  //DDRSS_PHY_543_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C880 0x020002CC  //DDRSS_PHY_544_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C884 0x00030000  //DDRSS_PHY_545_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C888 0x00000300  //DDRSS_PHY_546_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C88C 0x00000300  //DDRSS_PHY_547_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C890 0x00000300  //DDRSS_PHY_548_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C894 0x00000300  //DDRSS_PHY_549_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C898 0x00000300  //DDRSS_PHY_550_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C89C 0x42080010  //DDRSS_PHY_551_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A0 0x0000003E  //DDRSS_PHY_552_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A4 0x00000000  //DDRSS_PHY_553_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A8 0x00000000  //DDRSS_PHY_554_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC00 0x00000100  //DDRSS_PHY_768_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC04 0x00001000  //DDRSS_PHY_769_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC08 0x00070000  //DDRSS_PHY_770_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC0C 0x00000000  //DDRSS_PHY_771_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC10 0x00000000  //DDRSS_PHY_772_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC14 0x00000100  //DDRSS_PHY_773_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC18 0x00000000  //DDRSS_PHY_774_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC1C 0x00000000  //DDRSS_PHY_775_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC20 0x00000000  //DDRSS_PHY_776_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC24 0x00000000  //DDRSS_PHY_777_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC28 0x00000000  //DDRSS_PHY_778_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC2C 0x00000000  //DDRSS_PHY_779_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC30 0x00000000  //DDRSS_PHY_780_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC34 0x00DCBA98  //DDRSS_PHY_781_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC38 0x00000000  //DDRSS_PHY_782_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC3C 0x00000000  //DDRSS_PHY_783_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC40 0x00000000  //DDRSS_PHY_784_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC44 0x00000000  //DDRSS_PHY_785_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC48 0x00000000  //DDRSS_PHY_786_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC4C 0x00000100  //DDRSS_PHY_787_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC50 0x00000000  //DDRSS_PHY_788_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC54 0x00000000  //DDRSS_PHY_789_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC58 0x00000000  //DDRSS_PHY_790_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC5C 0x00000000  //DDRSS_PHY_791_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC60 0x00000000  //DDRSS_PHY_792_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC64 0x00000000  //DDRSS_PHY_793_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC68 0x00000000  //DDRSS_PHY_794_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC6C 0x00000000  //DDRSS_PHY_795_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC70 0x16A4A0E6  //DDRSS_PHY_796_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC74 0x103F0000  //DDRSS_PHY_797_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC78 0x000F0000  //DDRSS_PHY_798_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC7C 0x0000000F  //DDRSS_PHY_799_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC80 0x020002CC  //DDRSS_PHY_800_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC84 0x00030000  //DDRSS_PHY_801_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC88 0x00000300  //DDRSS_PHY_802_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC8C 0x00000300  //DDRSS_PHY_803_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC90 0x00000300  //DDRSS_PHY_804_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC94 0x00000300  //DDRSS_PHY_805_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC98 0x00000300  //DDRSS_PHY_806_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC9C 0x42080010  //DDRSS_PHY_807_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA0 0x0000003E  //DDRSS_PHY_808_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA4 0x00000000  //DDRSS_PHY_809_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA8 0x00000000  //DDRSS_PHY_810_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D000 0x00000100  //DDRSS_PHY_1024_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D004 0x00001000  //DDRSS_PHY_1025_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D008 0x00070000  //DDRSS_PHY_1026_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D00C 0x00000000  //DDRSS_PHY_1027_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D010 0x00000000  //DDRSS_PHY_1028_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D014 0x00000100  //DDRSS_PHY_1029_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D018 0x00000000  //DDRSS_PHY_1030_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D01C 0x00000000  //DDRSS_PHY_1031_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D020 0x00000000  //DDRSS_PHY_1032_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D024 0x00000000  //DDRSS_PHY_1033_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D028 0x00000000  //DDRSS_PHY_1034_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D02C 0x00000000  //DDRSS_PHY_1035_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D030 0x00000000  //DDRSS_PHY_1036_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D034 0x00DCBA98  //DDRSS_PHY_1037_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D038 0x00000000  //DDRSS_PHY_1038_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D03C 0x00000000  //DDRSS_PHY_1039_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D040 0x00000000  //DDRSS_PHY_1040_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D044 0x00000000  //DDRSS_PHY_1041_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D048 0x00000000  //DDRSS_PHY_1042_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D04C 0x00000100  //DDRSS_PHY_1043_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D050 0x00000000  //DDRSS_PHY_1044_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D054 0x00000000  //DDRSS_PHY_1045_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D058 0x00000000  //DDRSS_PHY_1046_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D05C 0x00000000  //DDRSS_PHY_1047_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D060 0x00000000  //DDRSS_PHY_1048_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D064 0x00000000  //DDRSS_PHY_1049_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D068 0x00000000  //DDRSS_PHY_1050_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D06C 0x00000000  //DDRSS_PHY_1051_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D070 0x2307B9AC  //DDRSS_PHY_1052_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D074 0x10030000  //DDRSS_PHY_1053_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D078 0x000F0000  //DDRSS_PHY_1054_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D07C 0x0000000F  //DDRSS_PHY_1055_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D080 0x020002CC  //DDRSS_PHY_1056_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D084 0x00030000  //DDRSS_PHY_1057_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D088 0x00000300  //DDRSS_PHY_1058_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D08C 0x00000300  //DDRSS_PHY_1059_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D090 0x00000300  //DDRSS_PHY_1060_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D094 0x00000300  //DDRSS_PHY_1061_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D098 0x00000300  //DDRSS_PHY_1062_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D09C 0x42080010  //DDRSS_PHY_1063_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A0 0x0000003E  //DDRSS_PHY_1064_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A4 0x00000000  //DDRSS_PHY_1065_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A8 0x00000000  //DDRSS_PHY_1066_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D400 0x00000000  //DDRSS_PHY_1280_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D404 0x00000100  //DDRSS_PHY_1281_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D408 0x00000000  //DDRSS_PHY_1282_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D40C 0x00000000  //DDRSS_PHY_1283_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D410 0x00000000  //DDRSS_PHY_1284_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D414 0x00000000  //DDRSS_PHY_1285_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D418 0x00050000  //DDRSS_PHY_1286_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D41C 0x04000100  //DDRSS_PHY_1287_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D420 0x00000055  //DDRSS_PHY_1288_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D424 0x00000000  //DDRSS_PHY_1289_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D428 0x06800000  //DDRSS_PHY_1290_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D42C 0x00000000  //DDRSS_PHY_1291_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D430 0x00000000  //DDRSS_PHY_1292_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D434 0x01002000  //DDRSS_PHY_1293_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D438 0x00004001  //DDRSS_PHY_1294_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D43C 0x00020028  //DDRSS_PHY_1295_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D440 0x00010100  //DDRSS_PHY_1296_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D444 0x00000001  //DDRSS_PHY_1297_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D448 0x00000000  //DDRSS_PHY_1298_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D44C 0x0F0F0E06  //DDRSS_PHY_1299_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D450 0x00010101  //DDRSS_PHY_1300_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D454 0x010F0004  //DDRSS_PHY_1301_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D458 0x00000000  //DDRSS_PHY_1302_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D45C 0x20125770  //DDRSS_PHY_1303_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D460 0x00000064  //DDRSS_PHY_1304_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D464 0x00000000  //DDRSS_PHY_1305_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D468 0x00000000  //DDRSS_PHY_1306_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D46C 0x01020103  //DDRSS_PHY_1307_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D470 0x03020102  //DDRSS_PHY_1308_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D474 0x03030303  //DDRSS_PHY_1309_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D478 0x03030303  //DDRSS_PHY_1310_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D47C 0x00040000  //DDRSS_PHY_1311_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D480 0x00005201  //DDRSS_PHY_1312_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D484 0x00000003  //DDRSS_PHY_1313_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D488 0x00010000  //DDRSS_PHY_1314_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D48C 0x00000000  //DDRSS_PHY_1315_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D490 0x00000003  //DDRSS_PHY_1316_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D494 0x00010000  //DDRSS_PHY_1317_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D498 0x00000000  //DDRSS_PHY_1318_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D49C 0x07070001  //DDRSS_PHY_1319_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A0 0x00005400  //DDRSS_PHY_1320_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A4 0x000040A2  //DDRSS_PHY_1321_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A8 0x00034890  //DDRSS_PHY_1322_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4AC 0x00014890  //DDRSS_PHY_1323_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B0 0x00014890  //DDRSS_PHY_1324_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B4 0x00014890  //DDRSS_PHY_1325_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B8 0x0001488F  //DDRSS_PHY_1326_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4BC 0x00014890  //DDRSS_PHY_1327_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C0 0x0001491E  //DDRSS_PHY_1328_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C4 0x0001491E  //DDRSS_PHY_1329_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C8 0x00014890  //DDRSS_PHY_1330_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4CC 0x00014890  //DDRSS_PHY_1331_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D0 0x00000000  //DDRSS_PHY_1332_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D4 0x00000046  //DDRSS_PHY_1333_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D8 0x00000400  //DDRSS_PHY_1334_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4DC 0x00000008  //DDRSS_PHY_1335_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E0 0x00814890  //DDRSS_PHY_1336_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E4 0x0081491E  //DDRSS_PHY_1337_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E8 0x00148900  //DDRSS_PHY_1338_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4EC 0x001491E8  //DDRSS_PHY_1339_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F0 0x00F4890F  //DDRSS_PHY_1340_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F4 0x03F491EF  //DDRSS_PHY_1341_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F8 0x00000000  //DDRSS_PHY_1342_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4FC 0x00000000  //DDRSS_PHY_1343_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D500 0xB3000000  //DDRSS_PHY_1344_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D504 0x04102006  //DDRSS_PHY_1345_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D508 0x00041020  //DDRSS_PHY_1346_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D50C 0x01C98C98  //DDRSS_PHY_1347_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D510 0x3F400000  //DDRSS_PHY_1348_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D514 0x3F3F1F3F  //DDRSS_PHY_1349_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D518 0x0000001F  //DDRSS_PHY_1350_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D51C 0x00000000  //DDRSS_PHY_1351_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D520 0x00000000  //DDRSS_PHY_1352_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D524 0x00000000  //DDRSS_PHY_1353_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D528 0x00000001  //DDRSS_PHY_1354_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D52C 0x00000000  //DDRSS_PHY_1355_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D530 0x00000000  //DDRSS_PHY_1356_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D534 0x00000000  //DDRSS_PHY_1357_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D538 0x00000000  //DDRSS_PHY_1358_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D53C 0x76543210  //DDRSS_PHY_1359_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D540 0x00000098  //DDRSS_PHY_1360_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D544 0x00000000  //DDRSS_PHY_1361_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D548 0x00000000  //DDRSS_PHY_1362_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D54C 0x00000000  //DDRSS_PHY_1363_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D550 0x00040700  //DDRSS_PHY_1364_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D554 0x00000000  //DDRSS_PHY_1365_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D558 0x00000000  //DDRSS_PHY_1366_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D55C 0x00000000  //DDRSS_PHY_1367_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D560 0x030F7102  //DDRSS_PHY_1368_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D564 0x00000100  //DDRSS_PHY_1369_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D568 0x00000000  //DDRSS_PHY_1370_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D56C 0x0001F7C2  //DDRSS_PHY_1371_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D570 0x00020002  //DDRSS_PHY_1372_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D574 0x00000000  //DDRSS_PHY_1373_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D578 0x00001142  //DDRSS_PHY_1374_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D57C 0x03020400  //DDRSS_PHY_1375_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D580 0x00000080  //DDRSS_PHY_1376_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D584 0x03900390  //DDRSS_PHY_1377_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D588 0x03900390  //DDRSS_PHY_1378_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D58C 0x03900390  //DDRSS_PHY_1379_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D590 0x03900390  //DDRSS_PHY_1380_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D594 0x03900390  //DDRSS_PHY_1381_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D598 0x03900390  //DDRSS_PHY_1382_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D59C 0x00000300  //DDRSS_PHY_1383_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A0 0x00000300  //DDRSS_PHY_1384_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A4 0x00000300  //DDRSS_PHY_1385_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A8 0x00000300  //DDRSS_PHY_1386_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5AC 0x31823FC7  //DDRSS_PHY_1387_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B0 0x00000000  //DDRSS_PHY_1388_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B4 0x0C000D3F  //DDRSS_PHY_1389_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B8 0x30000D3F  //DDRSS_PHY_1390_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5BC 0x300D3F11  //DDRSS_PHY_1391_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C0 0x01990000  //DDRSS_PHY_1392_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C4 0x000D3FCC  //DDRSS_PHY_1393_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C8 0x00000C11  //DDRSS_PHY_1394_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5CC 0x300D3F11  //DDRSS_PHY_1395_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D0 0x01990000  //DDRSS_PHY_1396_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D4 0x300C3F11  //DDRSS_PHY_1397_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D8 0x01990000  //DDRSS_PHY_1398_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5DC 0x300C3F11  //DDRSS_PHY_1399_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E0 0x01990000  //DDRSS_PHY_1400_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E4 0x300D3F11  //DDRSS_PHY_1401_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E8 0x01990000  //DDRSS_PHY_1402_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5EC 0x300D3F11  //DDRSS_PHY_1403_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F0 0x01990000  //DDRSS_PHY_1404_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F4 0x20040004  //DDRSS_PHY_1405_DATA_F0

Here are the summary of all the cases we tested (all tested with the modified main(), i.e. System_init(), System_Deinit() added)  :

1. ECC disabled, write 4096 32bit data, then read & verify,            tests pass with no failure.

2. ECC disabled, write 128M 32bit data(4Gb), then read & verify,  tests pass with no failure.

3. ECC enabled,  write 4096 32bit data, then read & verify,            tests pass with no failure.

4. ECC enabled,  write 8192 32bit data, then read & verify,            tests program stuck at some address between 0x9000 0000~0x9800 0000 (NO failure before stuck).  

For Case 4,  when the program stuck, stop the program, the register dump is:

MAIN_Cortex_R5_0_0: GEL Output: CPU reset (soft reset) has been issued through GEL.
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308000 0x10460A01  //DDRSS_CTL_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308004 0x5D1AF3C3  //DDRSS_CTL_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308008 0x0171A610  //DDRSS_CTL_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30800C 0x40020A11  //DDRSS_CTL_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308010 0x00052006  //DDRSS_CTL_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308014 0x02050020  //DDRSS_CTL_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308018 0x03070101  //DDRSS_CTL_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30801C 0x00089070  //DDRSS_CTL_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308020 0x00000000  //DDRSS_CTL_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308024 0x00000000  //DDRSS_CTL_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308028 0x00000000  //DDRSS_CTL_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30802C 0x00089070  //DDRSS_CTL_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308030 0x00000000  //DDRSS_CTL_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308034 0x00000000  //DDRSS_CTL_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308038 0x00000000  //DDRSS_CTL_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30803C 0x00089070  //DDRSS_CTL_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308040 0x00000000  //DDRSS_CTL_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308044 0x00000000  //DDRSS_CTL_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308048 0x00000000  //DDRSS_CTL_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30804C 0x01010100  //DDRSS_CTL_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308050 0x01000101  //DDRSS_CTL_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308054 0x01000110  //DDRSS_CTL_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308058 0x02010002  //DDRSS_CTL_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30805C 0x00027100  //DDRSS_CTL_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308060 0x00061A80  //DDRSS_CTL_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308064 0x02550255  //DDRSS_CTL_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308068 0x00000255  //DDRSS_CTL_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30806C 0x00000000  //DDRSS_CTL_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308070 0x00000000  //DDRSS_CTL_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308074 0x00000000  //DDRSS_CTL_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308078 0x00000000  //DDRSS_CTL_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30807C 0x00000000  //DDRSS_CTL_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308080 0x00000000  //DDRSS_CTL_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308084 0x00000000  //DDRSS_CTL_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308088 0x00000000  //DDRSS_CTL_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30808C 0x00000000  //DDRSS_CTL_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308090 0x00000000  //DDRSS_CTL_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308094 0x00000000  //DDRSS_CTL_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308098 0x0400091C  //DDRSS_CTL_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30809C 0x1C1C1C1C  //DDRSS_CTL_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A0 0x0400091C  //DDRSS_CTL_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A4 0x1C1C1C1C  //DDRSS_CTL_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080A8 0x0400091C  //DDRSS_CTL_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080AC 0x1C1C1C1C  //DDRSS_CTL_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B0 0x05050404  //DDRSS_CTL_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B4 0x00002606  //DDRSS_CTL_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080B8 0x0602001B  //DDRSS_CTL_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080BC 0x05001D0C  //DDRSS_CTL_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C0 0x00260605  //DDRSS_CTL_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C4 0x0602001B  //DDRSS_CTL_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080C8 0x05001D0C  //DDRSS_CTL_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080CC 0x00260605  //DDRSS_CTL_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D0 0x0602001B  //DDRSS_CTL_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D4 0x07001D0C  //DDRSS_CTL_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080D8 0x00180807  //DDRSS_CTL_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080DC 0x0400DB60  //DDRSS_CTL_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E0 0x07070009  //DDRSS_CTL_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E4 0x00001808  //DDRSS_CTL_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080E8 0x0400DB60  //DDRSS_CTL_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080EC 0x07070009  //DDRSS_CTL_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F0 0x00001808  //DDRSS_CTL_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F4 0x0400DB60  //DDRSS_CTL_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080F8 0x03000009  //DDRSS_CTL_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3080FC 0x0D0D0002  //DDRSS_CTL_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308100 0x0D0D0D0D  //DDRSS_CTL_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308104 0x01010000  //DDRSS_CTL_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308108 0x031A1A1A  //DDRSS_CTL_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30810C 0x0C0C0C0C  //DDRSS_CTL_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308110 0x00000C0C  //DDRSS_CTL_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308114 0x00000101  //DDRSS_CTL_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308118 0x00000000  //DDRSS_CTL_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30811C 0x01000000  //DDRSS_CTL_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308120 0x00D00803  //DDRSS_CTL_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308124 0x00001860  //DDRSS_CTL_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308128 0x000000D0  //DDRSS_CTL_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30812C 0x00001860  //DDRSS_CTL_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308130 0x000000D0  //DDRSS_CTL_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308134 0x00001860  //DDRSS_CTL_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308138 0x00000005  //DDRSS_CTL_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30813C 0x00000000  //DDRSS_CTL_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308140 0x00000000  //DDRSS_CTL_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308144 0x00000000  //DDRSS_CTL_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308148 0x00000000  //DDRSS_CTL_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30814C 0x00000000  //DDRSS_CTL_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308150 0x00000000  //DDRSS_CTL_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308154 0x00000000  //DDRSS_CTL_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308158 0x00000000  //DDRSS_CTL_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30815C 0x00090009  //DDRSS_CTL_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308160 0x00000009  //DDRSS_CTL_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308164 0x00000000  //DDRSS_CTL_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308168 0x00000000  //DDRSS_CTL_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30816C 0x00000000  //DDRSS_CTL_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308170 0x00000000  //DDRSS_CTL_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308174 0x00000000  //DDRSS_CTL_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308178 0x00010001  //DDRSS_CTL_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30817C 0x00025501  //DDRSS_CTL_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308180 0x025500D8  //DDRSS_CTL_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308184 0x025500D8  //DDRSS_CTL_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308188 0x00D800D8  //DDRSS_CTL_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30818C 0x00D800D8  //DDRSS_CTL_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308190 0x00000000  //DDRSS_CTL_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308194 0x00000000  //DDRSS_CTL_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308198 0x00000000  //DDRSS_CTL_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30819C 0x00000000  //DDRSS_CTL_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A0 0x00000000  //DDRSS_CTL_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A4 0x00000000  //DDRSS_CTL_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081A8 0x03010000  //DDRSS_CTL_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081AC 0x00010000  //DDRSS_CTL_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B0 0x00000000  //DDRSS_CTL_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B4 0x01000000  //DDRSS_CTL_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081B8 0x80104002  //DDRSS_CTL_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081BC 0x00040003  //DDRSS_CTL_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C0 0x00040005  //DDRSS_CTL_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C4 0x00030000  //DDRSS_CTL_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081C8 0x00050004  //DDRSS_CTL_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081CC 0x00000004  //DDRSS_CTL_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D0 0x00040003  //DDRSS_CTL_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D4 0x00040005  //DDRSS_CTL_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081D8 0x00000000  //DDRSS_CTL_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081DC 0x00061800  //DDRSS_CTL_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E0 0x00061800  //DDRSS_CTL_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E4 0x00061800  //DDRSS_CTL_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081E8 0x00061800  //DDRSS_CTL_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081EC 0x00061800  //DDRSS_CTL_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F0 0x00000000  //DDRSS_CTL_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F4 0x0000AAA0  //DDRSS_CTL_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081F8 0x00061800  //DDRSS_CTL_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3081FC 0x00061800  //DDRSS_CTL_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308200 0x00061800  //DDRSS_CTL_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308204 0x00061800  //DDRSS_CTL_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308208 0x00061800  //DDRSS_CTL_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30820C 0x00000000  //DDRSS_CTL_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308210 0x0000AAA0  //DDRSS_CTL_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308214 0x00061800  //DDRSS_CTL_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308218 0x00061800  //DDRSS_CTL_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30821C 0x00061800  //DDRSS_CTL_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308220 0x00061800  //DDRSS_CTL_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308224 0x00061800  //DDRSS_CTL_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308228 0x00000000  //DDRSS_CTL_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30822C 0x0000AAA0  //DDRSS_CTL_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308230 0x00000000  //DDRSS_CTL_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308234 0x00000000  //DDRSS_CTL_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308238 0x00000000  //DDRSS_CTL_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30823C 0x00000000  //DDRSS_CTL_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308240 0x00000000  //DDRSS_CTL_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308244 0x00000000  //DDRSS_CTL_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308248 0x00000000  //DDRSS_CTL_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30824C 0x00000000  //DDRSS_CTL_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308250 0x00000000  //DDRSS_CTL_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308254 0x00000000  //DDRSS_CTL_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308258 0x00000000  //DDRSS_CTL_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30825C 0x00000000  //DDRSS_CTL_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308260 0x00000000  //DDRSS_CTL_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308264 0x00000000  //DDRSS_CTL_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308268 0x00000000  //DDRSS_CTL_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30826C 0x00000000  //DDRSS_CTL_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308270 0x080C0000  //DDRSS_CTL_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308274 0x080C080C  //DDRSS_CTL_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308278 0x00000000  //DDRSS_CTL_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30827C 0x07010A09  //DDRSS_CTL_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308280 0x000E0A09  //DDRSS_CTL_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308284 0x010A0900  //DDRSS_CTL_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308288 0x0E0A0907  //DDRSS_CTL_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30828C 0x0A090000  //DDRSS_CTL_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308290 0x0A090701  //DDRSS_CTL_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308294 0x0000080E  //DDRSS_CTL_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308298 0x00040003  //DDRSS_CTL_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30829C 0x00004007  //DDRSS_CTL_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A0 0x00000000  //DDRSS_CTL_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A4 0x00000000  //DDRSS_CTL_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082A8 0x00000000  //DDRSS_CTL_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082AC 0x00000000  //DDRSS_CTL_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B0 0x00000000  //DDRSS_CTL_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B4 0x00000000  //DDRSS_CTL_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082B8 0x01000000  //DDRSS_CTL_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082BC 0x00000000  //DDRSS_CTL_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C0 0x00001500  //DDRSS_CTL_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C4 0x0000100E  //DDRSS_CTL_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082C8 0x00000000  //DDRSS_CTL_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082CC 0x00000000  //DDRSS_CTL_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D0 0x00000001  //DDRSS_CTL_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D4 0x00000002  //DDRSS_CTL_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082D8 0x00000C00  //DDRSS_CTL_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082DC 0x00001000  //DDRSS_CTL_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E0 0x00000C00  //DDRSS_CTL_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E4 0x00001000  //DDRSS_CTL_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082E8 0x00000C00  //DDRSS_CTL_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082EC 0x00001000  //DDRSS_CTL_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F0 0x00000000  //DDRSS_CTL_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F4 0x00000000  //DDRSS_CTL_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082F8 0x00000000  //DDRSS_CTL_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3082FC 0x00000000  //DDRSS_CTL_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308300 0x00000000  //DDRSS_CTL_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308304 0x00000000  //DDRSS_CTL_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308308 0x00000000  //DDRSS_CTL_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30830C 0x00000000  //DDRSS_CTL_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308310 0x00000000  //DDRSS_CTL_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308314 0x00000000  //DDRSS_CTL_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308318 0x00000000  //DDRSS_CTL_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30831C 0x00000000  //DDRSS_CTL_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308320 0x00000000  //DDRSS_CTL_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308324 0x00000000  //DDRSS_CTL_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308328 0x00000000  //DDRSS_CTL_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30832C 0x00000000  //DDRSS_CTL_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308330 0x00042400  //DDRSS_CTL_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308334 0x00000301  //DDRSS_CTL_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308338 0x00000000  //DDRSS_CTL_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30833C 0x00000424  //DDRSS_CTL_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308340 0x00000301  //DDRSS_CTL_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308344 0x00000000  //DDRSS_CTL_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308348 0x00000424  //DDRSS_CTL_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30834C 0x00000301  //DDRSS_CTL_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308350 0x00000000  //DDRSS_CTL_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308354 0x00000424  //DDRSS_CTL_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308358 0x00000301  //DDRSS_CTL_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30835C 0x00000000  //DDRSS_CTL_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308360 0x00000424  //DDRSS_CTL_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308364 0x00000301  //DDRSS_CTL_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308368 0x00000000  //DDRSS_CTL_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30836C 0x00000424  //DDRSS_CTL_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308370 0x00000301  //DDRSS_CTL_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308374 0x00000000  //DDRSS_CTL_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308378 0x00000000  //DDRSS_CTL_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30837C 0x00000000  //DDRSS_CTL_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308380 0x00000000  //DDRSS_CTL_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308384 0x00000000  //DDRSS_CTL_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308388 0x00000000  //DDRSS_CTL_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30838C 0x00000000  //DDRSS_CTL_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308390 0x00000000  //DDRSS_CTL_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308394 0x00000000  //DDRSS_CTL_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308398 0x00000000  //DDRSS_CTL_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30839C 0x00000000  //DDRSS_CTL_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A0 0x00000000  //DDRSS_CTL_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A4 0x00000000  //DDRSS_CTL_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083A8 0x00000000  //DDRSS_CTL_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083AC 0x00000000  //DDRSS_CTL_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B0 0x00001401  //DDRSS_CTL_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B4 0x00001401  //DDRSS_CTL_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083B8 0x00001401  //DDRSS_CTL_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083BC 0x00001401  //DDRSS_CTL_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C0 0x00001401  //DDRSS_CTL_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C4 0x00001401  //DDRSS_CTL_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083C8 0x00000493  //DDRSS_CTL_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083CC 0x00000493  //DDRSS_CTL_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D0 0x00000493  //DDRSS_CTL_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D4 0x00000493  //DDRSS_CTL_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083D8 0x00000493  //DDRSS_CTL_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083DC 0x00000493  //DDRSS_CTL_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E0 0x00000000  //DDRSS_CTL_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E4 0x00000000  //DDRSS_CTL_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083E8 0x00000000  //DDRSS_CTL_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083EC 0x00000000  //DDRSS_CTL_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F0 0x00000000  //DDRSS_CTL_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F4 0x00000000  //DDRSS_CTL_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083F8 0x00000000  //DDRSS_CTL_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3083FC 0x00000000  //DDRSS_CTL_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308400 0x00000000  //DDRSS_CTL_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308404 0x00000000  //DDRSS_CTL_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308408 0x00000000  //DDRSS_CTL_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30840C 0x00000000  //DDRSS_CTL_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308410 0x00000000  //DDRSS_CTL_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308414 0x00000000  //DDRSS_CTL_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308418 0x00000000  //DDRSS_CTL_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30841C 0x00000000  //DDRSS_CTL_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308420 0x00000000  //DDRSS_CTL_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308424 0x00000000  //DDRSS_CTL_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308428 0x00000000  //DDRSS_CTL_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30842C 0x00000000  //DDRSS_CTL_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308430 0x00000000  //DDRSS_CTL_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308434 0x00000000  //DDRSS_CTL_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308438 0x00000000  //DDRSS_CTL_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30843C 0x00000000  //DDRSS_CTL_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308440 0x00000000  //DDRSS_CTL_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308444 0x00000000  //DDRSS_CTL_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308448 0x00000000  //DDRSS_CTL_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30844C 0x00000000  //DDRSS_CTL_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308450 0x00000000  //DDRSS_CTL_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308454 0x00010000  //DDRSS_CTL_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308458 0x00000000  //DDRSS_CTL_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30845C 0x00000100  //DDRSS_CTL_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308460 0x00000000  //DDRSS_CTL_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308464 0x00000101  //DDRSS_CTL_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308468 0x00000000  //DDRSS_CTL_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30846C 0x00000000  //DDRSS_CTL_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308470 0x00000000  //DDRSS_CTL_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308474 0x00000000  //DDRSS_CTL_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308478 0x00000000  //DDRSS_CTL_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30847C 0x00000000  //DDRSS_CTL_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308480 0x00000000  //DDRSS_CTL_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308484 0x00000FFF  //DDRSS_CTL_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308488 0x0C181511  //DDRSS_CTL_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30848C 0x00000304  //DDRSS_CTL_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308490 0x00000000  //DDRSS_CTL_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308494 0x00000000  //DDRSS_CTL_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308498 0x00000000  //DDRSS_CTL_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30849C 0x00000000  //DDRSS_CTL_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A0 0x00000000  //DDRSS_CTL_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A4 0x00000000  //DDRSS_CTL_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084A8 0x00000000  //DDRSS_CTL_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084AC 0x00000000  //DDRSS_CTL_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B0 0x00000000  //DDRSS_CTL_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B4 0x00000000  //DDRSS_CTL_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084B8 0x00000000  //DDRSS_CTL_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084BC 0x00000000  //DDRSS_CTL_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C0 0x00000000  //DDRSS_CTL_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C4 0x00040000  //DDRSS_CTL_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084C8 0x00800200  //DDRSS_CTL_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084CC 0x00000000  //DDRSS_CTL_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D0 0x02000400  //DDRSS_CTL_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D4 0x00000080  //DDRSS_CTL_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084D8 0x00040000  //DDRSS_CTL_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084DC 0x00800200  //DDRSS_CTL_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E0 0x00000000  //DDRSS_CTL_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E4 0x00000000  //DDRSS_CTL_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084E8 0x00000000  //DDRSS_CTL_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084EC 0x00000100  //DDRSS_CTL_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F0 0x01010000  //DDRSS_CTL_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F4 0x00000202  //DDRSS_CTL_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084F8 0x0FFF0000  //DDRSS_CTL_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3084FC 0x000FFF00  //DDRSS_CTL_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308500 0xFFFFFFFF  //DDRSS_CTL_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308504 0x00FFFF00  //DDRSS_CTL_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308508 0x0A000000  //DDRSS_CTL_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30850C 0x0001FFFF  //DDRSS_CTL_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308510 0x01010101  //DDRSS_CTL_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308514 0x01010101  //DDRSS_CTL_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308518 0x00000118  //DDRSS_CTL_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30851C 0x00000C01  //DDRSS_CTL_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308520 0x00000000  //DDRSS_CTL_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308524 0x00000000  //DDRSS_CTL_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308528 0x00000000  //DDRSS_CTL_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30852C 0x01000000  //DDRSS_CTL_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308530 0x00000100  //DDRSS_CTL_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308534 0x00010000  //DDRSS_CTL_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308538 0x80000040  //DDRSS_CTL_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30853C 0x00000000  //DDRSS_CTL_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308540 0x00000000  //DDRSS_CTL_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308544 0x00000000  //DDRSS_CTL_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308548 0x00000000  //DDRSS_CTL_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30854C 0x00000000  //DDRSS_CTL_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308550 0x00000003  //DDRSS_CTL_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308554 0x00000000  //DDRSS_CTL_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308558 0x00000000  //DDRSS_CTL_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30855C 0x00000000  //DDRSS_CTL_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308560 0x00000000  //DDRSS_CTL_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308564 0x00000000  //DDRSS_CTL_345_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308568 0x00000000  //DDRSS_CTL_346_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30856C 0x00000000  //DDRSS_CTL_347_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308570 0x00000000  //DDRSS_CTL_348_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308574 0x00000000  //DDRSS_CTL_349_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308578 0x00000000  //DDRSS_CTL_350_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30857C 0x00000000  //DDRSS_CTL_351_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308580 0x00000000  //DDRSS_CTL_352_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308584 0x00000000  //DDRSS_CTL_353_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308588 0x00000000  //DDRSS_CTL_354_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30858C 0x00000000  //DDRSS_CTL_355_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308590 0x00000000  //DDRSS_CTL_356_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308594 0x00000000  //DDRSS_CTL_357_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308598 0x00000000  //DDRSS_CTL_358_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30859C 0x00000000  //DDRSS_CTL_359_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A0 0x20000000  //DDRSS_CTL_360_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A4 0x02002000  //DDRSS_CTL_361_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085A8 0x0000003F  //DDRSS_CTL_362_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085AC 0x00000000  //DDRSS_CTL_363_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B0 0x00000000  //DDRSS_CTL_364_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B4 0x00000001  //DDRSS_CTL_365_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085B8 0x00000001  //DDRSS_CTL_366_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085BC 0x12000010  //DDRSS_CTL_367_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C0 0x00000000  //DDRSS_CTL_368_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C4 0x00000000  //DDRSS_CTL_369_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085C8 0x0C000000  //DDRSS_CTL_370_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085CC 0x060C0606  //DDRSS_CTL_371_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D0 0x06060C06  //DDRSS_CTL_372_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D4 0x00010101  //DDRSS_CTL_373_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085D8 0x02000000  //DDRSS_CTL_374_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085DC 0x05020101  //DDRSS_CTL_375_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E0 0x00000505  //DDRSS_CTL_376_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E4 0x02020200  //DDRSS_CTL_377_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085E8 0x02020202  //DDRSS_CTL_378_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085EC 0x02020202  //DDRSS_CTL_379_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F0 0x02020202  //DDRSS_CTL_380_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F4 0x00000000  //DDRSS_CTL_381_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085F8 0x00000000  //DDRSS_CTL_382_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F3085FC 0x04000100  //DDRSS_CTL_383_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308600 0x1E000304  //DDRSS_CTL_384_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308604 0x000030C0  //DDRSS_CTL_385_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308608 0x00000200  //DDRSS_CTL_386_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30860C 0x00000200  //DDRSS_CTL_387_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308610 0x00000200  //DDRSS_CTL_388_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308614 0x00000200  //DDRSS_CTL_389_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308618 0x0000DB60  //DDRSS_CTL_390_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30861C 0x0001E780  //DDRSS_CTL_391_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308620 0x0C0D0302  //DDRSS_CTL_392_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308624 0x001E090A  //DDRSS_CTL_393_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308628 0x000030C0  //DDRSS_CTL_394_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30862C 0x00000200  //DDRSS_CTL_395_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308630 0x00000200  //DDRSS_CTL_396_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308634 0x00000200  //DDRSS_CTL_397_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308638 0x00000200  //DDRSS_CTL_398_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30863C 0x0000DB60  //DDRSS_CTL_399_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308640 0x0001E780  //DDRSS_CTL_400_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308644 0x0C0D0302  //DDRSS_CTL_401_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308648 0x001E090A  //DDRSS_CTL_402_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30864C 0x000030C0  //DDRSS_CTL_403_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308650 0x00000200  //DDRSS_CTL_404_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308654 0x00000200  //DDRSS_CTL_405_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308658 0x00000200  //DDRSS_CTL_406_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30865C 0x00000200  //DDRSS_CTL_407_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308660 0x0000DB60  //DDRSS_CTL_408_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308664 0x0001E780  //DDRSS_CTL_409_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308668 0x0C0D0302  //DDRSS_CTL_410_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30866C 0x0000090A  //DDRSS_CTL_411_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308670 0x00000000  //DDRSS_CTL_412_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308674 0x0302000A  //DDRSS_CTL_413_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308678 0x01000500  //DDRSS_CTL_414_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30867C 0x01010001  //DDRSS_CTL_415_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308680 0x00010001  //DDRSS_CTL_416_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308684 0x01010001  //DDRSS_CTL_417_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308688 0x02010000  //DDRSS_CTL_418_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30868C 0x00000200  //DDRSS_CTL_419_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308690 0x02000201  //DDRSS_CTL_420_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308694 0x00000000  //DDRSS_CTL_421_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F308698 0x00202020  //DDRSS_CTL_422_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A000 0x00000A01  //DDRSS_PI_0_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A004 0xAE8D79E2  //DDRSS_PI_1_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A008 0x0714B570  //DDRSS_PI_2_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A00C 0x01011387  //DDRSS_PI_3_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A010 0x00000001  //DDRSS_PI_4_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A014 0x00010064  //DDRSS_PI_5_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A018 0x00000000  //DDRSS_PI_6_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A01C 0x00000000  //DDRSS_PI_7_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A020 0x00000000  //DDRSS_PI_8_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A024 0x00000000  //DDRSS_PI_9_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A028 0x00000000  //DDRSS_PI_10_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A02C 0x00000000  //DDRSS_PI_11_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A030 0x00000000  //DDRSS_PI_12_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A034 0x00010001  //DDRSS_PI_13_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A038 0x00000000  //DDRSS_PI_14_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A03C 0x00010001  //DDRSS_PI_15_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A040 0x00000005  //DDRSS_PI_16_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A044 0x00010000  //DDRSS_PI_17_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A048 0x00000000  //DDRSS_PI_18_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A04C 0x00000000  //DDRSS_PI_19_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A050 0x00000000  //DDRSS_PI_20_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A054 0x00000000  //DDRSS_PI_21_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A058 0x00000000  //DDRSS_PI_22_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A05C 0x00000000  //DDRSS_PI_23_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A060 0x280D0001  //DDRSS_PI_24_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A064 0x00000000  //DDRSS_PI_25_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A068 0x00010000  //DDRSS_PI_26_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A06C 0x00003200  //DDRSS_PI_27_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A070 0x00000000  //DDRSS_PI_28_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A074 0x00000000  //DDRSS_PI_29_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A078 0x00060602  //DDRSS_PI_30_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A07C 0x00000000  //DDRSS_PI_31_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A080 0x00000000  //DDRSS_PI_32_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A084 0x00000000  //DDRSS_PI_33_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A088 0x00000001  //DDRSS_PI_34_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A08C 0x00000055  //DDRSS_PI_35_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A090 0x000000AA  //DDRSS_PI_36_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A094 0x000000AD  //DDRSS_PI_37_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A098 0x00000052  //DDRSS_PI_38_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A09C 0x0000006A  //DDRSS_PI_39_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A0 0x00000095  //DDRSS_PI_40_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A4 0x00000095  //DDRSS_PI_41_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0A8 0x000000AD  //DDRSS_PI_42_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0AC 0x00000000  //DDRSS_PI_43_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B0 0x00000000  //DDRSS_PI_44_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B4 0x00010100  //DDRSS_PI_45_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0B8 0x00000014  //DDRSS_PI_46_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0BC 0x000007D0  //DDRSS_PI_47_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C0 0x00000300  //DDRSS_PI_48_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C4 0x00000000  //DDRSS_PI_49_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0C8 0x00000000  //DDRSS_PI_50_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0CC 0x01000000  //DDRSS_PI_51_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D0 0x00010101  //DDRSS_PI_52_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D4 0x0100090C  //DDRSS_PI_53_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0D8 0x00000000  //DDRSS_PI_54_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0DC 0x00010000  //DDRSS_PI_55_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E0 0x00000000  //DDRSS_PI_56_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E4 0x00000000  //DDRSS_PI_57_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0E8 0x00000000  //DDRSS_PI_58_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0EC 0x00000000  //DDRSS_PI_59_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F0 0x00001400  //DDRSS_PI_60_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F4 0x00000000  //DDRSS_PI_61_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0F8 0x01000000  //DDRSS_PI_62_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A0FC 0x00000404  //DDRSS_PI_63_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A100 0x00000001  //DDRSS_PI_64_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A104 0x0001010E  //DDRSS_PI_65_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A108 0x02040100  //DDRSS_PI_66_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A10C 0x00010000  //DDRSS_PI_67_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A110 0x00000034  //DDRSS_PI_68_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A114 0x00000000  //DDRSS_PI_69_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A118 0x00000000  //DDRSS_PI_70_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A11C 0x00000000  //DDRSS_PI_71_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A120 0x00000000  //DDRSS_PI_72_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A124 0x00000000  //DDRSS_PI_73_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A128 0x00000000  //DDRSS_PI_74_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A12C 0x00000005  //DDRSS_PI_75_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A130 0x01000000  //DDRSS_PI_76_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A134 0x04020100  //DDRSS_PI_77_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A138 0x00020000  //DDRSS_PI_78_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A13C 0x00010002  //DDRSS_PI_79_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A140 0x00000001  //DDRSS_PI_80_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A144 0x00020001  //DDRSS_PI_81_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A148 0x00020002  //DDRSS_PI_82_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A14C 0x29C02000  //DDRSS_PI_83_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A150 0x00000000  //DDRSS_PI_84_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A154 0x00000000  //DDRSS_PI_85_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A158 0x00000000  //DDRSS_PI_86_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A15C 0x00000000  //DDRSS_PI_87_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A160 0x00000000  //DDRSS_PI_88_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A164 0x00000000  //DDRSS_PI_89_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A168 0x00000000  //DDRSS_PI_90_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A16C 0x00000300  //DDRSS_PI_91_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A170 0x0A090B0C  //DDRSS_PI_92_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A174 0x04060708  //DDRSS_PI_93_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A178 0x01000005  //DDRSS_PI_94_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A17C 0x00000800  //DDRSS_PI_95_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A180 0x00000000  //DDRSS_PI_96_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A184 0x00010008  //DDRSS_PI_97_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A188 0x00000000  //DDRSS_PI_98_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A18C 0x0000AA00  //DDRSS_PI_99_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A190 0x00000000  //DDRSS_PI_100_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A194 0x00010000  //DDRSS_PI_101_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A198 0x00000000  //DDRSS_PI_102_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A19C 0x00000000  //DDRSS_PI_103_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A0 0x00000000  //DDRSS_PI_104_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A4 0x00000000  //DDRSS_PI_105_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1A8 0x00000000  //DDRSS_PI_106_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1AC 0x00000000  //DDRSS_PI_107_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B0 0x00000000  //DDRSS_PI_108_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B4 0x00000000  //DDRSS_PI_109_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1B8 0x00000000  //DDRSS_PI_110_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1BC 0x00000000  //DDRSS_PI_111_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C0 0x00000000  //DDRSS_PI_112_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C4 0x00000000  //DDRSS_PI_113_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1C8 0x00000000  //DDRSS_PI_114_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1CC 0x00000000  //DDRSS_PI_115_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D0 0x00000000  //DDRSS_PI_116_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D4 0x00000000  //DDRSS_PI_117_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1D8 0x00000000  //DDRSS_PI_118_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1DC 0x00000000  //DDRSS_PI_119_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E0 0x00000000  //DDRSS_PI_120_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E4 0x00000000  //DDRSS_PI_121_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1E8 0x00000000  //DDRSS_PI_122_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1EC 0x00000000  //DDRSS_PI_123_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F0 0x00000008  //DDRSS_PI_124_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F4 0x00000000  //DDRSS_PI_125_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1F8 0x00000000  //DDRSS_PI_126_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A1FC 0x00000000  //DDRSS_PI_127_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A200 0x00000000  //DDRSS_PI_128_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A204 0x00000000  //DDRSS_PI_129_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A208 0x00000000  //DDRSS_PI_130_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A20C 0x00000000  //DDRSS_PI_131_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A210 0x00000000  //DDRSS_PI_132_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A214 0x00010100  //DDRSS_PI_133_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A218 0x00000000  //DDRSS_PI_134_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A21C 0x00000000  //DDRSS_PI_135_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A220 0x00027100  //DDRSS_PI_136_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A224 0x00061A80  //DDRSS_PI_137_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A228 0x00000100  //DDRSS_PI_138_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A22C 0x00000000  //DDRSS_PI_139_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A230 0x00000000  //DDRSS_PI_140_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A234 0x00000000  //DDRSS_PI_141_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A238 0x00000000  //DDRSS_PI_142_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A23C 0x00000000  //DDRSS_PI_143_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A240 0x01000000  //DDRSS_PI_144_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A244 0xC1010003  //DDRSS_PI_145_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A248 0x02000101  //DDRSS_PI_146_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A24C 0x01030101  //DDRSS_PI_147_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A250 0x00010400  //DDRSS_PI_148_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A254 0x06000105  //DDRSS_PI_149_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A258 0x01070001  //DDRSS_PI_150_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A25C 0x00000010  //DDRSS_PI_151_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A260 0x00000000  //DDRSS_PI_152_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A264 0x00000001  //DDRSS_PI_153_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A268 0x00010000  //DDRSS_PI_154_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A26C 0x00000000  //DDRSS_PI_155_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A270 0x00000000  //DDRSS_PI_156_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A274 0x00000000  //DDRSS_PI_157_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A278 0x00000000  //DDRSS_PI_158_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A27C 0x00010000  //DDRSS_PI_159_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A280 0x00000004  //DDRSS_PI_160_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A284 0x00000000  //DDRSS_PI_161_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A288 0x00000000  //DDRSS_PI_162_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A28C 0x00000000  //DDRSS_PI_163_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A290 0x00007800  //DDRSS_PI_164_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A294 0x00780078  //DDRSS_PI_165_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A298 0x00141414  //DDRSS_PI_166_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A29C 0x0000003A  //DDRSS_PI_167_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A0 0x0000003A  //DDRSS_PI_168_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A4 0x0004003A  //DDRSS_PI_169_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2A8 0x04000400  //DDRSS_PI_170_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2AC 0xC8040009  //DDRSS_PI_171_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B0 0x0400091C  //DDRSS_PI_172_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B4 0x00091CC8  //DDRSS_PI_173_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2B8 0x001CC804  //DDRSS_PI_174_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2BC 0x000000D0  //DDRSS_PI_175_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C0 0x00001860  //DDRSS_PI_176_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C4 0x000000D0  //DDRSS_PI_177_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2C8 0x00001860  //DDRSS_PI_178_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2CC 0x000000D0  //DDRSS_PI_179_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D0 0x04001860  //DDRSS_PI_180_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D4 0x01010404  //DDRSS_PI_181_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2D8 0x00001901  //DDRSS_PI_182_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2DC 0x00190019  //DDRSS_PI_183_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E0 0x010C010C  //DDRSS_PI_184_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E4 0x0000010C  //DDRSS_PI_185_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2E8 0x00000000  //DDRSS_PI_186_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2EC 0x05000000  //DDRSS_PI_187_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F0 0x01010505  //DDRSS_PI_188_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F4 0x01010101  //DDRSS_PI_189_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2F8 0x00181818  //DDRSS_PI_190_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A2FC 0x00000000  //DDRSS_PI_191_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A300 0x00000000  //DDRSS_PI_192_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A304 0x0D000000  //DDRSS_PI_193_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A308 0x0A0A0D0D  //DDRSS_PI_194_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A30C 0x0303030A  //DDRSS_PI_195_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A310 0x00000000  //DDRSS_PI_196_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A314 0x00000000  //DDRSS_PI_197_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A318 0x00000000  //DDRSS_PI_198_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A31C 0x00000000  //DDRSS_PI_199_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A320 0x00000000  //DDRSS_PI_200_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A324 0x00000000  //DDRSS_PI_201_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A328 0x00000000  //DDRSS_PI_202_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A32C 0x00000000  //DDRSS_PI_203_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A330 0x00000000  //DDRSS_PI_204_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A334 0x00000000  //DDRSS_PI_205_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A338 0x00000000  //DDRSS_PI_206_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A33C 0x00000000  //DDRSS_PI_207_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A340 0x00000000  //DDRSS_PI_208_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A344 0x0D090000  //DDRSS_PI_209_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A348 0x0D09000D  //DDRSS_PI_210_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A34C 0x0D09000D  //DDRSS_PI_211_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A350 0x0000000D  //DDRSS_PI_212_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A354 0x00000000  //DDRSS_PI_213_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A358 0x00000000  //DDRSS_PI_214_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A35C 0x00000000  //DDRSS_PI_215_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A360 0x00000000  //DDRSS_PI_216_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A364 0x16000000  //DDRSS_PI_217_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A368 0x001600C8  //DDRSS_PI_218_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A36C 0x001600C8  //DDRSS_PI_219_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A370 0x010100C8  //DDRSS_PI_220_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A374 0x00001B01  //DDRSS_PI_221_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A378 0x1F0F0053  //DDRSS_PI_222_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A37C 0x05000001  //DDRSS_PI_223_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A380 0x001B0A0D  //DDRSS_PI_224_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A384 0x1F0F0053  //DDRSS_PI_225_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A388 0x05000001  //DDRSS_PI_226_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A38C 0x001B0A0D  //DDRSS_PI_227_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A390 0x1F0F0053  //DDRSS_PI_228_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A394 0x05000001  //DDRSS_PI_229_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A398 0x00010A0D  //DDRSS_PI_230_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A39C 0x0D0C0700  //DDRSS_PI_231_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A0 0x000D0605  //DDRSS_PI_232_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A4 0x0000C570  //DDRSS_PI_233_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3A8 0x0000001B  //DDRSS_PI_234_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3AC 0x180A0800  //DDRSS_PI_235_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B0 0x0C071C1C  //DDRSS_PI_236_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B4 0x0D06050D  //DDRSS_PI_237_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3B8 0x0000C570  //DDRSS_PI_238_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3BC 0x0000001B  //DDRSS_PI_239_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C0 0x180A0800  //DDRSS_PI_240_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C4 0x0C071C1C  //DDRSS_PI_241_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3C8 0x0D06050D  //DDRSS_PI_242_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3CC 0x0000C570  //DDRSS_PI_243_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D0 0x0000001B  //DDRSS_PI_244_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D4 0x180A0800  //DDRSS_PI_245_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3D8 0x00001C1C  //DDRSS_PI_246_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3DC 0x000030C0  //DDRSS_PI_247_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E0 0x0001E780  //DDRSS_PI_248_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E4 0x000030C0  //DDRSS_PI_249_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3E8 0x0001E780  //DDRSS_PI_250_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3EC 0x000030C0  //DDRSS_PI_251_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F0 0x0001E780  //DDRSS_PI_252_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F4 0x02550255  //DDRSS_PI_253_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3F8 0x03030255  //DDRSS_PI_254_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A3FC 0x00025503  //DDRSS_PI_255_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A400 0x02550255  //DDRSS_PI_256_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A404 0x0C080C08  //DDRSS_PI_257_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A408 0x00000C08  //DDRSS_PI_258_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A40C 0x00089070  //DDRSS_PI_259_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A410 0x00000000  //DDRSS_PI_260_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A414 0x00000000  //DDRSS_PI_261_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A418 0x00000000  //DDRSS_PI_262_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A41C 0x000000D8  //DDRSS_PI_263_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A420 0x00089070  //DDRSS_PI_264_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A424 0x00000000  //DDRSS_PI_265_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A428 0x00000000  //DDRSS_PI_266_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A42C 0x00000000  //DDRSS_PI_267_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A430 0x000000D8  //DDRSS_PI_268_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A434 0x00089070  //DDRSS_PI_269_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A438 0x00000000  //DDRSS_PI_270_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A43C 0x00000000  //DDRSS_PI_271_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A440 0x00000000  //DDRSS_PI_272_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A444 0x020000D8  //DDRSS_PI_273_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A448 0x00000080  //DDRSS_PI_274_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A44C 0x00020000  //DDRSS_PI_275_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A450 0x00000080  //DDRSS_PI_276_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A454 0x00020000  //DDRSS_PI_277_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A458 0x00000080  //DDRSS_PI_278_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A45C 0x00000000  //DDRSS_PI_279_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A460 0x00000000  //DDRSS_PI_280_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A464 0x00040404  //DDRSS_PI_281_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A468 0x00000000  //DDRSS_PI_282_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A46C 0x02010102  //DDRSS_PI_283_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A470 0x67676767  //DDRSS_PI_284_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A474 0x00000202  //DDRSS_PI_285_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A478 0x00000000  //DDRSS_PI_286_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A47C 0x00000000  //DDRSS_PI_287_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A480 0x00000000  //DDRSS_PI_288_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A484 0x00000000  //DDRSS_PI_289_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A488 0x00000000  //DDRSS_PI_290_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A48C 0x0D100F00  //DDRSS_PI_291_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A490 0x0003020E  //DDRSS_PI_292_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A494 0x00000001  //DDRSS_PI_293_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A498 0x01000000  //DDRSS_PI_294_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A49C 0x00020201  //DDRSS_PI_295_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A0 0x00000000  //DDRSS_PI_296_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A4 0x00000424  //DDRSS_PI_297_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4A8 0x00000301  //DDRSS_PI_298_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4AC 0x00000000  //DDRSS_PI_299_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B0 0x00000000  //DDRSS_PI_300_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B4 0x00000000  //DDRSS_PI_301_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4B8 0x00001401  //DDRSS_PI_302_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4BC 0x00000493  //DDRSS_PI_303_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C0 0x00000000  //DDRSS_PI_304_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C4 0x00000424  //DDRSS_PI_305_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4C8 0x00000301  //DDRSS_PI_306_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4CC 0x00000000  //DDRSS_PI_307_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D0 0x00000000  //DDRSS_PI_308_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D4 0x00000000  //DDRSS_PI_309_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4D8 0x00001401  //DDRSS_PI_310_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4DC 0x00000493  //DDRSS_PI_311_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E0 0x00000000  //DDRSS_PI_312_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E4 0x00000424  //DDRSS_PI_313_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4E8 0x00000301  //DDRSS_PI_314_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4EC 0x00000000  //DDRSS_PI_315_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F0 0x00000000  //DDRSS_PI_316_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F4 0x00000000  //DDRSS_PI_317_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4F8 0x00001401  //DDRSS_PI_318_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A4FC 0x00000493  //DDRSS_PI_319_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A500 0x00000000  //DDRSS_PI_320_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A504 0x00000424  //DDRSS_PI_321_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A508 0x00000301  //DDRSS_PI_322_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A50C 0x00000000  //DDRSS_PI_323_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A510 0x00000000  //DDRSS_PI_324_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A514 0x00000000  //DDRSS_PI_325_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A518 0x00001401  //DDRSS_PI_326_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A51C 0x00000493  //DDRSS_PI_327_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A520 0x00000000  //DDRSS_PI_328_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A524 0x00000424  //DDRSS_PI_329_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A528 0x00000301  //DDRSS_PI_330_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A52C 0x00000000  //DDRSS_PI_331_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A530 0x00000000  //DDRSS_PI_332_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A534 0x00000000  //DDRSS_PI_333_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A538 0x00001401  //DDRSS_PI_334_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A53C 0x00000493  //DDRSS_PI_335_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A540 0x00000000  //DDRSS_PI_336_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A544 0x00000424  //DDRSS_PI_337_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A548 0x00000301  //DDRSS_PI_338_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A54C 0x00000000  //DDRSS_PI_339_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A550 0x00000000  //DDRSS_PI_340_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A554 0x00000000  //DDRSS_PI_341_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A558 0x00001401  //DDRSS_PI_342_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A55C 0x00000493  //DDRSS_PI_343_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30A560 0x00000000  //DDRSS_PI_344_DATA
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C000 0x04C00000  //DDRSS_PHY_0_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C004 0x00000000  //DDRSS_PHY_1_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C008 0x00000200  //DDRSS_PHY_2_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C00C 0x00000000  //DDRSS_PHY_3_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C010 0x00000000  //DDRSS_PHY_4_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C014 0x00000000  //DDRSS_PHY_5_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C018 0x00000000  //DDRSS_PHY_6_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C01C 0x00000000  //DDRSS_PHY_7_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C020 0x00000001  //DDRSS_PHY_8_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C024 0x00000000  //DDRSS_PHY_9_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C028 0x000C0000  //DDRSS_PHY_10_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C02C 0x010101FF  //DDRSS_PHY_11_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C030 0x00010000  //DDRSS_PHY_12_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C034 0x00C03804  //DDRSS_PHY_13_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C038 0x00CC0008  //DDRSS_PHY_14_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C03C 0x00660201  //DDRSS_PHY_15_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C040 0x00000000  //DDRSS_PHY_16_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C044 0x00000000  //DDRSS_PHY_17_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C048 0x00000000  //DDRSS_PHY_18_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C04C 0x0000AAAA  //DDRSS_PHY_19_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C050 0x00005555  //DDRSS_PHY_20_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C054 0x0000B5B5  //DDRSS_PHY_21_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C058 0x00004A4A  //DDRSS_PHY_22_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C05C 0x00005656  //DDRSS_PHY_23_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C060 0x0000A9A9  //DDRSS_PHY_24_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C064 0x0000B7B7  //DDRSS_PHY_25_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C068 0x00004848  //DDRSS_PHY_26_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C06C 0x00000000  //DDRSS_PHY_27_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C070 0x00000000  //DDRSS_PHY_28_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C074 0x08000000  //DDRSS_PHY_29_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C078 0x0F000008  //DDRSS_PHY_30_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C07C 0x00000F0F  //DDRSS_PHY_31_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C080 0x00E4E400  //DDRSS_PHY_32_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C084 0x00070820  //DDRSS_PHY_33_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C088 0x000C0020  //DDRSS_PHY_34_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C08C 0x00062000  //DDRSS_PHY_35_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C090 0x00000000  //DDRSS_PHY_36_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C094 0x55555555  //DDRSS_PHY_37_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C098 0xAAAAAAAA  //DDRSS_PHY_38_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C09C 0x55555555  //DDRSS_PHY_39_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A0 0xAAAAAAAA  //DDRSS_PHY_40_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A4 0x00005555  //DDRSS_PHY_41_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0A8 0x01000100  //DDRSS_PHY_42_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0AC 0x00800180  //DDRSS_PHY_43_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B0 0x00000000  //DDRSS_PHY_44_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B4 0x00100000  //DDRSS_PHY_45_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0B8 0x00000000  //DDRSS_PHY_46_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0BC 0x14070010  //DDRSS_PHY_47_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C0 0x00000014  //DDRSS_PHY_48_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C4 0x00000000  //DDRSS_PHY_49_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0C8 0x00300024  //DDRSS_PHY_50_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0CC 0x00000FFF  //DDRSS_PHY_51_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D0 0x00000000  //DDRSS_PHY_52_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D4 0x02B802AC  //DDRSS_PHY_53_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0D8 0x00000030  //DDRSS_PHY_54_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0DC 0x0120003C  //DDRSS_PHY_55_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E0 0x00000000  //DDRSS_PHY_56_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E4 0x0C000000  //DDRSS_PHY_57_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0E8 0x07FF0000  //DDRSS_PHY_58_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0EC 0x00000000  //DDRSS_PHY_59_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F0 0x00000000  //DDRSS_PHY_60_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F4 0x00000000  //DDRSS_PHY_61_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0F8 0x00000000  //DDRSS_PHY_62_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C0FC 0x00000000  //DDRSS_PHY_63_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C100 0x00000000  //DDRSS_PHY_64_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C104 0x00000004  //DDRSS_PHY_65_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C108 0x00000000  //DDRSS_PHY_66_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C10C 0x00000000  //DDRSS_PHY_67_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C110 0x00000000  //DDRSS_PHY_68_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C114 0x00000000  //DDRSS_PHY_69_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C118 0x00000000  //DDRSS_PHY_70_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C11C 0x00000000  //DDRSS_PHY_71_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C120 0x041F07FF  //DDRSS_PHY_72_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C124 0x00000000  //DDRSS_PHY_73_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C128 0x01CCB001  //DDRSS_PHY_74_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C12C 0x2000CCB0  //DDRSS_PHY_75_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C130 0x20000140  //DDRSS_PHY_76_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C134 0x07FF0200  //DDRSS_PHY_77_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C138 0x0000DD01  //DDRSS_PHY_78_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C13C 0x10100303  //DDRSS_PHY_79_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C140 0x10101010  //DDRSS_PHY_80_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C144 0x10101010  //DDRSS_PHY_81_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C148 0x00021010  //DDRSS_PHY_82_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C14C 0x00100010  //DDRSS_PHY_83_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C150 0x00100010  //DDRSS_PHY_84_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C154 0x00100010  //DDRSS_PHY_85_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C158 0x00100010  //DDRSS_PHY_86_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C15C 0x02020010  //DDRSS_PHY_87_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C160 0x51515041  //DDRSS_PHY_88_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C164 0x31804000  //DDRSS_PHY_89_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C168 0x04B80340  //DDRSS_PHY_90_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C16C 0x01008080  //DDRSS_PHY_91_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C170 0x04050001  //DDRSS_PHY_92_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C174 0x00000504  //DDRSS_PHY_93_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C178 0x42100010  //DDRSS_PHY_94_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C17C 0x010C053E  //DDRSS_PHY_95_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C180 0x000F0C14  //DDRSS_PHY_96_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C184 0x01000140  //DDRSS_PHY_97_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C188 0x007A0120  //DDRSS_PHY_98_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C18C 0x00000C00  //DDRSS_PHY_99_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C190 0x000001CC  //DDRSS_PHY_100_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C194 0x20100200  //DDRSS_PHY_101_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C198 0x00000005  //DDRSS_PHY_102_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C19C 0x76543210  //DDRSS_PHY_103_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A0 0x00000008  //DDRSS_PHY_104_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A4 0x02800280  //DDRSS_PHY_105_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1A8 0x02800280  //DDRSS_PHY_106_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1AC 0x02800280  //DDRSS_PHY_107_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B0 0x02800280  //DDRSS_PHY_108_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B4 0x002A0280  //DDRSS_PHY_109_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1B8 0x0000AE00  //DDRSS_PHY_110_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1BC 0x00AE00AE  //DDRSS_PHY_111_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C0 0x00A800AE  //DDRSS_PHY_112_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C4 0x00AE00A8  //DDRSS_PHY_113_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1C8 0x00AE00B4  //DDRSS_PHY_114_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1CC 0x00A200B4  //DDRSS_PHY_115_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D0 0x00A200A8  //DDRSS_PHY_116_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D4 0x00A200A8  //DDRSS_PHY_117_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1D8 0x00AE00A8  //DDRSS_PHY_118_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1DC 0x01B200AE  //DDRSS_PHY_119_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E0 0x01000000  //DDRSS_PHY_120_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E4 0x00000000  //DDRSS_PHY_121_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1E8 0x00000000  //DDRSS_PHY_122_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1EC 0x00080200  //DDRSS_PHY_123_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F0 0x00000000  //DDRSS_PHY_124_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C1F4 0x00000000  //DDRSS_PHY_125_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C400 0x04C00000  //DDRSS_PHY_256_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C404 0x00000000  //DDRSS_PHY_257_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C408 0x00000200  //DDRSS_PHY_258_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C40C 0x00000000  //DDRSS_PHY_259_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C410 0x00000000  //DDRSS_PHY_260_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C414 0x00000000  //DDRSS_PHY_261_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C418 0x00000000  //DDRSS_PHY_262_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C41C 0x00000000  //DDRSS_PHY_263_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C420 0x00000001  //DDRSS_PHY_264_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C424 0x00000000  //DDRSS_PHY_265_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C428 0x000C0000  //DDRSS_PHY_266_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C42C 0x010101FF  //DDRSS_PHY_267_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C430 0x00010000  //DDRSS_PHY_268_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C434 0x00C03804  //DDRSS_PHY_269_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C438 0x00CC0008  //DDRSS_PHY_270_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C43C 0x00660201  //DDRSS_PHY_271_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C440 0x00000000  //DDRSS_PHY_272_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C444 0x00000000  //DDRSS_PHY_273_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C448 0x00000000  //DDRSS_PHY_274_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C44C 0x0000AAAA  //DDRSS_PHY_275_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C450 0x00005555  //DDRSS_PHY_276_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C454 0x0000B5B5  //DDRSS_PHY_277_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C458 0x00004A4A  //DDRSS_PHY_278_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C45C 0x00005656  //DDRSS_PHY_279_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C460 0x0000A9A9  //DDRSS_PHY_280_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C464 0x0000B7B7  //DDRSS_PHY_281_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C468 0x00004848  //DDRSS_PHY_282_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C46C 0x00000000  //DDRSS_PHY_283_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C470 0x00000000  //DDRSS_PHY_284_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C474 0x08000000  //DDRSS_PHY_285_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C478 0x0F000008  //DDRSS_PHY_286_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C47C 0x00000F0F  //DDRSS_PHY_287_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C480 0x00E4E400  //DDRSS_PHY_288_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C484 0x00070820  //DDRSS_PHY_289_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C488 0x000C0020  //DDRSS_PHY_290_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C48C 0x00062000  //DDRSS_PHY_291_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C490 0x00000000  //DDRSS_PHY_292_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C494 0x55555555  //DDRSS_PHY_293_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C498 0xAAAAAAAA  //DDRSS_PHY_294_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C49C 0x55555555  //DDRSS_PHY_295_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A0 0xAAAAAAAA  //DDRSS_PHY_296_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A4 0x00005555  //DDRSS_PHY_297_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4A8 0x01000100  //DDRSS_PHY_298_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4AC 0x00800180  //DDRSS_PHY_299_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B0 0x00000000  //DDRSS_PHY_300_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B4 0x00100000  //DDRSS_PHY_301_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4B8 0x00000000  //DDRSS_PHY_302_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4BC 0x0D070010  //DDRSS_PHY_303_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C0 0x00000013  //DDRSS_PHY_304_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C4 0x00010500  //DDRSS_PHY_305_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4C8 0x0048003C  //DDRSS_PHY_306_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4CC 0x00000FFF  //DDRSS_PHY_307_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D0 0x00000000  //DDRSS_PHY_308_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D4 0x02AC02A0  //DDRSS_PHY_309_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4D8 0x00000030  //DDRSS_PHY_310_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4DC 0x0120003C  //DDRSS_PHY_311_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E0 0x00000000  //DDRSS_PHY_312_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E4 0x0C000000  //DDRSS_PHY_313_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4E8 0x07FF0000  //DDRSS_PHY_314_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4EC 0x00000000  //DDRSS_PHY_315_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F0 0x00000000  //DDRSS_PHY_316_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F4 0x00000000  //DDRSS_PHY_317_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4F8 0x00000000  //DDRSS_PHY_318_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C4FC 0x00000000  //DDRSS_PHY_319_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C500 0x00000000  //DDRSS_PHY_320_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C504 0x00000004  //DDRSS_PHY_321_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C508 0x00000000  //DDRSS_PHY_322_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C50C 0x00000000  //DDRSS_PHY_323_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C510 0x00000000  //DDRSS_PHY_324_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C514 0x00000000  //DDRSS_PHY_325_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C518 0x00000000  //DDRSS_PHY_326_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C51C 0x00000000  //DDRSS_PHY_327_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C520 0x041F07FF  //DDRSS_PHY_328_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C524 0x00000000  //DDRSS_PHY_329_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C528 0x01CCB001  //DDRSS_PHY_330_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C52C 0x2000CCB0  //DDRSS_PHY_331_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C530 0x20000140  //DDRSS_PHY_332_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C534 0x07FF0200  //DDRSS_PHY_333_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C538 0x0000DD01  //DDRSS_PHY_334_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C53C 0x10100303  //DDRSS_PHY_335_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C540 0x10101010  //DDRSS_PHY_336_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C544 0x10101010  //DDRSS_PHY_337_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C548 0x00021010  //DDRSS_PHY_338_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C54C 0x00100010  //DDRSS_PHY_339_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C550 0x00100010  //DDRSS_PHY_340_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C554 0x00100010  //DDRSS_PHY_341_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C558 0x00100010  //DDRSS_PHY_342_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C55C 0x02020010  //DDRSS_PHY_343_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C560 0x51515041  //DDRSS_PHY_344_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C564 0x31804000  //DDRSS_PHY_345_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C568 0x04B80340  //DDRSS_PHY_346_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C56C 0x01008080  //DDRSS_PHY_347_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C570 0x04050001  //DDRSS_PHY_348_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C574 0x00000504  //DDRSS_PHY_349_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C578 0x42100010  //DDRSS_PHY_350_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C57C 0x010C053E  //DDRSS_PHY_351_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C580 0x000F0C14  //DDRSS_PHY_352_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C584 0x01000140  //DDRSS_PHY_353_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C588 0x007A0120  //DDRSS_PHY_354_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C58C 0x00000C00  //DDRSS_PHY_355_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C590 0x000001CC  //DDRSS_PHY_356_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C594 0x20100200  //DDRSS_PHY_357_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C598 0x00000005  //DDRSS_PHY_358_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C59C 0x76543210  //DDRSS_PHY_359_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A0 0x00000008  //DDRSS_PHY_360_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A4 0x02800280  //DDRSS_PHY_361_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5A8 0x02800280  //DDRSS_PHY_362_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5AC 0x02800280  //DDRSS_PHY_363_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B0 0x02800280  //DDRSS_PHY_364_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B4 0x00420280  //DDRSS_PHY_365_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5B8 0x0000AE00  //DDRSS_PHY_366_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5BC 0x00AE00B4  //DDRSS_PHY_367_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C0 0x00AE00AE  //DDRSS_PHY_368_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C4 0x00BA00A8  //DDRSS_PHY_369_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5C8 0x00AE00B4  //DDRSS_PHY_370_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5CC 0x00AE00B4  //DDRSS_PHY_371_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D0 0x00B400B4  //DDRSS_PHY_372_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D4 0x00AE00AE  //DDRSS_PHY_373_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5D8 0x00AE00AE  //DDRSS_PHY_374_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5DC 0x01A600B4  //DDRSS_PHY_375_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E0 0x01000000  //DDRSS_PHY_376_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E4 0x00000000  //DDRSS_PHY_377_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5E8 0x00000000  //DDRSS_PHY_378_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5EC 0x00080200  //DDRSS_PHY_379_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F0 0x00000000  //DDRSS_PHY_380_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C5F4 0x00000000  //DDRSS_PHY_381_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C800 0x00000100  //DDRSS_PHY_512_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C804 0x00001000  //DDRSS_PHY_513_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C808 0x00070000  //DDRSS_PHY_514_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C80C 0x00000000  //DDRSS_PHY_515_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C810 0x00000000  //DDRSS_PHY_516_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C814 0x00000100  //DDRSS_PHY_517_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C818 0x00000000  //DDRSS_PHY_518_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C81C 0x00000000  //DDRSS_PHY_519_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C820 0x00000000  //DDRSS_PHY_520_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C824 0x00000000  //DDRSS_PHY_521_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C828 0x00000000  //DDRSS_PHY_522_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C82C 0x00000000  //DDRSS_PHY_523_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C830 0x00000000  //DDRSS_PHY_524_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C834 0x00DCBA98  //DDRSS_PHY_525_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C838 0x00000000  //DDRSS_PHY_526_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C83C 0x00000000  //DDRSS_PHY_527_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C840 0x00000000  //DDRSS_PHY_528_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C844 0x00000000  //DDRSS_PHY_529_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C848 0x00000000  //DDRSS_PHY_530_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C84C 0x00000100  //DDRSS_PHY_531_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C850 0x00000000  //DDRSS_PHY_532_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C854 0x00000000  //DDRSS_PHY_533_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C858 0x00000000  //DDRSS_PHY_534_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C85C 0x00000000  //DDRSS_PHY_535_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C860 0x00000000  //DDRSS_PHY_536_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C864 0x00000000  //DDRSS_PHY_537_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C868 0x00000000  //DDRSS_PHY_538_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C86C 0x00000000  //DDRSS_PHY_539_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C870 0x0A418820  //DDRSS_PHY_540_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C874 0x103F0000  //DDRSS_PHY_541_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C878 0x000F0100  //DDRSS_PHY_542_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C87C 0x0000000F  //DDRSS_PHY_543_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C880 0x020002CC  //DDRSS_PHY_544_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C884 0x00030000  //DDRSS_PHY_545_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C888 0x00000300  //DDRSS_PHY_546_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C88C 0x00000300  //DDRSS_PHY_547_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C890 0x00000300  //DDRSS_PHY_548_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C894 0x00000300  //DDRSS_PHY_549_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C898 0x00000300  //DDRSS_PHY_550_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C89C 0x42080010  //DDRSS_PHY_551_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A0 0x0000003E  //DDRSS_PHY_552_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A4 0x00000000  //DDRSS_PHY_553_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30C8A8 0x00000000  //DDRSS_PHY_554_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC00 0x00000100  //DDRSS_PHY_768_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC04 0x00001000  //DDRSS_PHY_769_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC08 0x00070000  //DDRSS_PHY_770_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC0C 0x00000000  //DDRSS_PHY_771_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC10 0x00000000  //DDRSS_PHY_772_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC14 0x00000100  //DDRSS_PHY_773_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC18 0x00000000  //DDRSS_PHY_774_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC1C 0x00000000  //DDRSS_PHY_775_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC20 0x00000000  //DDRSS_PHY_776_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC24 0x00000000  //DDRSS_PHY_777_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC28 0x00000000  //DDRSS_PHY_778_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC2C 0x00000000  //DDRSS_PHY_779_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC30 0x00000000  //DDRSS_PHY_780_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC34 0x00DCBA98  //DDRSS_PHY_781_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC38 0x00000000  //DDRSS_PHY_782_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC3C 0x00000000  //DDRSS_PHY_783_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC40 0x00000000  //DDRSS_PHY_784_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC44 0x00000000  //DDRSS_PHY_785_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC48 0x00000000  //DDRSS_PHY_786_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC4C 0x00000100  //DDRSS_PHY_787_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC50 0x00000000  //DDRSS_PHY_788_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC54 0x00000000  //DDRSS_PHY_789_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC58 0x00000000  //DDRSS_PHY_790_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC5C 0x00000000  //DDRSS_PHY_791_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC60 0x00000000  //DDRSS_PHY_792_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC64 0x00000000  //DDRSS_PHY_793_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC68 0x00000000  //DDRSS_PHY_794_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC6C 0x00000000  //DDRSS_PHY_795_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC70 0x16A4A0E6  //DDRSS_PHY_796_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC74 0x103F0000  //DDRSS_PHY_797_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC78 0x000F0000  //DDRSS_PHY_798_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC7C 0x0000000F  //DDRSS_PHY_799_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC80 0x020002CC  //DDRSS_PHY_800_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC84 0x00030000  //DDRSS_PHY_801_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC88 0x00000300  //DDRSS_PHY_802_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC8C 0x00000300  //DDRSS_PHY_803_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC90 0x00000300  //DDRSS_PHY_804_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC94 0x00000300  //DDRSS_PHY_805_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC98 0x00000300  //DDRSS_PHY_806_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CC9C 0x42080010  //DDRSS_PHY_807_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA0 0x0000003E  //DDRSS_PHY_808_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA4 0x00000000  //DDRSS_PHY_809_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30CCA8 0x00000000  //DDRSS_PHY_810_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D000 0x00000100  //DDRSS_PHY_1024_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D004 0x00001000  //DDRSS_PHY_1025_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D008 0x00070000  //DDRSS_PHY_1026_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D00C 0x00000000  //DDRSS_PHY_1027_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D010 0x00000000  //DDRSS_PHY_1028_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D014 0x00000100  //DDRSS_PHY_1029_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D018 0x00000000  //DDRSS_PHY_1030_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D01C 0x00000000  //DDRSS_PHY_1031_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D020 0x00000000  //DDRSS_PHY_1032_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D024 0x00000000  //DDRSS_PHY_1033_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D028 0x00000000  //DDRSS_PHY_1034_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D02C 0x00000000  //DDRSS_PHY_1035_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D030 0x00000000  //DDRSS_PHY_1036_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D034 0x00DCBA98  //DDRSS_PHY_1037_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D038 0x00000000  //DDRSS_PHY_1038_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D03C 0x00000000  //DDRSS_PHY_1039_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D040 0x00000000  //DDRSS_PHY_1040_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D044 0x00000000  //DDRSS_PHY_1041_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D048 0x00000000  //DDRSS_PHY_1042_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D04C 0x00000100  //DDRSS_PHY_1043_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D050 0x00000000  //DDRSS_PHY_1044_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D054 0x00000000  //DDRSS_PHY_1045_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D058 0x00000000  //DDRSS_PHY_1046_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D05C 0x00000000  //DDRSS_PHY_1047_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D060 0x00000000  //DDRSS_PHY_1048_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D064 0x00000000  //DDRSS_PHY_1049_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D068 0x00000000  //DDRSS_PHY_1050_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D06C 0x00000000  //DDRSS_PHY_1051_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D070 0x2307B9AC  //DDRSS_PHY_1052_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D074 0x10030000  //DDRSS_PHY_1053_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D078 0x000F0000  //DDRSS_PHY_1054_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D07C 0x0000000F  //DDRSS_PHY_1055_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D080 0x020002CC  //DDRSS_PHY_1056_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D084 0x00030000  //DDRSS_PHY_1057_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D088 0x00000300  //DDRSS_PHY_1058_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D08C 0x00000300  //DDRSS_PHY_1059_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D090 0x00000300  //DDRSS_PHY_1060_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D094 0x00000300  //DDRSS_PHY_1061_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D098 0x00000300  //DDRSS_PHY_1062_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D09C 0x42080010  //DDRSS_PHY_1063_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A0 0x0000003E  //DDRSS_PHY_1064_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A4 0x00000000  //DDRSS_PHY_1065_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D0A8 0x00000000  //DDRSS_PHY_1066_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D400 0x00000000  //DDRSS_PHY_1280_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D404 0x00000100  //DDRSS_PHY_1281_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D408 0x00000000  //DDRSS_PHY_1282_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D40C 0x00000000  //DDRSS_PHY_1283_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D410 0x00000000  //DDRSS_PHY_1284_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D414 0x00000000  //DDRSS_PHY_1285_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D418 0x00050000  //DDRSS_PHY_1286_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D41C 0x04000100  //DDRSS_PHY_1287_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D420 0x00000055  //DDRSS_PHY_1288_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D424 0x00000000  //DDRSS_PHY_1289_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D428 0x06800000  //DDRSS_PHY_1290_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D42C 0x00000000  //DDRSS_PHY_1291_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D430 0x00000000  //DDRSS_PHY_1292_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D434 0x01002000  //DDRSS_PHY_1293_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D438 0x00004001  //DDRSS_PHY_1294_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D43C 0x00020028  //DDRSS_PHY_1295_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D440 0x00010100  //DDRSS_PHY_1296_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D444 0x00000001  //DDRSS_PHY_1297_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D448 0x00000000  //DDRSS_PHY_1298_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D44C 0x0F0F0E06  //DDRSS_PHY_1299_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D450 0x00010101  //DDRSS_PHY_1300_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D454 0x010F0004  //DDRSS_PHY_1301_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D458 0x00000000  //DDRSS_PHY_1302_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D45C 0x20125770  //DDRSS_PHY_1303_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D460 0x00000064  //DDRSS_PHY_1304_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D464 0x00000000  //DDRSS_PHY_1305_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D468 0x00000000  //DDRSS_PHY_1306_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D46C 0x01020103  //DDRSS_PHY_1307_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D470 0x03020102  //DDRSS_PHY_1308_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D474 0x03030303  //DDRSS_PHY_1309_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D478 0x03030303  //DDRSS_PHY_1310_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D47C 0x00040000  //DDRSS_PHY_1311_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D480 0x00005201  //DDRSS_PHY_1312_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D484 0x00000003  //DDRSS_PHY_1313_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D488 0x00010000  //DDRSS_PHY_1314_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D48C 0x00000000  //DDRSS_PHY_1315_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D490 0x00000003  //DDRSS_PHY_1316_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D494 0x00010000  //DDRSS_PHY_1317_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D498 0x00000000  //DDRSS_PHY_1318_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D49C 0x07070001  //DDRSS_PHY_1319_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A0 0x00005400  //DDRSS_PHY_1320_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A4 0x000040A2  //DDRSS_PHY_1321_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4A8 0x00034890  //DDRSS_PHY_1322_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4AC 0x00014890  //DDRSS_PHY_1323_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B0 0x00014890  //DDRSS_PHY_1324_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B4 0x00014890  //DDRSS_PHY_1325_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4B8 0x00014890  //DDRSS_PHY_1326_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4BC 0x00014890  //DDRSS_PHY_1327_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C0 0x0001491E  //DDRSS_PHY_1328_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C4 0x0001491E  //DDRSS_PHY_1329_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4C8 0x00014890  //DDRSS_PHY_1330_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4CC 0x00014890  //DDRSS_PHY_1331_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D0 0x00000000  //DDRSS_PHY_1332_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D4 0x00000046  //DDRSS_PHY_1333_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4D8 0x00000400  //DDRSS_PHY_1334_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4DC 0x00000008  //DDRSS_PHY_1335_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E0 0x00814890  //DDRSS_PHY_1336_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E4 0x0081491E  //DDRSS_PHY_1337_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4E8 0x00148900  //DDRSS_PHY_1338_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4EC 0x001491E8  //DDRSS_PHY_1339_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F0 0x00F4890F  //DDRSS_PHY_1340_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F4 0x03F491EF  //DDRSS_PHY_1341_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4F8 0x00000000  //DDRSS_PHY_1342_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D4FC 0x00000000  //DDRSS_PHY_1343_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D500 0xB3000000  //DDRSS_PHY_1344_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D504 0x04102006  //DDRSS_PHY_1345_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D508 0x00041020  //DDRSS_PHY_1346_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D50C 0x01C98C98  //DDRSS_PHY_1347_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D510 0x3F400000  //DDRSS_PHY_1348_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D514 0x3F3F1F3F  //DDRSS_PHY_1349_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D518 0x0000001F  //DDRSS_PHY_1350_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D51C 0x00000000  //DDRSS_PHY_1351_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D520 0x00000000  //DDRSS_PHY_1352_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D524 0x00000000  //DDRSS_PHY_1353_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D528 0x00000001  //DDRSS_PHY_1354_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D52C 0x00000000  //DDRSS_PHY_1355_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D530 0x00000000  //DDRSS_PHY_1356_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D534 0x00000000  //DDRSS_PHY_1357_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D538 0x00000000  //DDRSS_PHY_1358_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D53C 0x76543210  //DDRSS_PHY_1359_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D540 0x00000098  //DDRSS_PHY_1360_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D544 0x00000000  //DDRSS_PHY_1361_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D548 0x00000000  //DDRSS_PHY_1362_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D54C 0x00000000  //DDRSS_PHY_1363_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D550 0x00040700  //DDRSS_PHY_1364_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D554 0x00000000  //DDRSS_PHY_1365_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D558 0x00000000  //DDRSS_PHY_1366_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D55C 0x00000000  //DDRSS_PHY_1367_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D560 0x030F7102  //DDRSS_PHY_1368_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D564 0x00000100  //DDRSS_PHY_1369_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D568 0x00000000  //DDRSS_PHY_1370_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D56C 0x0001F7C2  //DDRSS_PHY_1371_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D570 0x00020002  //DDRSS_PHY_1372_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D574 0x00000000  //DDRSS_PHY_1373_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D578 0x00001142  //DDRSS_PHY_1374_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D57C 0x03020400  //DDRSS_PHY_1375_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D580 0x00000080  //DDRSS_PHY_1376_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D584 0x03900390  //DDRSS_PHY_1377_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D588 0x03900390  //DDRSS_PHY_1378_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D58C 0x03900390  //DDRSS_PHY_1379_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D590 0x03900390  //DDRSS_PHY_1380_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D594 0x03900390  //DDRSS_PHY_1381_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D598 0x03900390  //DDRSS_PHY_1382_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D59C 0x00000300  //DDRSS_PHY_1383_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A0 0x00000300  //DDRSS_PHY_1384_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A4 0x00000300  //DDRSS_PHY_1385_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5A8 0x00000300  //DDRSS_PHY_1386_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5AC 0x31823FC7  //DDRSS_PHY_1387_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B0 0x00000000  //DDRSS_PHY_1388_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B4 0x0C000D3F  //DDRSS_PHY_1389_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5B8 0x30000D3F  //DDRSS_PHY_1390_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5BC 0x300D3F11  //DDRSS_PHY_1391_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C0 0x01990000  //DDRSS_PHY_1392_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C4 0x000D3FCC  //DDRSS_PHY_1393_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5C8 0x00000C11  //DDRSS_PHY_1394_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5CC 0x300D3F11  //DDRSS_PHY_1395_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D0 0x01990000  //DDRSS_PHY_1396_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D4 0x300C3F11  //DDRSS_PHY_1397_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5D8 0x01990000  //DDRSS_PHY_1398_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5DC 0x300C3F11  //DDRSS_PHY_1399_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E0 0x01990000  //DDRSS_PHY_1400_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E4 0x300D3F11  //DDRSS_PHY_1401_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5E8 0x01990000  //DDRSS_PHY_1402_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5EC 0x300D3F11  //DDRSS_PHY_1403_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F0 0x01990000  //DDRSS_PHY_1404_DATA_F0
MAIN_Cortex_R5_0_0: GEL Output: 0x0F30D5F4 0x20040004  //DDRSS_PHY_1405_DATA_F0

It appears the program stops at different places at different runs.  Two of them are posted here:

void __attribute__((interrupt("ABORT"), section(".text.hwi"),weak)) HwiP_data_abort_handler_c(void)
{
    volatile uint32_t loop = 1;
    while(loop!=0U)            /* stoped here */
    {
        ;
    }
}

static inline uint32_t HW_RD_FIELD32_RAW(uint32_t addr,
                                         uint32_t mask,
                                         uint32_t shift)
{
    uint32_t regVal = *(volatile uint32_t *) ((uintptr_t) addr); /* stopped here */
    regVal = (regVal & mask) >> shift;
    return (regVal);
}

Could you pls provide any comments on this for further debugging?  thanks. 

Regards,

Larry

Larry, 

you should only be initializing the DDR and setting up DDR ECC once.  That fact that you are doing it twice (once with the boot code from the OSPI, and once with the downloaded .out file) is confusing and is going to cause inconsistent results.

I would recommend the following:

1 Build your code with ECC disabled, flash it into the OSPI, and boot with that code.  Your test code .out file should just be the memory test, it should not initialize DDR again.  If this code passes, then you know you have a robust DDR configuration.

2. Build your code with ECC enabled, flash it into the OSPI, and boot with that code.  Similarly, your test code should just be the memory test.  Now run your test code.  If you get failures, you know there is an issue with the ECC setup.  Most likely there is some issue with priming the memory.  Although, if you setup everything in the MCU+ SDK Sysconfig tool, there should not be an issue.

I'm not sure what System_init() or deinit() does exactly, but you should not need those.  The bootloader in OSPI should be doing your "system init", all you would need to download via JTAG is your test code.

Regards,

James

Hi James，

There might be some miscommunication. 

The original main() is from the demo of TI SDK+. 

System_init() and System_deinit() are the functions from TI MCU+ SDK.   DDR register configuration/initialization is done in System_init().  

Without System_init() in the main(), the DDR won't be initializated.

The test main() we modified  is with System_init() and System_deinit() both added at the very beginning of main(),  in additional to the existing System_init().

We tried building the test program only for DDR test (with ECC enabled)and flash it into QSPI and boot with the code. No JTAG connection.  Two cases:

1. If the test program only has the original System_init() in the beginning of main(),  the test fails as before.   

2. If the test program with System_Init() and System_deinit() added in the very beginning of main(),  the test passes.

Regards,

Larry

Larry, before you load your code, what is booting out of OSPI?  Can you take a register dump before the first System_Init()?  

Regards,

James