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MSP432E401Y: MSP432P401V RTC issue

Zane Wei
Intellectual 1925 points

Part Number: MSP432E401Y

Tool/software:

Hi Team,

RDG260KN and RDG204KN are built to test alternative source of X301(crystal in KNX) and U402 (humidity source). The testing is handled in customer side.
One RDG260KN is reported RTC clock accuracy out range (> 30min/year). The two alternative is not related to RTC clock.

Support need:

  1. Since this accuracy issue has impact on eu-bac certification, could you provide a solution to detect this issue during production test? You know it’s not possible for production line to wait 10min..30min / pcs to check device one by one. Thanks!

Best Regards,

Zane

  • 0
    TI__Guru**** 191886 points

    Hi Zane,

      Can you provide more details how the MCU is used in the end systems? 

      Is hibernate mode used in the final systems?

      What is percentage of the MCUs that is observed to have the RTC inaccuracy issue? 

      Per the TRM, there is a software trim register to allow the user to compensate for oscillator inaccuracies using software. Has the customer used the trim?

    Real-Time Clock
    The RTC module is designed to keep wall time. The RTC can operate in seconds counter mode or
    calendar mode. A 32.768 kHz clock source along with a 15-bit predivider reduces the clock to 1 Hz.
    The 1 Hz clock is used to increment the 32-bit counter and keep track of seconds. In calendar mode,
    registers are provided which support the tracking of date, month, year and day-of-week. A match
    register can be configured to interrupt or wake the system from hibernate. In addition, a software
    trim register is implemented to allow the user to compensate for oscillator inaccuracies using software.

      RTC Trim
    The RTC counting rate can be adjusted to compensate for inaccuracies in the clock source by using
    the predivider trim register, HIBRTCT. This register has a nominal value of 0x7FFF, and is used for
    one second out of every 64 seconds in RTC counter mode, when bits [5:0] in the HIBRTCC register
    change from 0x00 to 0x01, to divide the input clock. Trim is applied every 60 seconds in calendar
    mode. This configuration allows the software to make fine corrections to the clock rate by adjusting
    the predivider trim register up or down from 0x7FFF. The predivider trim should be adjusted up from
    0x7FFF in order to slow down the RTC rate and down from 0x7FFF in order to speed up the RTC
    rate.
    Care must be taken when using trim values that are near to the sub seconds match value in the
    HIBRTCSS register. It is possible when using trim values above 0x7FFF to receive two match
    interrupts for the same counter value. In addition, it is possible when using trim values below 0x7FFF
    to miss a match interrupt.
    In the case of a trim value above 0x7FFF, when the RTCSSC value in the HIBRTCSS register reaches
    0x7FFF, the RTCC value increments from 0x0 to 0x1 while the RTCSSC value is decreased by the
    trim amount. The RTCSSC value is counted up again to 0x7FFF before rolling over to 0x0 to begin
    counting up again. If the match value is within this range, the match interrupt is triggered twice. For
    example, as shown in Figure 7-5 on page 542, if the match interrupt was configured with RTCM0=0x1
    and RTCSSM=0x7FFD, two interrupts would be triggered.