TM4C123GH6PM: UART Delay

Hi,

  I suppose you use xMBPortSerialGetByte to receive UART data and xMBPortSerialGetByte to send UART data. Is that a correct understanding? Why don't you do as follows for diagnosis of the delay?

  1. Set a GPIO pin high at the end of prvvUARTTxReadyISR and then clear the pin at the end of xMBPortSerialGetByte. This will measure the time a receive UART ISR is entered until the the UART char is actually read out. I want to know how much time your protocol stack is involved in this process. 

  2. Set a GPIO pin high at the end of prvvUARTTxReadyISR and then clear the pin at the end of xMBPortSerialPutByte. This will measure the time a transmit UART ISR is entered until the the UART char is transmitted.

  3. Set a GPIO pin high at the end of xMBPortSerialGetByte and then clear the pin at the end of xMBPortSerialPutByte. I want to know how much time your protocol stack spend between receiving a UART char and sending a UART char. 

 You can use the GPIO at places as you see fit to narrow down places where the delay is taking place. The delay may be in your protocol stack that is not shown in your snippet of code. 

Hi Charles,

Sorry for the late reply, but we were devastated by hurricane Helene. No power, water, or internet for a week. I modified portserial.c to turn gpio pins ON and OFF in accordance with the debug instructions you provided. the modified portserial.c is here,

/*
 * FreeModbus Libary: BARE Port
 * Copyright (C) 2006 Christian Walter <wolti@sil.at>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 *
 * File: $Id$
 */

#include "port.h"

/* ----------------------- Modbus includes ----------------------------------*/
#include "mb.h"
#include "mbport.h"

//TI Tiva Includes
#include <stdint.h>
#include <stdbool.h>

#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/hw_gpio.h"

#include "driverlib/debug.h"
#include "driverlib/fpu.h"
#include "driverlib/gpio.h"
#include "driverlib/interrupt.h"
#include "driverlib/pin_map.h"
#include "driverlib/sysctl.h"
#include "driverlib/uart.h"


/* ----------------------- static functions ---------------------------------*/
void prvvUARTTxReadyISR( void );
void prvvUARTRxISR( void );

/* ----------------------- Start implementation -----------------------------*/
void
vMBPortSerialEnable( BOOL xRxEnable, BOOL xTxEnable )
{
    /* If xRXEnable enable serial receive interrupts. If xTxENable enable
     * transmitter empty interrupts.
     */
    if( xRxEnable )
    {
        UARTIntEnable(UART0_BASE, UART_INT_RX|UART_INT_RT);
        UARTIntRegister(UART0_BASE, &prvvUARTRxISR);

        GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_2, 0); //UART_TX_EN (Active High) -> TX OFF
        GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, 0); //UART_RX_EN (Active Low) -> RX ON
    }
    else
    {
        UARTIntDisable(UART0_BASE, UART_INT_RX);

        GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_PIN_2); //UART_TX_EN (Active High) -> TX OFF
        GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); //UART_RX_EN (Active Low) -> RX ON
    }

    if( xTxEnable )
    {
        UARTIntEnable(UART0_BASE, UART_INT_TX);
        UARTIntRegister(UART0_BASE, &prvvUARTTxReadyISR);

        GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_PIN_2); //UART_TX_EN (Active High) -> TX ON
        GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); //UART_RX_EN (Active Low) -> RX OFF
    }
    else
    {
        UARTIntDisable(UART0_BASE,UART_INT_TX);

        GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_2, 0); //UART_TX_EN (Active High) -> TX OFF
        GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, 0); //UART_RX_EN (Active Low) -> RX ON
    }
}

BOOL
xMBPortSerialInit( UCHAR ucPORT, ULONG ulBaudRate, UCHAR ucDataBits, eMBParity eParity )
{
    //Vars

    (void)ucPORT;
    uint32_t Parity,Bits,StopBits;
    //Enable the GPIO Peripheral used by the UART.
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
    // Enable UART0
    SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);

    while(!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOA))
    {
    }

    while(!SysCtlPeripheralReady(SYSCTL_PERIPH_UART0))
    {
    }

    // Configure GPIO Pins for UART mode.
    GPIOPinConfigure(GPIO_PA0_U0RX);
    GPIOPinConfigure(GPIO_PA1_U0TX);
    GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);

    // Select the length and Parity of UART
    switch( eParity )
    {
    case MB_PAR_EVEN:
        Parity = UART_CONFIG_PAR_EVEN;
        StopBits = UART_CONFIG_STOP_ONE;
        break;
    case MB_PAR_ODD:
        Parity = UART_CONFIG_PAR_ODD;
        StopBits = UART_CONFIG_STOP_ONE;
        break;
    case MB_PAR_NONE:
        Parity = UART_CONFIG_PAR_NONE;
        StopBits = UART_CONFIG_STOP_ONE;
        break;
    }

    switch( ucDataBits )
    {
    case 8:
        Bits = UART_CONFIG_WLEN_8;
        break;
    case 7:
        Bits = UART_CONFIG_WLEN_7;
        break;
    }

    // Initialize the UART for console I/O.
    UARTConfigSetExpClk(UART0_BASE,
                        SysCtlClockGet(),
                        ulBaudRate,
                        (Bits | StopBits | Parity));
    //Disable the fifo in order to ensure the interrupt is only for a change in RX
    UARTFIFODisable(UART0_BASE);
    // Enable UART & Interrupts
    UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT);
    UARTIntRegister(UART0_BASE,&prvvUARTRxISR);
    UARTEnable(UART0_BASE);

    //Enable the GPIO Pins.
    GPIOPinUnlockGPIO(GPIO_PORTA_BASE, GPIO_PIN_2);
    GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_2); //TX EN
    GPIOPinUnlockGPIO(GPIO_PORTA_BASE, GPIO_PIN_3);
    GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_3); //RX EN

    GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_2, 0); //UART_TX_EN (Active High)
    GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, 0); //UART_RX_EN (Active Low)

    return TRUE;
}

BOOL
xMBPortSerialPutByte( CHAR ucByte )
{
    /* Put a byte in the UARTs transmit buffer. This function is called
     * by the protocol stack if pxMBFrameCBTransmitterEmpty( ) has been
     * called. */
    UARTCharPut(UART0_BASE, ucByte);
    while (UARTBusy(UART0_BASE))
    {
    }
    GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_2, 0); //2.CLEAR. Timing Between TX UART ISR and Transmit
    GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_0, 0); //3.CLEAR. Timing Between RX CHAR and TX CHAR
    return TRUE;
}

BOOL
xMBPortSerialGetByte( CHAR * pucByte )
{
    /* Return the byte in the UARTs receive buffer. This function is called
     * by the protocol stack after pxMBFrameCBByteReceived( ) has been called.
     */
    uint32_t ui32Status;
    ui32Status = UARTIntStatus(UART0_BASE, true);
    UARTIntClear(UART0_BASE,ui32Status);

    *pucByte = UARTCharGet(UART0_BASE);

    GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_4, 0); //1.CLEAR. Timing Between RX UART ISR and Read Out
    GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_0, GPIO_PIN_0); //3.HIGH. Timing Between RX CHAR and TX CHAR
    return TRUE;
}

/* Create an interrupt handler for the transmit buffer empty interrupt
 * (or an equivalent) for your target processor. This function should then
 * call pxMBFrameCBTransmitterEmpty( ) which tells the protocol stack that
 * a new character can be sent. The protocol stack will then call 
 * xMBPortSerialPutByte( ) to send the character.
 */
void prvvUARTTxReadyISR( void )
{
    pxMBFrameCBTransmitterEmpty(  );
    GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_4, GPIO_PIN_4); //1.HIGH. Timing Between RX UART ISR and Read Out
    GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_2, GPIO_PIN_2); //2.HIGH. Timing Between TX UART ISR and Transmit
}

/* Create an interrupt handler for the receive interrupt for your target
 * processor. This function should then call pxMBFrameCBByteReceived( ). The
 * protocol stack will then call xMBPortSerialGetByte( ) to retrieve the
 * character.
 */
void prvvUARTRxISR(void)
{
    pxMBFrameCBByteReceived(  );
}

void vMBPPortEnterCritical()
{

}

void vMBPPortExitCritical()
{

}

The results are pretty confusing.

Channel 1 is GPIO Pin PF4, Channel 2 is Pin PE2, Channel 3 is Pin PE0, Channel 4 is the UART Bus.

Thanks,

Allan

Based on your waveforms this is what I interpret:

JAOverstreet said:

Sorry for the late reply, but we were devastated by hurricane Helene. No power, water, or internet for a week.

Hope everything is well with you now. We also had Beryl hitting Texas this past summer. We were without power for many days with 100F temperature. 

PE2 stays high for a very long time once prvvUARTTxReadyISR is entered until it is cleared in  xMBPortSerialPutByte. This tells me that UART TX is empty for you to write data to its TXFIFO but you haven't received anything on the RX and therefore didn't write anything to the TXFIFO yet.

PE0: The time from xMBPortSerialGetByte to xMBPortSerialPutByte is also very long. You did not capture enough waveform when PE0 is first set. All I can see is that PE0 stays high for a long time. This means it has read something from the RXFIFO but didn't write to the TXFIFO yet. 

PF4: You are measuring time from when prvvUARTTxReadyISR is entered until xMBPortSerialGetByte is called. This pulse is quite short. This tells me as soon as TXFIFO is empty then it will quickly send out the characters. By the time the next char is received, PF4 is cleared. 

From what I see, I have a question. Why do you want to wait for TXFIFO to be empty before transmitting out chars?  Why don't you transmit out chars as soon as you are done reading chars? In another word, why don't you call xMBPortSerialPutByte as soon as you are done with xMBPortSerialGetByte instead of waiting for TXFIFO to be empty.

Hi Charles,

I am not sure how to respond to your post.

I don't want to have to modify the FreeModBus library extensively to get it to work.

The code was originally written for a MSP430 microcontroller. The MSP430 has interrupts for the TX FIFO being empty. I think that is why there is a delay for the TX FIFO.

I did some more debugging and I think I have narrowed down the problem.

I set pin PE0 to toggle by modifying the prvvTIMERExpiredISR() function in porttimer.c,

/*
 * FreeModbus Libary: BARE Port
 * Copyright (C) 2006 Christian Walter <wolti@sil.at>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 *
 * File: $Id$
 */

/* ----------------------- Platform includes --------------------------------*/
#include "port.h"

/* ----------------------- Modbus includes ----------------------------------*/
#include "mb.h"
#include "mbport.h"

#include <stdint.h>
#include <stdbool.h>

#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/hw_gpio.h"

#include "driverlib/debug.h"
#include "driverlib/fpu.h"
#include "driverlib/gpio.h"
#include "driverlib/interrupt.h"
#include "driverlib/pin_map.h"
#include "driverlib/sysctl.h"
#include "driverlib/uart.h"
#include "driverlib/timer.h"

/* ----------------------- static functions ---------------------------------*/
static void prvvTIMERExpiredISR( void );

/* Global Vars */
uint32_t a;

/* ----------------------- Start implementation -----------------------------*/
BOOL
xMBPortTimersInit( USHORT usTim1Timerout50us )
{
    SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0);
    TimerConfigure(TIMER0_BASE, TIMER_CFG_ONE_SHOT);
    a = ((usTim1Timerout50us*SysCtlClockGet())/20000)-1; //Original
    TimerLoadSet(TIMER0_BASE, TIMER_A, a);
    TimerIntRegister(TIMER0_BASE, TIMER_A, prvvTIMERExpiredISR);
    IntEnable(INT_TIMER0A);
    TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
    TimerEnable(TIMER0_BASE, TIMER_A);

     return TRUE;
}


inline void
vMBPortTimersEnable(  )
{
    /* Enable the timer with the timeout passed to xMBPortTimersInit( ) */
    TimerLoadSet(TIMER0_BASE, TIMER_A, a);
    TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
    TimerEnable(TIMER0_BASE, TIMER_A);
}

inline void
vMBPortTimersDisable(  )
{
   /* Disable any pending timers. */
   TimerDisable(TIMER0_BASE,TIMER_A);
   TimerIntDisable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
   TimerIntClear(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
}

/* Create an ISR which is called whenever the timer has expired. This function
 * must then call pxMBPortCBTimerExpired( ) to notify the protocol stack that
 * the timer has expired.
 */
static void prvvTIMERExpiredISR( void )
{
    uint32_t pin_e0 = GPIOPinRead(GPIO_PORTE_BASE, GPIO_PIN_0);
    TimerIntClear(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
    ( void )pxMBPortCBTimerExpired(  );
    pin_e0 = ~pin_e0;
    GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_0, pin_e0);
}

Toggling this pin produces a delay about the same amount of time between RX and TX.

I tried reducing the delay by modifying the timer configuration, but reducing the delay too much prevents the MCU from transmitting anything at all.

When the delay is too short you get four PE0 pulses and no TX.

Channel setup is still the same.

Channel 1 is GPIO Pin PF4, Channel 2 is Pin PE2, Channel 3 is Pin PE0, Channel 4 is the UART Bus.

Changing vMBPortTimersEnable() in porttimer.c to try and force it to TX now prevents the MCU from transmitting,

inline void
vMBPortTimersEnable(  )
{
    /* Enable the timer with the timeout passed to xMBPortTimersInit( ) */
    //TimerLoadSet(TIMER0_BASE, TIMER_A, a);
    //TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
    //TimerEnable(TIMER0_BASE, TIMER_A);
    //Don't Wait Transmit Now!
    (  void  )prvvTIMERExpiredISR();
}

You get the same four PE0 pulses and no data back from the MCU.

Thanks,

Allan

JAOverstreet said:

The code was originally written for a MSP430 microcontroller. The MSP430 has interrupts for the TX FIFO being empty.

Hi Allan,

  MSP430 is architecturally different from Tiva MCU and the UART module is also different between them in terms of how they handle interrupts. If you refer to the datasheet, the Tiva UART module generates TX interrupt based on a programmable number of data in the TXFIFO. It is not based TXFIFO being empty. You will need to take this into consideration. I'm not familiar with MSP430 but I don't think its UART has an FIFO. What I will suggest you try is to disable the TXFIFO. The FEN bit in the UARTLCRH register is used to enabled/disable FIFO. You can call UARTFIFODisable() to disable the FIFO.

  I also want to give you a heads up that I will be out of office for a week. My response will be much delayed. Sorry for the inconvenience. 

The receive interrupt changes state when one of the following events occurs:
■ If the FIFOs are enabled and the receive FIFO reaches the programmed trigger level, the RXRIS
bit is set. The receive interrupt is cleared by reading data from the receive FIFO until it becomes
less than the trigger level, or by clearing the interrupt by writing a 1 to the RXIC bit.

■ If the FIFOs are disabled (have a depth of one location) and data is received thereby filling the
location, the RXRIS bit is set. The receive interrupt is cleared by performing a single read of the
receive FIFO, or by clearing the interrupt by writing a 1 to the RXIC bit.

The transmit interrupt changes state when one of the following events occurs:
■ If the FIFOs are enabled and the transmit FIFO progresses through the programmed trigger
level, the TXRIS bit is set. The transmit interrupt is based on a transition through level, therefore
the FIFO must be written past the programmed trigger level otherwise no further transmit interrupts
will be generated. The transmit interrupt is cleared by writing data to the transmit FIFO until it
becomes greater than the trigger level, or by clearing the interrupt by writing a 1 to the TXIC bit.

■ If the FIFOs are disabled (have a depth of one location) and there is no data present in the
transmitters single location, the TXRIS bit is set. It is cleared by performing a single write to the
transmit FIFO, or by clearing the interrupt by writing a 1 to the TXIC bit.