Tool/software:

Hi team,

I'm configuring new f lash via CCS and reffer this AM273x MCU+ SDK: Writing flash driver for a custom flash device steps. when I'm in

Step 4: Test the new flash driver with the changes using QSPI Flash transfer example

, I got this error shown below. This error may happen after I choose the new driver and run the Flash transfer example 

[Cortex_R5_0] ERROR: Board_flashOpen:98: FLASH open failed for instance 0 !!!
[QSPI Flash Transfer Test] Starting ...
[QSPI Flash Transfer Test] Executing Flash Erase on first block...
[QSPI Flash Transfer Test] Performing Write-Read Test...
ERROR: qspi_flash_diag_test_compare_buffers:127: QSPI read data mismatch !!!
Some tests have failed!!

(1) I got current flash information from qspi_flash_diag project

[Cortex_R5_0] [QSPI Flash Diagnostic Test] Starting ...
[QSPI Flash Diagnostic Test] Flash Manufacturer ID : 0xEF
[QSPI Flash Diagnostic Test] Flash Device ID : 0x9020
[QSPI Flash Diagnostic Test] Executing Flash Erase on first block...
[QSPI Flash Diagnostic Test] Done !!!
[QSPI Flash Diagnostic Test] Performing Write-Read Test...
[QSPI Flash Diagnostic Test] Write-Read Test Passed!
[QSPI Flash Diagnostic Test] SFDP Information :
================================================
SFDP
================================================
SFDP Major Revision : 0x1
SFDP Minor Revision : 0x6
Number of Parameter Headers in this Table : 2

Types of Additional Parameter Tables in this flash
---------------------------------------------------
4 BYTE ADDRESSING MODE INSTRUCTIONS TABLE

Flash_NorSpiDevDefines gFlashNorSpiDeviceDefines_<part-number> = {

.NOR_SPI_CMD_RSTEN = 0x66,
.NOR_SPI_CMD_RSTMEM = 0x99,
.NOR_SPI_CMD_WREN = 0x06,
.NOR_SPI_CMD_WRREG = 0x00,
.NOR_SPI_CMD_BULK_ERASE = 0xC7,
.NOR_SPI_CMD_SECTOR_ERASE_3B = 0x20,
.NOR_SPI_CMD_SECTOR_ERASE_4B = 0x21,
.NOR_SPI_CMD_BLOCK_ERASE_3B = 0xD8,
.NOR_SPI_CMD_BLOCK_ERASE_4B = 0xDC,
.NOR_SPI_CMD_PAGE_PROG_3B = 0x02,
.NOR_SPI_CMD_PAGE_PROG_4B = 0x12,
.NOR_SPI_CMD_RDSR = 0x05,
.NOR_SPI_CMD_RDREG = 0x00,
.NOR_SPI_CMD_RDID = 0x9F,
.NOR_SPI_CMD_READ = 0x03,
.NOR_SPI_CMD_888_SDR_READ = 0x00,
.NOR_SPI_CMD_888_DDR_READ = 0x00,
.NOR_SPI_CMD_444_SDR_READ = 0xEB,
.NOR_SPI_CMD_444_DDR_READ = 0x00,
.NOR_SPI_CMD_114_READ = 0x6B,
.NOR_SPI_SR_WIP = 0,
.NOR_SPI_SR_WEL = 0,
.NOR_SPI_RDID_NUM_BYTES = 5,
.NOR_SPI_MANF_ID = 0xEF,
.NOR_SPI_DEVICE_ID = 0x9020,
.NOR_SPI_114_READ_MODE_CLKS = 0,
.NOR_SPI_114_READ_DUMMY_CYCLES = 8,
.NOR_SPI_444_READ_MODE_CLKS = 2,
.NOR_SPI_444_READ_DUMMY_CYCLES = 0,
.NOR_SPI_444_READ_DUMMY_CYCLES_LC = 0x00,
.NOR_SPI_QUAD_CMD_READ_DUMMY_CYCLES = 0x00,
.NOR_SPI_OCTAL_READ_DUMMY_CYCLE = 0,
.NOR_SPI_OCTAL_READ_DUMMY_CYCLE_LC = 0x00,
.NOR_SPI_OCTAL_DDR_RDSR_DUMMY_CYCLE = 0,
.NOR_SPI_OCTAL_DDR_RDREG_ADDR_BYTES = 0,
.NOR_SPI_OCTAL_DDR_WRREG_ADDR_BYTES = 0,
.NOR_SPI_OCTAL_DDR_RDVREG_DUMMY_CYCLE = 0,
.NOR_SPI_OCTAL_DDR_RDNVREG_DUMMY_CYCLE = 0,
.NOR_SPI_OCTAL_RDSFDP_DUMMY_CYCLE = 0,
.NOR_SPI_OCTAL_RDSFDP_ADDR_TYPE = 0,
.NOR_SPI_WRR_WRITE_TIMEOUT = 7040,
.NOR_SPI_BULK_ERASE_TIMEOUT = 192000000,
.NOR_SPI_PAGE_PROG_TIMEOUT = 704,
.NOR_SPI_VREG_OFFSET = 0x0,
.NOR_SPI_NVREG_OFFSET = 0x0,
.NOR_SPI_QUAD_MODE_CFG_ADDR = 0x0,
.NOR_SPI_QUAD_MODE_CFG_BIT_LOCATION = 0x0,
.NOR_SPI_DDR_OCTAL_MODE_CFG_ADDR = 0x0,
.NOR_SPI_DDR_OCTAL_MODE_CFG_BIT_LOCATION = 0x0,
.NOR_SPI_DUMMY_CYCLE_CFG_ADDR = 0x0,
.NOR_SPI_FLASH_SIZE = 67108864,
.NOR_SPI_PAGE_SIZE = 256,
.NOR_SPI_BLOCK_SIZE = 65536,
.NOR_SPI_SECTOR_SIZE = 4096,
.addrByteSupport = 1,
.dtrSupport = 1,
.qeType = 4,
.seq444Enable = { 1, 0, 0, 0, 1 },
.seq444Disable = { 1, 0, 0, 1 },
.oeType = 0,
.cmdExtType = 0,
.byteOrder = 0,
};

All tests have passed!!

(2) This is my new flash c file(flash_nor_qspi_device_W25H512J.c). I modified it with the information of (1).

#include <board/flash.h>

Flash_NorQspiDevDefines gFlashNorQspiDeviceDefines_W25H512J = {
.NOR_CMD_RDID = 0x9FU, //
.NOR_CMD_SINGLE_READ = 0x03U, // read data
.NOR_CMD_QUAD_READ = 0x6CU, //
.NOR_PAGE_PROG = 0x12U,//
.NOR_CMD_RSTEN = 0x66U,//
.NOR_CMD_RST = 0x99U,//
.NOR_RDID_NUM_BYTES = 0x5U, //
.NOR_MANF_ID = 0xEFU, //
.NOR_DEVICE_ID = 0x9020U, //
.NOR_CMD_WREN = 0x06U, //Write Enable
.NOR_CMD_WRSR = 0x01U, //
.NOR_CMD_RDSR1 = 0x05U, //
.NOR_CMD_RDSR2 = 0x35U, //
.NOR_CMD_SECTOR_ERASE = 0x21U, //
.NOR_CMD_BLOCK_ERASE = 0xDCU,//
.NOR_CMD_BULK_ERASE = 0xC7U, //Chip Erase
.NOR_QUAD_READ_DUMMY_CYCLE = 0U,
.NOR_BULK_ERASE_TIMEOUT = 192000000U,
.NOR_WRR_WRITE_TIMEOUT = 7040U,
.NOR_PAGE_PROG_TIMEOUT = 704U,
.NOR_PAGE_SIZE = 256U,
.NOR_ADDR_NUM_BYTES = 4U,
};

#define FLASH_SIZE (64U * 1024U * 1024U)
#define FLASH_BLOCK_SIZE (64U * 1024U)
#define FLASH_PAGE_SIZE (256U)
#define FLASH_SECTOR_SIZE (4096U)
#define FLASH_NUM_BLOCKS (FLASH_SIZE / FLASH_BLOCK_SIZE)
#define FLASH_NUM_PAGES_PER_BLOCK (FLASH_BLOCK_SIZE / FLASH_PAGE_SIZE)

Flash_Attrs gFlashNorQspiAttrs_W25H512J =
{
.deviceId = 0, /* filled by Flash_open, after querying the flash */
.manufacturerId = 0, /* filled by Flash_open, after querying the flash */
.driverInstance = 0, /* filled by SysConfig */
.flashSize = FLASH_SIZE,
.blockCount = FLASH_NUM_BLOCKS,
.blockSize = FLASH_BLOCK_SIZE,
.pageCount = FLASH_NUM_PAGES_PER_BLOCK,
.pageSize = FLASH_PAGE_SIZE,
.sectorSize = FLASH_SECTOR_SIZE, /* NOT USED */
.sectorCount = 0, /* NOT USED */
};

Could you please help me check if my new driver configuration is correct? And how to fix this issue?

Thank you so much 

Amy