Tool/software:

Hi 

I am using the MSPM0G3106/MSPM0G3507 for a UART DMA communication running at the following configuration. 

Baud rate - 2mbps 

CPU clock - 80Mhz 

MCLK - 80Mhz 

ULPCLK - 40Mhz ( max possible as per TRM ) 

UART0 ( Power Domain 0)  being used which refers to ULPCLK at 40Mhz ( max)  as the BUSCLK for its operation. DMA is used  for RX and TX  with  the Triggers Set to transfer to and from RX/TX FIFOs. DMA ( Power Domain 1 ). 


Problem Statement: 

We are a TX Task running at 1ms , which creates packets of max 130 bytes at a time which will be the source buffer for the DMA to push to the UART TX FIFO.  With an Internal Loopback enabled , we are observing random 1 or 2 bytes missing from the Packet transmitted. we have validated the packet structure till the buffer is given for UART DMA transaction, so the issue has to be the UART/DMA  layer itself. 

Observations :

1. The same code with the MCLK and CPU CLOCK set to 40Mhz , along with ULPCLK also at 40Mhz seems to be not giving the issue. 

2. On a launchpad ,the  same test conducted by using UART3 (PD1) instead of UART0(PD0) there by using the MCLK 80Mhz for UART3(PD1) - this setup is also working with the missing of bytes. 


Is there any recommendations for using UART0 DMA with ULPCLK -40Mhz , MCLK - 80Mhz , CPU CLOCK - 80Mhz  for attaining stability ? 



Please find the code snippet for the configurations used when the issue is observed  :

Clock Configurations ( SYS PLL) :

static const DL_SYSCTL_SYSPLLConfig gSYSPLLConfig = {
    .inputFreq              = DL_SYSCTL_SYSPLL_INPUT_FREQ_16_32_MHZ,
    .rDivClk2x              = 0,
    .rDivClk1               = 0,
    .rDivClk0               = 0,
    .enableCLK2x            = DL_SYSCTL_SYSPLL_CLK2X_DISABLE,
    .enableCLK1             = DL_SYSCTL_SYSPLL_CLK1_ENABLE,
    .enableCLK0             = DL_SYSCTL_SYSPLL_CLK0_ENABLE,
    .sysPLLMCLK             = DL_SYSCTL_SYSPLL_MCLK_CLK0,
    .sysPLLRef              = DL_SYSCTL_SYSPLL_REF_SYSOSC,
    .qDiv                   = 9,
    .pDiv                   = DL_SYSCTL_SYSPLL_PDIV_2
};


    DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
    DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *) &gSYSPLLConfig);
    DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK, DL_SYSCTL_HSCLK_SOURCE_SYSPLL);
    DL_SYSCTL_setULPCLKDivider(DL_SYSCTL_ULPCLK_DIV_2);
    //Low Power Mode is configured to be SLEEP0
    DL_SYSCTL_setBORThreshold(DL_SYSCTL_BOR_THRESHOLD_LEVEL_0);
    DL_SYSCTL_setFlashWaitState(DL_SYSCTL_FLASH_WAIT_STATE_2);

UART0 & DMA configurations:

DL_UART_Main_setOversampling(UART_INST, DL_UART_OVERSAMPLING_RATE_16X);

DL_UART_Main_setBaudRateDivisor(UART_INST, UART_IBRD_40_MHZ_2000000_BAUD, UART_FBRD_40_MHZ_2000000_BAUD);

DL_UART_Main_enableDMAReceiveEvent(UART_INST, DL_UART_DMA_INTERRUPT_RX);
DL_UART_Main_enableDMATransmitEvent(UART_INST);

    /* Configure FIFOs */
    DL_UART_Main_enableFIFOs(UART_INST);
    DL_UART_Main_setRXFIFOThreshold(UART_INST, DL_UART_RX_FIFO_LEVEL_ONE_ENTRY);
    DL_UART_Main_setTXFIFOThreshold(UART_INST, DL_UART_TX_FIFO_LEVEL_ONE_ENTRY);


/* Configuration for UART 0 Peripheral  */
static const DL_UART_Main_ClockConfig gUART_ClockConfig = {
    .clockSel    = DL_UART_MAIN_CLOCK_BUSCLK,
    .divideRatio = DL_UART_MAIN_CLOCK_DIVIDE_RATIO_1
};

static const DL_UART_Main_Config gUART_Config = {
    .mode        = DL_UART_MAIN_MODE_NORMAL,
    .direction   = DL_UART_MAIN_DIRECTION_TX_RX,
    .flowControl = DL_UART_MAIN_FLOW_CONTROL_NONE,
    .parity      = DL_UART_MAIN_PARITY_NONE,
    .wordLength  = DL_UART_MAIN_WORD_LENGTH_8_BITS,
    .stopBits    = DL_UART_MAIN_STOP_BITS_ONE
};




/*configuration for DMA TX channel - Channel 1*/
static const DL_DMA_Config gDMA_CH1Config = {
    .transferMode   = DL_DMA_SINGLE_TRANSFER_MODE,
    .extendedMode   = DL_DMA_NORMAL_MODE,
    .destIncrement  = DL_DMA_ADDR_UNCHANGED,
    .srcIncrement   = DL_DMA_ADDR_INCREMENT,
    .destWidth      = DL_DMA_WIDTH_BYTE,
    .srcWidth       = DL_DMA_WIDTH_BYTE,
    .trigger        = UART_INST_DMA_TRIGGER_1,
    .triggerType    = DL_DMA_TRIGGER_TYPE_EXTERNAL,
};


/*configuration for DMA RX channel - Channel 0*/
static const DL_DMA_Config gDMA_CH0Config = {
    .transferMode   = DL_DMA_FULL_CH_REPEAT_SINGLE_TRANSFER_MODE,
    .extendedMode   = DL_DMA_NORMAL_MODE,
    .destIncrement  = DL_DMA_ADDR_INCREMENT,
    .srcIncrement   = DL_DMA_ADDR_UNCHANGED,
    .destWidth      = DL_DMA_WIDTH_BYTE,
    .srcWidth       = DL_DMA_WIDTH_BYTE,
    .trigger        = UART_INST_DMA_TRIGGER_0,
    .triggerType    = DL_DMA_TRIGGER_TYPE_EXTERNAL,
};