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Original question:

MCU-PLUS-SDK-AM243X: How to Perform DDR ECC Fault Injection Test in EMIF

MCU-PLUS-SDK-AM243X: Writing to DDR when ECC is enabled

Katsuyuki Sasajima
Prodigy 50 points
Part Number: MCU-PLUS-SDK-AM243X

Tool/software:

I have an additional related question.

I think it is possible to write a program that maps a variable with initialization to DDR if ECC is enabled (ECC_EN(ECC_CTRL_REG[0])) and ECC_CK(ECC_CTRL_REG[2]) is 0, before expanding it to DDR.

When I looked at the initial value, the initial value was not written and the memory showed ALL 0xAA.
By the way, the area where the initial value is mapped is the range of non-ECC area.

If ECC is disabled, the initial value is written normally.
Is this behavior a specification?

Translated with DeepL.com (free version)

  • 0
    TI__Mastermind 20376 points

    Hello,

    Apologies for the delay.

    I am not sure I understand the above statement properly.

    Are you saying the writes to DDR are not happening properly when the ECC is enabled and the same writes go through when ECC is disabled? Are you trying to write to DDR after the DDR_inlineECCCfg function? 

    Regards,

    Nihar Potturu. 

  • 0 in reply to Nihar Potturu
    Prodigy 50 points

    Hi Nihar Potturu,

    I understood your current comment about not being able to write after the DDR_inlineECCCfg function.

    But if I enable it after writing, the written value is cleared.

    What is the procedure for using ECC when the program is mapped to DDR?

    (The sample code is a program that places the program in the internal RAM and detects errors with ECC injection.)

    best regards,

    katsuyuki sasajima.

  • 0 in reply to Katsuyuki Sasajima
    TI__Mastermind 20376 points

    Hello Katsuyuki-san,

    Katsuyuki Sasajima said:
    What is the procedure for using ECC when the program is mapped to DDR?

    You have to fill the DDR with known values before enabling the ECC so that the reference ECC values are calculated on the known values. 

    The ECC has to be enabled before the application which is mapped to DDR is run so that when the application is loaded into DDR the ECC can be calculated for the application. We usually enable DDR ECC inside the DDR_init function in Stage-1 of bootloader. 

    Katsuyuki Sasajima said:
    But if I enable it after writing, the written value is cleared.

    What is the total size of your DDR? For how much region are you enabling ECC? What do you mean by the value is getting cleared? Can you please share the screenshots so that I can understand better.

    Regards,

    Nihar Potturu. 

  • 0 in reply to Nihar Potturu
    Expert 1540 points

    Hi, Nihar:

    I have a related  question. 

    Is enabling ECC protection for DDR an overkill in applications with high-bandwidth streaming data, such as video at 10 MB/s, where data changes constantly and error correction may introduce unnecessary overhead?

    Thanks

  • 0 in reply to Jun Tu
    TI__Guru* 86180 points

    Yes, you may not need ECC in video applications, since a 1-bit error may just result in a momentary wrong pixel value.  You would have to determine the effect of bit errors on the video.

    Regards,

    James