AM263P4: Questions on CAN CLK

Hello Kier,

Kier said:

Question 1: The register bit field suffix 'CLKDIV_SEL' in the diagram above cannot be found in the Register Addendum. Do you mean this to be: 'CLKDIVR' as shown below in the Register Addendum:

Yes - and this will be more clear in the next release of the RA we are working on.

Kier said:

Question 2: If so, what is the coding of the register bit field (CLKDIVR) to actual divider value? According to the description in the excerpt above, the divisor is 8 but I suspect that 1 is added to the register value to give 9 and therefore 9 is the divisor for the input frequency. Is that correct?

The field is a multi-bit field where you need to load multiple bits of data for the change to apply such as 0x222 or 0x555.

The formula is Divider = [n+1] so if you want a divider of 9, your 'n' input into the register is 8.

To handle the multi-bit aspect, this means you'd load 0x888 to get a divisor of 9.

Kier said:

Question 3: Are you sure that PLL_CORE_CLK:HSDIV0_CLKOUT0 is 500MHz as shown in the TRM below?

When I debug, it says 400Mhz:

The TRM is incorrect, it should be listing 400 MHz. I will file a bug to resolve that.

Best Regards,

Ralph Jacobi