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TMS570LC4357: Transmit DCAN with DMA

Zonguldak's Rose <3
Prodigy 141 points
Part Number: TMS570LC4357

Tool/software:

Hello,

I managed to receive CAN data via IF3 with DMA on the TMS570LC4357 microcontroller.

But I am trying to transmit data via IF1/IF2 on CAN using DMA. In this case, I see that DMA does not work.

I came across comments in some of your forum resources that IF1/IF2 registers are in "Privilege Mode" and DMA is in "User Mode", so they are not suitable for sending data.

Can you answer the following questions:
1- Isn't there a corresponding bit in the registers for using IF1/IF2 bits with DMA in the reference document I gave in the attachment? What kind of behavior occurs when I set them?
2- Also, what should I understand from the expression "High Speed ​​Mailbox Access - DMA Access to Message RAM" given in the attachment?
3- Isn't data transmitted via CAN with DMA?
4- If data transmission is not performed, what is the purpose of "DE1/DE2 bits in the CAN Controller Register"?
5- What is the use of "DMA Activate" on the IF1/IF2 CMD register?
6- Privilege mode comment was made for CAN IF1/IF2 Data registers, but when I examined the register, it was seen that it only said "Protected by Busy Bit". In this case, shouldn't I be able to use IF1/IF2 Busy bit with DMA when it is zero?

  • +1
    TI__Guru**** 196776 points

    the DCAN1 IF1 DMA request is triggered if it is enabled by the DE1 bit in the DCAN CTL register, additionally in the DCAN IF1CMD register the DMA Active bit needs to be set. Then the transfer from/to IF1 and message RAM needs to be triggered. Once the transfer completes the DMA request will be triggered. 

    The transfer between DCAN1 IF1 and Message RAM should be triggered manually by writing the message number to IF1CMD register.

    Zonguldak's Rose <3 said:
    2- Also, what should I understand from the expression "High Speed ​​Mailbox Access - DMA Access to Message RAM" given in the attachment?

    No, the message RAM can not be accessed by CPU and DMA in normal operating mode. 

    But can be accessed by CPU and DMA directly in test mode.

    Zonguldak's Rose <3 said:
    3- Isn't data transmitted via CAN with DMA?

    From the device TRM, the DMA is supported for data transfer between device memory and IFx data registers. But I haven't tried the DMA for IF1 and IF2.

    Zonguldak's Rose <3 said:
    What is the use of "DMA Activate" on the IF1/IF2 CMD register?

    It is to enable the DMA request after the transfer between IFx and Message RAM completes.

    Zonguldak's Rose <3 said:
    6- Privilege mode comment was made for CAN IF1/IF2 Data registers, but when I examined the register, it was seen that it only said "Protected by Busy Bit". In this case, shouldn't I be able to use IF1/IF2 Busy bit with DMA when it is zero?

    Have you tried to DMA transfer data to IFx data register using SW trigger in user mode and Busy=0?

  • 0 in reply to QJ Wang
    Prodigy 141 points

    I tried what you said before asking you the question. But I didn't get any results.

    I tried again after your answer. The steps are in the following order:
    1- I set the "DE1" bit for the IF1 DMA request on CAN 1.
    2- I performed the DMA setup.
    3- I checked the IF1 Busy bit.
    4- I set the IF1 CMD to write to the Data Registers (0x87).
    5- I used the DMA SW trigger after your answer.
    6- I set the "DMA Active" bit in the IF1 CMD registers on CAN1.
    7- I entered the message number on the IF1 CMD.

    When I perform the above steps, I can write my data in the system memory to the IF1DATAx registers as 1 frame. But for example, when I want to send 4-5 frames in a row with a single trigger, I have to repeat steps 3 to 7 each time. So I need to re-enter the message number on IF1 CMD.

    But what I understand on TRM is that when I manually trigger 1 between IF1 and Message RAM and set the "DMA Active" bit, I expect the remaining frames with the same message number to be completed without any triggering thanks to DMA HW (when I want to send 4 frames at once).

    In addition, I can write data to IF1DATAx records with DMA SW triggering, but I cannot write even 1 frame with DMA HW triggering. Shouldn't I be able to write to the records that I can access on SW by triggering with HW?

    When I trigger DMA by transmitting data between IF1 and the message RAM with 1 frame, what should I do to send the remaining frames I want to send (4 frames that I want to send at once) with DMA?

    Can you create an algorithm for me?

  • 0 in reply to Zonguldak's Rose <3
    TI__Guru**** 196776 points

    I just tried the same way. I am not able to make DMA work on IF1x either. 

    /*Enable DE1 bit in CTL register to trigger DMA when IF1 receives data*/
    canREG1->CTL |= (1U << 18U);

    /* - setting the dma channel to trigger on h/w request */
    dmaSetChEnable(DMA_CH0, DMA_HW);

    dmaReqAssign(DMA_CH0, DMA_REQ8); //DMA request DCAN1 IF1

    dmaEnable();

    /*Wait until IF1 is ready for use */
    while ((canREG1->IF1STAT & 0x80U) ==0x80U)
    {
    } /* Wait */

    /** - Configure IF1 for
    * - Message direction - Write
    * - Data Update
    * - Start Transmission
    */
    canREG1->IF1CMD = 0x87U;

    canREG1->IF1DATx[0] = 0xa8; //write 1st data manually


    /*Set DMA Active bit*/
    canREG1->IF1STAT = (1 << 6); 

    /*Copy TX data into message box 1 */
    canREG1->IF1NO = (uint8) 0x1;  //DMA Active bit is cleared

    /*Set DMA Active bit*/
    canREG1->IF1STAT = (1 << 6);

    /*Copy TX data into message box 1 */
    canREG1->IF1NO = (uint8) 0x1;

  • 0 in reply to QJ Wang
    TI__Guru**** 196776 points

    Using DMA for DCAN IF1/IF2 doesn't have much benefit because you have to manually program the message number to IFCMD register to trigger the message copy from IF1/IF2 registers to message RAM, and set the DMA Active bit manually in each DMA cycle.

    Please use CPU to write data to IFxDAT register instead of DMA. I am sorry for no-working DMA on IF1/IF2.

  • 0 in reply to QJ Wang
    Prodigy 141 points

    I understand. Thank you for your answer.

    Well, I see that DMA is triggered by hardware in the sample code you shared.
    Are you triggering it by hardware?

    I could not trigger it by hardware. I only trigger DMA by software.

  • 0 in reply to Zonguldak's Rose <3
    TI__Guru**** 196776 points

    Yes, the DMA channel 0 is configured to be triggered by HW. The DMA channel 0 is mapped to request line 8 which is DCAN1 IF1 (defined in datasheet). 

    I am not able to make the DMA work with the shared code. 

  • 0 in reply to QJ Wang
    Prodigy 141 points

    Hello again,

    I tried everything we discussed on TRM and the forum.

    As a result, while performing data transmission with DMA on IF1/IF2 over CAN, I managed to trigger DMA by software thanks to DMA SW. I managed to write data to IF1/IF2 Data Registers as 8 bytes.

    But I cannot trigger with DMA HW. If I set the "DMA Active" bit on IF1/IF2 CMD Register via the register tab on CCS, DMA HW is triggered and writes data to DMA IF1/IF2 Data Registers. When I set the "DMA Active" bit on software, DMA HW triggering does not occur. The "DMA Active" bit remains set until I access IF1/IF2 Register again.

    My question:
    If I set the "DMA Active" bit for DMA HW triggering via the "Registers" tab on the CCS, why is it that when the "DMA Active" bit is set in software, the DMA HW triggering does not occur?

    I am investigating this to reach a conclusion. If necessary, can you share a detailed code sample including the DMA board? Or I need a detailed explanation.

  • 0 in reply to Zonguldak's Rose <3
    TI__Guru**** 196776 points
    Zonguldak's Rose <3 said:
    If I set the "DMA Active" bit on IF1/IF2 CMD Register via the register tab on CCS, DMA HW is triggered and writes data to DMA IF1/IF2 Data Registers.

    Nice knowing you make DMA_HW trigger work through CCS register panel. 

    Zonguldak's Rose <3 said:
    can you share a detailed code sample including the DMA board?

    I don't have any working code.

    I am looking forward to hearing good news from you again!