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AM2434: How to set Interrupt Priority

Hideaki Matsumoto
Genius 9050 points
Part Number: AM2434

Tool/software:

Hi,

My customer is evaluating AM2434 by using the example code of tidep_01032_dual_motor_drive\single_chip_servo.

In the source code of Core 0 in this example code, interrupt is separated for ch1 and ch2.

When these interrupts are input at the same time, how the priority is configured ?

Is there any configuration parameter ?

　ch1：pruEncoderIrqHandler

　ch2：pruEncoderIrqHandler2

 

Thanks and regards,

Hideaki

  • 0
    TI__Genius 9050 points

    One more question, is it possible to unified these interrupts ? Can one interrupt control both ch1 and ch2 ?

    For example, pruEncoderIrqHandler executes both processing of ch1 and ch2.

    Thanks and regards,

    Hideaki

  • 0 in reply to Hideaki Matsumoto
    TI__Mastermind 38820 points

    Hi Matsumoto, please allow me some time as I have been out of office. I will come back to you in a day or two

    Thank you,

    Paula

  • 0 in reply to Paula Carrillo
    TI__Mastermind 38820 points

    Matsumoto-san,

    The priority of interrupts these interrupts is determined by the hardware. Lower interrupt numbers have higher priority. 

    Searching in "single_chip_servo.c" I found the following:

    ch1: hwiPrms.intNum      = ICSSG_PRU_ENDAT_INT_NUM; which correspond to "CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG0_PR1_HOST_INTR_PEND_0 (120U)"

    And ch2: hwiPrms.intNum      = ICSSG_PRU_ENDAT_INT_NUM + 2; which correspond to "CSLR_R5FSS0_CORE0_INTR_PRU_ICSSG0_PR1_HOST_INTR_PEND_2 (122U)"
    From AM243x TRM I see there are two prioritization levels. Channel number and Interrupt number. For both criteria "pruEncoderIrqHandler" should have the higher priority

    thank you,

    Paula

  • 0 in reply to Paula Carrillo
    TI__Genius 9050 points

    Hi Paula,

    Thank you so much for your answers. 

    Could you help to answer the following questions as well ?

    Hideaki Matsumoto said:

    One more question, is it possible to unified these interrupts ? Can one interrupt control both ch1 and ch2 ?

    For example, pruEncoderIrqHandler executes both processing of ch1 and ch2.

    Thanks and regards,

    Hideaki

  • 0 in reply to Hideaki Matsumoto
    TI__Mastermind 38820 points

    Matsumoto-san, I think it is the other way around. Several interrupts can be mapped to one channel, which I am guessing is the intend here. If I misunderstood, please let me know what they are trying to achieve so we can guide them better

    thank you,

    Paula

  • 0 in reply to Paula Carrillo
    TI__Genius 9050 points

    Hi Paula,

    Thank you so much for your answer.

    As I confirmed the customer's question, let me revise the following question.

    Hideaki Matsumoto said:

    One more question, is it possible to unified these interrupts ? Can one interrupt control both ch1 and ch2 ?

    For example, pruEncoderIrqHandler executes both processing of ch1 and ch2.

    Currently, ch1 interrupt is into R5F0_0 and ch2 into R5F0_1.

    　ch1：pruEncoderIrqHandler        ch2：pruEncoderIrqHandler2

    Is it possible to input both ch1 and ch2 interrupt into R5F0_0.?

    If it's possible, could you tell them how to modify the code ?

    They want to control both channels by one core.

    Thanks and regards,
    Hideaki 

  • 0 in reply to Hideaki Matsumoto
    TI__Mastermind 38820 points

    Hi Matsumoto, let me check internally and come back to you

    thank you,

    Paula

  • +1 in reply to Paula Carrillo
    TI__Mastermind 38820 points

    Matsumoto-san, one of our experts sent below information.

    There are three ways to do this: 

    1) we can generate same event number for both the axis 

    2) we can use different event number for both the axis and map it to same INTC channel (Here lowest INTC event number is given high priority 

    once, high event is served, lowest priority one should be served again) 

    3) we can use different event number for both axis and different INTC channel and same host Interrupt (Here lowest INTC channel number is given high priority)

    In order to implement 3rd case we can do the following in "tisddf_pruss_intc_mapping.h".

    tisddf_pruss_intc_mapping.h


    These are the event numbers, channel number, host Interrupt number used by both the axis, after making the changes :

    event_18 -> channel2 - > host Interrupt2 -> 120 (R5F0_0)
    event_20 -> channel4 -> host Interrupt2 -> 120 (R5F0_0)

    Also, please update application's EnDAT to use "hwiPrms.intNum" 120 for both Motors

    Please let us know if this works for your customer's use case

    thank you,

    Paula

  • 0 in reply to Paula Carrillo
    TI__Mastermind 38820 points

    Matsumoto-san, actually, below might not be needed as customer intention is to service both of the axis on same ISR in one R5F core.

    Paula Carrillo said:
    Also, please update application's EnDAT to use "hwiPrms.intNum" 120 for both Motors

    thank you,

    Paula