TM4C129XNCZAD: How to set up FIFO operation properly

Hi,

  You can enable by calling  UARTFIFOEnable(UART0_BASE). If you also enable the interrupt then by default an interrupt is generated when either the FXFIFO or RXFIFO is half empty. However, you can program the FIFO level by which to generate an interrupt. 

16.3.8 FIFO Operation
The UART has two 16x8 FIFOs; one for transmit and one for receive. Both FIFOs are accessed via
the UART Data (UARTDR) register (see page 1175). Read operations of the UARTDR register return
a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in
the transmit FIFO.

Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are
enabled by setting the FEN bit in UARTLCRH (page 1186).

FIFO status can be monitored via the UART Flag (UARTFR) register (see page 1180) and the UART
Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The

UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits), and the
UARTRSR register shows overrun status via the OE bit. If the FIFOs are disabled, the empty and
full flags are set according to the status of the 1-byte-deep holding registers.

The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO
Level Select (UARTIFLS) register (see page 1192). Both FIFOs can be individually configured to
trigger interrupts at different levels. Available configurations include ., ., ., ., and .. For example,
if the . option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data
bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the 1/2. mark.