Tool/software:
Hi, Ti Expert,
I am trying to evaluate EtherCAT slave on custom AM2434 board. I have built the beckhoff slave demo application but I am facing problem with slave state when DC feature is used. The setup involves an IGH EtherCAT master, with the DC cycle time set at 1ms. Upon initiating communication, the slave enters SAFEOP+ERROR state, and the al_status report "0x001A, Synchronization error", the slave fails to transition automatically into OP state. The system can only enter the OP state normally when the DC cycle time is set to 5 or 10 ms.
Im delving into the SSC source code, I'm confident that the aforementioned synchronization error should spontaneously resolve itself once the PDI_Isr() and Sync0_Isr() functions commence executing in an alternating pattern. However, during debugging sessions, I've noticed that the PDI_Isr function ceases execution precisely when the al_status signals "0x001A, Synchronization Error" while in SAFEOP state. To further analyze the situation, I resorted to using Wireshark for packet capturing, which confirmed that the EtherCAT data packets appear normal, suggesting no blatant transmission issues.
An interesting observation arises when utilizing TwinCAT3 as the EtherCAT master—while the same "0x001A, Synchronization Error" is occasionally flagged, the system has been known to self-correct and resume normal operation without intervention.
My primary query then revolves around understanding why the PDI_Isr() function fails to execute when the slave is in a SAFEOP + "0x001A, Synchronization Error." Could you shed some light on this behavior?
Looking forward to your insights. Best regards,
