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RM44L920: Flash and SRAM 2Bit ECC tests fail

Part Number: RM44L920

Tool/software:

Hi,

I'm working on implementing 2-bit ECC tests for Flash and SRAM using the Safety Diagnostic Library (SDL) and following the SDL demo example.

However, I'm encountering failures with these tests, and I'm having trouble identifying the cause.

retVal = SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_2BIT, TRUE, &failInfoTCMRAM); 
INCREMENT_PASS_FAIL_COUNTER(failInfoTCMRAM, retVal);
// failInfoTCMRAM = ST_FAIL

/* Run 2Bit ECC test on Flash */
retVal = SL_SelfTest_Flash(FLASH_ECC_TEST_MODE_2BIT, TRUE, &failInfoFlash);
INCREMENT_PASS_FAIL_COUNTER(failInfoFlash, retVal);
// failInfoFlash = ST_FAIL

Additionally, I've noticed that in the SDL demo example, a certain test is commented out in the sys_startup.c file. Could someone explain why this test is commented?

Is there a specific reason or condition for it to be disabled by default?

#if 0
/* Run Address tag mode test on Flash */
retVal = SL_SelfTest_Flash(FLASH_ECC_ADDR_TAG_REG_MODE, TRUE, &failInfoFlash);
INCREMENT_PASS_FAIL_COUNTER(failInfoFlash, retVal);
#endif

Thanks & regards,

Ilija

  • Hi Ilija,

    Apologies for the delay in late response.

    However, I'm encountering failures with these tests, and I'm having trouble identifying the cause.

    Can you please try to extract the code related to these two test cases and create a new project and can see the behavior once?

    Is there a specific reason or condition for it to be disabled by default?

    I don't know exact reason why they disabled it, i can check with my senior colleague once.

    However, this diagnostic is supported by this device:

    --
    Thanks & regards,
    Jagadish.

  • Hi Jagadish,

    I’m not quite sure I fully understand your suggestion:

    Can you please try to extract the code related to these two test cases and create a new project and can see the behavior once?

    Could you please clarify what you mean by this?
    I would appreciate a more detailed explanation.

    Thanks & regards,

    Ilija

  • Hi Ilija,

    I mean we can also extract the part of the code in SDL, so i am suggesting you copy the .c and .h files related to these tastings and try to create a new project.

    In this way we can simplify the project and can easily debug if anything not working in corresponding testing.

    --
    Thanks & regards,
    Jagadish.

  • Hi Jagadish,

    After further debugging, I've identified that only the Flash 2-bit ECC test is failing:

    /* Run 2Bit ECC test on Flash */
    retVal = SL_SelfTest_Flash(FLASH_ECC_TEST_MODE_2BIT, TRUE, &failInfoFlash);
    INCREMENT_PASS_FAIL_COUNTER(failInfoFlash, retVal);

    I also debugged the SDL Demo project, and I noticed that this test does not fail there.

    Could you please advise if there are any specific configurations or steps required for this test to pass? Unfortunately, I’m unable to create a new project due to time constraints.

    Thanks & regards,

    Ilija

  • Hi,

    I managed to resolve the issue with the 2-bit ECC testing for both Flash and RAM. It turns out the problem was that I didnt change the sys_intvecs.asm file as shown in the SDL Demo application. Once I made those changes, the tests ran successfully.

    ;-------------------------------------------------------------------------------
    ; sys_intvecs.asm
    ;
    ; Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
    ; 
    ; 
    ;  Redistribution and use in source and binary forms, with or without 
    ;  modification, are permitted provided that the following conditions 
    ;  are met:
    ;
    ;    Redistributions of source code must retain the above copyright 
    ;    notice, this list of conditions and the following disclaimer.
    ;
    ;    Redistributions in binary form must reproduce the above copyright
    ;    notice, this list of conditions and the following disclaimer in the 
    ;    documentation and/or other materials provided with the   
    ;    distribution.
    ;
    ;    Neither the name of Texas Instruments Incorporated nor the names of
    ;    its contributors may be used to endorse or promote products derived
    ;    from this software without specific prior written permission.
    ;
    ;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
    ;  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
    ;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
    ;  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
    ;  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
    ;  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
    ;  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    ;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    ;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
    ;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
    ;  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    ;
    ;
    ;
    
        .sect ".intvecs"
        .arm
    
    ;-------------------------------------------------------------------------------
    ; import reference for interrupt routines
    
        .ref _c_int00
        .ref vPortSWI
        .ref _excpt_vec_udef_instr
        .ref _excpt_vec_abort_pref
        .ref _excpt_vec_abort_data
        .ref phantomInterrupt
        .def resetEntry
    
    ;-------------------------------------------------------------------------------
    ; interrupt vectors
    
    resetEntry
            b   _c_int00
    undefEntry
            b   _excpt_vec_udef_instr
            b   vPortSWI
    prefetchEntry
            b   _excpt_vec_abort_pref
            b   _excpt_vec_abort_data
            b   phantomInterrupt
            ldr pc,[pc,#-0x1b0]
            ldr pc,[pc,#-0x1b0]
    
        
    ;-------------------------------------------------------------------------------
    

    Thanks & regards,

    Ilija