Tool/software:
Dear staff,
We are receiving unexpected Data Aborts in our development on R5 core, which are quite undeterministic in their occurrences and disappear when cache is disabled.
We believe that the following limitation might be the root cause:
(from Technical Reference Manual SPRUJ17H Oct 2024, page 63)
Due to MPU architecture limitation, in case of a Cacheable access from R5 CPU, if the cache
line(32Byte) access falls in the last 32Bytes of the MPU region, the MPU incorrectly indicates an
access fault. Hence it is recommended that the application does not perform a cacheable access on
the last 32Bytes of an MPU region. This limitation does not exist for non Cacheable access from R5 or
any access from non R5 initiators.
We'd need to work out a way to circumvent that limitation, and we were wondering if there is any "standard" way to proceed.
Also, we have noticed that that item is not reported in the Errata document. Did we miss anything, or is it "standard feature"?
Thank you in advance,
Kind regards,
Orazio
