TMS570LS0714: How does the MCU Handle BANK 7 faulty accesses (ECC Errors)?

Tool/software:

Question to be cleared - How does the MCU Handle BANK 7 faulty accesses (ECC Errors)?

1. ESM Group 2 - Channel 36: Refers to “36 FMC - uncorrectable ECC error (Bank 7 access)”. Leading to a high level interrupt which is handled through - esmActionFatal(); (which leads to a while true condition killing the processor). Also asserts the ERROR Pin.

2. ESM Group 3 - Channel 7: Refers to “FMC - uncorrectable ECC error: bus1 and bus2 interfaces (does not include address parity error and errors on accesses to Bank 7)”.

   1. These channels have no interrupt response as they are reserved for CPU based diagnostics that generate aborts directly to the CPU.

3. However in the legacy testing of the system start-up c_int00 function, there is a test which forces deliberate ECC Errors (section 5.4.2.5 of the TRM) by reading from BANK0 - OTP. This function looks specifically to see if such error was signaled to the ESM Group 3 - Channel 7 in order to pass the test.

4. Moreover, for ESM Group3 - Channel 7: FMC - uncorrectable error: bus1 and bus2 interfaces:

   1. For Bus2, the ECC error is detected by the flash wrapper itself when accessing OTP space and ECC space. There is no data abort. Only error is sent to the ESM. nERROR pin is asserted.

   2. Bus2 handles both OTP Bank 0 and Bank 7.

5. When trying to perform the same test in step 3. I do not get a full system reset.

   1. I believe this is due to the fact that Group 3 Events do not generate a high level interrupt, meaning they do not get handled by our handlers (esmActionFatal()); Is this correct?

   2. There is however signaling to the ESM Group 3 - Channel 7 and nERROR Pin is asserted. We currently are not using the nERROR Pin in our application's HW.

6. The final question is, what would be the expected behavior if an uncorrectable ECC error was detected on a BANK7 access?

   1. I’m guessing a CPU data abort wouldn’t be generated since bank 7 is handled through Bus2. Is this correct?

   2. What would then be the behavior ? Would the ESM Group 2 - Channel 36 be signaled or the ESM Group 3 - Channel 7, or both?

      1. If the first option is correct, the handler esmActionFatal(); would be called, killing the processor. NERROR Pin is asserted.

      2. If the second option is correct, no handler would be called, since Group 3 events do not generate interrupts. NERROR Pin is asserted.

      3. If both, the handler esmActionFatal(); would be called due to the Group 2 interrupt killing the processor and NERROR Pin would be asserted.

Thank you very much for your support.

Martin Estorninho Blocher