Tool/software:
With reference to SPNU515C
The Field Descriptions for SPI Pin Control Register 0 (SPIPC0) states the following:
Note: Duplicate Control Bits for SPISOMI[0]. Bit 24 is not physically implemented. It is a
mirror of Bit 11. Any write to bit 24 will be reflected on bit 11. When bit 24 and bit 11 are
simultaneously written, the value of bit 11 will control the SPISOMI[0] pin. The read value of
bit 24 always reflects the value of bit 11.
Similar text is included regarding bit 16 and bit 10.
The Field Descriptions for SPI Pin Control Register 1 (SPIPC1) include similar statements relating to bits 16 and 24.
The Field Descriptions for SPI Pin Control Registers 3-8 have different text.
For example, the Field Descriptions for SPI Pin Control Register 8 (SPIPC8) states the following:
Note: Bit 11 or bit 24 can be used to set pull-select for SPISOMI[0]. If a 32-bit write is
performed, bit 11 will have priority over bit 24.
My question: For SPI Pin Control Registers 3-8, is it also the case that the read value of bit 24 always reflects the value of bit 11 and the read value of
bit 16 always reflects the value of bit 10?
