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AM2634-Q1: ucc5880-q1

Part Number: AM2634-Q1
Other Parts Discussed in Thread: AM2634

Tool/software:

Hi,

Our understanding with ESM module configuration for core failure is as below.

1. If ESM detects the Core0 error, it will raise NERROR output.

2. If Core1 is active at this time, it should clear the NERROR status, it has to be explicitly handled by Core1

     - With NERROR of AM2634 connected to ERROR pin on PMIC TPS6528860A,  we don't PMIC to reset the controller if Core0 has failed and Core1 is still working well.

Whereas we were expecting that only when both the cores are in error state,

ESM module should have triggered the NERROR output.

Is this possible to achieve? Can we configure ESM to do that ?

Regards

Sunil

  • Hi Sunil,

    The ESM aggregates all safety related events from throughout the SoC and gives out pulls down the "SAFETY_ERRORn" pin in case of a severe error. The device doesn't have an internal circuitry to AND/OR ESM errors for "SAFETY_ERRORn" pin.