Using PLL at 50Mhz locks up device

B M

I am using a dev kit DK-LM3S815 (http://www.ti.com/lit/ml/spmu148/spmu148.pdf)

Here is the messages during an programming using JLINK:-

Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\config\flashloader\TexasInstruments\FlashLM3Sxxx.mac
JLINK command: ProjectFile = C:\start_Debug.jlink, return = 0
JLINK command: device = LM3S815, return = 0
DLL version: V4.20m, compiled Oct 28 2010 09:07:34
Firmware: J-Link Ultra Rev.1 compiled Feb 8 2011 17:39:33
JTAG speed is initially set to: 32 kHz
TotalIRLen = 4, IRPrint = 0x01
Found Cortex-M3 r0p1, Little endian.
TPIU fitted.
FPUnit: 6 code (BP) slots and 2 literal slots
Hardware reset with strategy 0 was performed
Initial reset was performed
Found 1 JTAG device, Total IRLen = 4:
#0 Id: 0x2BA00477, IRLen: 4, IRPrint: 0x1 CoreSight JTAG-DP
Turning off watchdog
392 bytes downloaded and verified (0.87 Kbytes/sec)
Loaded debugee: C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\config\flashloader\TexasInstruments\FlashLM3SxxxRAM8K.out
Target reset

Downloaded c.out to flash memory.
TotalIRLen = 4, IRPrint = 0x01
Found Cortex-M3 r0p1, Little endian.
TPIU fitted.
FPUnit: 6 code (BP) slots and 2 literal slots
Hardware reset with strategy 0 was performed
21260 bytes downloaded into FLASH and verified (9.49 Kbytes/sec)
Loaded debugee: c.out
TotalIRLen = 4, IRPrint = 0x01
Found Cortex-M3 r0p1, Little endian.
TPIU fitted.
FPUnit: 6 code (BP) slots and 2 literal slots
Hardware reset with strategy 0 was performed
Target reset

I set the clock to 50Mhz using PLL:-

SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_6MHZ);

When I debug the system will lock up. So when I try to debug again using JLINK the popup message appears

Wrong AHB ID (15:3). Expected 0x04770001 (Mask 0x0FFFFFFF), Found 0x00000000

and the Debug Log within IAR is

Loaded macro file: C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\config\flashloader\TexasInstruments\FlashLM3Sxxx.mac
JLINK command: ProjectFile = start_Debug.jlink, return = 0
JLINK command: device = LM3S815, return = 0
DLL version: V4.20m, compiled Oct 28 2010 09:07:34
Firmware: J-Link Ultra Rev.1 compiled Feb 8 2011 17:39:33
JTAG speed is initially set to: 32 kHz
TotalIRLen = 4, IRPrint = 0x01
Found Cortex-M3 r0p1, Little endian.
TPIU fitted.
FPUnit: 6 code (BP) slots and 2 literal slots
SYSRESETREQ has confused core. Trying to reconnect and use VECTRESET.
CPU did not halt, trying to disable WDT.
Core did not halt after reset, trying to disable WDT.
CPU did not halt, trying to disable WDT.
Core did not halt after reset, trying to disable WDT.
CPU did not halt, trying to disable WDT.
Fatal error: Wrong AHB ID (15:3). Expected 0x04770001 (Mask 0x0FFFFF0F), Found 0x00000000 Session aborted!
Failed to load flash loader: C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\config\flashloader\TexasInstruments\FlashLM3SxxxRAM8K.out
Failed to load flash loader: C:\Program Files\IAR Systems\Embedded Workbench 6.0\arm\config\flashloader\TexasInstruments\FlashLM3S8xx.flash

What is causing the problem?

Thanks,

Liam

over 13 years ago

0 cb1_mobile over 13 years ago

Guru 117855 points

Have paid version of IAR (6.21.4) - experienced very similar to your "Fatal error: Wrong AHB ID (15:3)" error.

Now this happened as we made initial attempt moving from LM3S16xx to brand new LM4F232H5Q - was caused by my improper "mating" of this new M4 MCU to IAR's "Project -> Options -> Target -> Device," set-up. As you are using the more established 3S815 device - we must ask what you have "most recently" changed to generate this error. As always - make careful scrutiny of all of your JTAG pins - their pull-up Rs and routings. Is this a one board issue - always wise to see if you've a single or multi-board problem.

Your post links this issue to 50MHz - does this problem resolve at lower speeds? (I doubt that) Do test @ lower speeds and kindly report - good luck.

0 B M over 13 years ago in reply to cb1_mobile

Prodigy 210 points

I am using standard off the shelf components (IAR J-Link and LM3S815 Development Kit) and have not made any modifications to these.

I have checked to ensure that the correct device is selected in "Project -> Options -> Target -> Device," - TexasInstruments LM3S815

I have this working when using the external oscillator. When I try to configure it to use PLL at any frequency (SYSCTL_SYSDIV_1 through SYSCTL_SYSDIV_16) then it locks up. This is a consistent and repeatable problem.

Device Identification

DID0=0x00000200
MINOR=0x00
MAJOR=0x02
VER=0x0

Liam

0 cb1_mobile over 13 years ago in reply to B M

Guru 117855 points

Wow - Ai carumba - sorry about that. We have been using IAR, Stellaris (and others) w/J-Link (since 2006) and "never" experienced your issue - and always used PLL and xtal.

Is it possible that your xtal is mis-marked - or that xtal/bypass cap traces have an issue? (or that the xtal freq is not matched to your command) We've used LM3S, 6S and 8S hundreds of times - again never encountered an issue.

Kindly expand upon,

LiamD said:
When I try to configure it to use PLL

Are you implying that operation is normal when you use the board's external xtal - and that it only fails when you engage the PLL?

You've used an external osc - perhaps there is a shunt/jumper mechanism to "steer" the external osc into MCU's Osc0 or Osc1 - and that this "breaks" the connection between xtal and these pins.

LiamD said:
This is a consistent and repeatable problem.

Yes but across how many boards? (one board anomaly "not as vital/compelling" as multi board (i.e. real) issue)

Suggest you swap xtal, bypass C's between this board and some working (known good) board - then re-test...

*** Final thought - perhaps MCU errata sheds light - recall that in past the LDO voltage had to be tweaked (raised) to solve somewhat related issues...

0 Stellaris Mitch over 13 years ago in reply to B M

TI__Intellectual 2790 points

Hi Liam,

The ClockSet call looks fine and I verified the external crystal is 6MHz on that board from the schematic. If you are not already using one, can you verify if this is also reproducible with the example applications? It looks like the quick-start example is already configured to use PLL but the others would need to be modified.

Also, can you provide the Rev for the LM3S815 part on the board?

0 B M over 13 years ago in reply to Stellaris Mitch

Prodigy 210 points

cb1_mobile,

cb1_mobile said:

Kindly expand upon,
When I try to configure it to use PLL

[/quote]

I am using the call to :-

SysCtlClockSet(SYSCTL_SYSDIV_16 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN |
SYSCTL_XTAL_6MHZ);

cb1_mobile said:

Are you implying that operation is normal when you use the board's external xtal - and that it only fails when you engage the PLL?

Yes everything works fine when I use the external xtal.

cb1_mobile said:

Yes but across how many boards? (one board anomaly "not as vital/compelling" as multi board (i.e. real) issue)

I only have one development kit to test.

Stellaris Mitch,

Stellaris Mitch said:

If you are not already using one, can you verify if this is also reproducible with the example applications?

I can confirm that I get the problem when I execute the test application qs_dk-lm3s811.c at revision 5961:

// qs_dk-lm3s811.c - A quick start sample application to demo chip features

// This is part of revision 5961 of the DK-LM3S811 Firmware Package.

I did change the Debugger from TI Stellaris FTDI to J-Link/J-Trace. If I use TI Stellaris FTDI then I can successfully connect to the board. But if I use the J-Link debugger then I fail to connect to the board.

Stellaris Mitch said:

Also, can you provide the Rev for the LM3S815 part on the board?

Not sure how to determine the revision of the LMS815. In the above posts I have:

Found Cortex-M3 r0p1, Little endian.

Device Identification

DID0=0x00000200
MINOR=0x00
MAJOR=0x02
VER=0x0

Is this sufficient information for the revision?

Thanks,

Liam

0 cb1_mobile over 13 years ago in reply to B M

Guru 117855 points

As I also have IAR 6.21.4 (paid version) here are pertinent screen shots - you may wish to compare/contrast these with yours. (in reviewing these - I did not set the CPU clock to 72MHz w/in Screen "3" JLink Setup. System does work well - both debug and download/program. Hope this provides some aid/assistance.