Tool/software:
Hi.
In asynchronous operation with caches disabled, a GPMC write such as *((uint32_t*)0x50000000u) = 0xAAAAAAAAu; produces a dummy access whose presence is not expected. It consists of an access without either REn or WEn asserted that always accompanies the expected write operation. It occurs for any access size (8, 16 or 32-bit).
Why does this occur? Is this a known behavior? Can this dummy access be avoided?
Regards,
Luís
GPMC Configuration is as follows:
/* CONFIG1 register config */
// WRAPBURST[31] = 0 = Synchronous wrapping burst not supported
// READMULTIPLE[30] = 0 = Single access
// READTYPE[29] = 0 = Read asynchronous
// WRITEMULTIPLE[28] = 0 = Single access
// WRITETYPE[27] = 0 = Write asynchronous
// CLKACTIVATIONTIME[26:25] = 00 = First rising edge of GPMC CLK at start access time
// ATTACHEDDEVICEPAGELENGTH[24:23] = 00 = 4 words
// WAITREADMONITORING[22] = 0 = WAIT pin is not monitored for read accesses
// WAITWRITEMONITORING[21] = 0 = WAIT pin is not monitored for write accesses
// WAITMONITORINGTIME[19:18] = 00 = WAIT pin is monitored with valid data
// WAITPINSELECT[17:16] = 00 = Wait input pin is WAIT0
// DEVICESIZE[13:12] = 10 = 32 bits
// DEVICETYPE[11:10] = 00 = NOR flash-like, asynchronous and synchronous devices
// MUXADDDATA[9:8] = 10 = Address and data multiplexed attached device
// TIMEPARAGRANULARITY[4] = 0 = x1 latencies
// GPMCFCLKDIVIDER[1:0] = 11 = GPMC_FCLK frequency / 4
/* CONFIG2 register config */
// CSWROFFTIME[20:16] = 00010 = 2 GPMC_FCLK cycle [CSi deassertion time from start cycle time for write accesses]
// CSRDOFFTIME[12:8] = 00010 = 2 GPMC_FCLK cycle [CSi de-assertion time from start cycle time for read accesses]
// CSEXTRADELAY[7] = 0 = CSi Timing control signal is not delayed
// CSONTIME[3:0] = 0000 = 0 GPMC_FCLK cycle [CSi assertion time from start cycle time]
/* CONFIG3 register config */
// ADVAADMUXWROFFTIME[30:28] = 000 = 0 GPMC_FCLK cycle
// ADVAADMUXRDOFFTIME[26:24] = 000 = 0 GPMC_FCLK cycle
// ADVWROFFTIME[20:16] = 00000 = 0 GPMC_FCLK cycle [nADV deassertion time from start cycle time for write accesses]
// ADVRDOFFTIME[12:8] = 00000 = 0 GPMC_FCLK cycle [nADV deassertion time from start cycle time for read accesses]
// ADVEXTRADELAY[7] = 0 = nADV timing control signal is not delayed
// ADVAADMUXONTIME[6:4] = 000 = 0 GPMC_FCLK cycle
// ADVONTIME[3:0] = 0001 = 1 GPMC_FCLK cycle [nADV assertion time from start cycle time]
/* CONFIG4 register config */
// WEOFFTIME[28:24] = 00010 = 2 GPMC_FCLK cycle [nWE deassertion time from start cycle time]
// WEEXTRADELAY[23] = 0 = nWE timing control signal is not delayed
// WEONTIME[19:16] = 0001 = 1 GPMC_FCLK cycle [nWE assertion time from start cycle time]
// OEAADMUX_OFFTIME[15:13] = 000 = 0 GPMC_FCLK cycle
// OEOFFTIME[12:8] = 00010 = 2 GPMC_FCLK cycle [nOE deassertion time from start cycle time]
// OEEXTRADELAY[7] = 0 = nOE timing control signal is not delayed
// OEAADMUX_ONTIME[6:4] = 000 = 0 GPMC_FCLK cycle
// OEONTIME[3:0] = 0000 = 0 GPMC_FCLK cycle [nOE assertion time from start cycle time]
/* CONFIG5 register config */
// PAGEBURSTACCESSTIME[27:24] = 0000 = 0 GPMC_FCLK cycle
// RDACCESSTIME[20:16] = 00010 = 2 GPMC_FCLK cycle [Delay between start cycle time and first data valid]
// WRCYCLETIME[12:8] = 00010 = 2 GPMC_FCLK cycle [Total write cycle time]
// RDCYCLETIME[4:0] = 00010 = 2 GPMC_FCLK cycle [Total read cycle time]
/* CONFIG6 register config */
// RESERVED[31] = 1h = TI Internal use - Do not modify
// WRACCESSTIME[28:24] = 00001 = 1 GPMC_FCLK cycle [Delay from start access time to the GPMC_FCLK rising edge corresponding the GPMC CLK rising edge used by the attached memory for the first data capture]
// WRDATAONADMUXBUS[19:16] = 0001 = 1 GPMC_FCLK cycle [Specifies on which GPMC_FCLK rising edge the first data of the write is driven in the add/data mux bus]
// CYCLE2CYCLEDELAY[11:8] = 0001 = 1 GPMC_FCLK cycle [Chip-select high pulse delay between successive accesses]
// CYCLE2CYCLESAMECS[7] = 1 = Add CYCLE2CYCLEDELAY [Add CYCLE2CYCLEDELAY between successive accesses to the same chip-select (any access type)]
// CYCLE2CYCLEDIFFCSE[6] = 1 = Add CYCLE2CYCLEDELAY [Add CYCLE2CYCLEDELAY between successive accesses to a different chip-select (any access type)]
// BUSTURNAROUND[3:0] = 0000 = 0 GPMC_FCLK cycle [Bus turnaround latency between successive accesses to the same chip-select (read to write) or to a different chip-select (read to read and read to write)]
/* CONFIG7 register config */
// MASKADDRESS[11:8] = 1111 = Chip-select size of 16MB
// CSVALID[6] = 1 = CS enabled
// BASEADDRESS[5:0] = 010000 = Base address is 0x50000000 (bits [31:30] are always 01 and bits [29:24] are specified here)
